Wafer preparation method for improving alignment accuracy during semiconductor probe card bonding

Abstract

The application provides a wafer preparation method for improving alignment accuracy during semiconductor probe card bonding, comprising the following steps: forming M first etching positions on a silicon substrate by photoetching on an upper oxide layer; etching the first etching positions to form M needle tip growth positions; removing the first photoresist layer; forming a titanium-copper alloy layer on the surface of the needle tip growth positions and the upper oxide layer; forming a needle body growth position above the needle tip growth position by photoetching on the titanium-copper alloy layer; forming probes on the needle tip growth positions and the needle body growth positions; forming a first circuit pattern on the upper surfaces of all the probes by photoetching; forming a gold layer by electroplating on the first circuit pattern; forming a limiting block growth position beside N probes by photoetching; forming a limiting block on each limiting block growth position; and removing all the photoresist layers to obtain a wafer. The wafer preparation method for improving alignment accuracy during semiconductor probe card bonding can realize accurate bonding of the wafer and a ceramic sheet, improve product yield, and reduce cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a wafer fabrication method for improving alignment accuracy during semiconductor probe card bonding. Background Technology

[0002] A probe card is a key component used for front-end semiconductor wafer testing, enabling electrical connection between the wafer chip and the testing machine. It consists of multiple probes that test the electrical performance of the wafer chip by contacting it.

[0003] MEMS probe cards are a new type of probe card manufactured using microelectromechanical systems (MEMS) technology. MEMS probes utilize microfabrication techniques to integrate over 100k pins within a single probe card, meeting the testing needs of electronic devices. The probe card consists of a wafer and a ceramic sheet, which are bonded together using a bonding process during fabrication.

[0004] However, existing fabrication processes cannot achieve precise alignment between the ceramic wafer and the wafer during bonding. On one hand, the positioning equipment used for alignment lacks precision, leading to deviations in the positional calibration of the ceramic wafer and the wafer, failing to meet the high-precision alignment standards required for bonding. On the other hand, the skill level of the operators and the adherence to standardized operating procedures also significantly impact alignment accuracy. Inexperienced operators or failure to strictly follow standard procedures can easily introduce additional errors when adjusting the positions of the ceramic wafer and the wafer, affecting alignment accuracy and resulting in inaccurate alignment before bonding. Inaccurate alignment leads to poor bonding, affecting product yield and wasting significant manpower and material resources in upstream processes. This not only impacts production efficiency but also increases production costs and reduces economic benefits. Summary of the Invention

[0005] This invention provides a wafer fabrication method that improves alignment accuracy during semiconductor probe card bonding, enabling precise bonding between wafers and ceramic sheets, improving product yield, and reducing costs.

[0006] To address the aforementioned technical problems, this invention provides a wafer fabrication method for improving alignment accuracy during semiconductor probe card bonding, comprising the following steps:

[0007] Step 10: An upper oxide layer is formed on the upper surface of the silicon substrate, and a lower oxide layer is formed on the lower surface of the silicon substrate; and photoresist is coated on the upper surface of the upper oxide layer to form a first photoresist layer.

[0008] Step 20: Expose and develop the M first preset positions of the first photoresist layer to form M first etch sites; M is an integer greater than or equal to 2;

[0009] Step 30: Etch the upper oxide layer and silicon substrate directly below each first etch site sequentially to form M tip growth sites; remove the first photoresist layer;

[0010] Step 40: A titanium-copper alloy layer is formed on the surface of the tip growth site and the upper surface of the upper oxide layer using a sputtering process; and photoresist is coated on the upper surface of the titanium-copper alloy layer to form a second photoresist layer; the M second preset positions of the second photoresist layer are exposed and developed to form a needle body growth site above each tip growth site.

[0011] Step 50: An electroplating process is used to form a first nickel-cobalt alloy layer at M tip growth sites and needle body growth sites. The first nickel-cobalt alloy layer is then planarized to form M probes.

[0012] Step 60: Apply photoresist to the upper surface of all probes and the upper surface of the retained second photoresist layer to form a third photoresist layer; expose and develop the M third preset positions of the third photoresist layer to form a first circuit pattern above each probe; electroplate M gold layers on the M first circuit patterns.

[0013] Step 70: Apply photoresist to the upper surface of all gold layers and the retained third photoresist layer to form a fourth photoresist layer; after exposing and developing the N fourth preset positions of the fourth photoresist layer, form limiting block growth sites next to the N probes respectively; N is an integer greater than or equal to 1;

[0014] Step 80: At each growth site of the limiting block, a second nickel-cobalt alloy layer is formed on the titanium-copper alloy layer by electroplating. The second nickel-cobalt alloy layer is then planarized to form N limiting blocks.

[0015] Step 90: Remove all photoresist layers to obtain a wafer.

[0016] As a further improvement of the present invention, step 90, before removing all photoresist layers, further includes:

[0017] A photoresist is coated on the lower surface of the lower oxide layer to form a fifth photoresist layer; the fifth preset position of the fifth photoresist layer is exposed and developed to form a second circuit pattern around each probe tip and a third circuit pattern under each gold layer; the lower oxide layer, silicon substrate and upper oxide layer corresponding to each second circuit pattern are etched in sequence to form M exposure positions; the lower oxide layer, silicon substrate and upper oxide layer corresponding to each third circuit pattern are etched to form M detection positions.

[0018] As a further improvement of the present invention, the ratio of N to M is 6 to 8:100.

[0019] As a further improvement of the present invention, the thickness of the limiting block is 80-100µm.

[0020] As a further improvement of the present invention, in step 30, the first photoresist layer is removed by plasma etching, and isopropanol is used to remove organic matter from the tip growth site and the surface of the upper oxide layer.

[0021] As a further improvement of the present invention, in step 40, the thickness of the second photoresist layer is 80-90µm.

[0022] As a further improvement of the present invention, in step 50, before electroplating, a plasma surface treatment method is first used to treat the surface of the needle growth site, and dilute sulfuric acid is used for pretreatment.

[0023] As a further improvement of the present invention, in step 60, the thickness of the gold layer is 1 ± 0.5 µm.

[0024] As a further improvement of the present invention, in step 80, before electroplating, a plasma surface treatment method is first used to treat the surface of the growth site of the limiting block.

[0025] As a further improvement to the present invention, it also includes:

[0026] Step 100: Based on the positioning of the limiting block, the gold layer of the wafer is bonded to the ceramic sheet; the titanium-copper alloy layer is etched to remove the silicon substrate and the limiting block.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] This invention provides a wafer fabrication method to improve alignment accuracy during semiconductor probe card bonding. By forming N limiting blocks on the wafer, these blocks act as positioning elements during the bonding of ceramic wafers to the wafer, achieving precise bonding between the wafer and ceramic wafer, improving product yield, and reducing costs. During wafer fabrication, the existing process is used to prepare the probes. After all probes are formed, the limiting blocks are then selectively prepared next to the N probes, without altering the original probe fabrication process. Since the limiting blocks are formed on a titanium-copper alloy layer, after the wafer and ceramic wafer are bonded, the limiting blocks can be etched off from the silicon substrate along with the silicon wafer, preventing them from remaining on the probe card. Attached Figure Description

[0029] Figure 1 This is a flowchart of a wafer fabrication method according to an embodiment of the present invention.

[0030] The diagram shows: silicon substrate 1, upper oxide layer 21, lower oxide layer 22, first photoresist layer 3, first etch site 4, tip growth site 5, titanium-copper alloy layer 6, needle growth site 9, second photoresist layer 11, probe 12, third photoresist layer 15, gold layer 16, fourth photoresist layer 17, limit block growth site 18, limit block 19, fifth photoresist layer 20, exposure site 13, and detection site 14. Detailed Implementation

[0031] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] The terms “first,” “second,” “third,” “fourth,” etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order.

[0033] This invention provides a wafer fabrication method to improve alignment accuracy during semiconductor probe card bonding, such as... Figure 1 As shown, it includes the following steps:

[0034] Step 10: An upper oxide layer 21 is formed on the upper surface of the silicon substrate 1, and a lower oxide layer 22 is formed on the lower surface of the silicon substrate 1. Oxide layers are formed on both the upper and lower surfaces of the silicon substrate 1 to provide insulation and prevent current from flowing to unwanted parts and causing a short circuit. Photoresist is coated on the upper surface of the upper oxide layer 21 to form a first photoresist layer 3.

[0035] Step 20: Expose and develop the M preset positions on the first photoresist layer 3 to form M first etched positions 4. Here, M is an integer greater than or equal to 2. The number of M varies depending on the probe card specifications.

[0036] Step 30: The upper oxide layer 21 and the silicon substrate 1 directly below each first etch site 4 are etched sequentially, specifically using a wet oxidation etching process to form M needle-tip growth sites 5.

[0037] Remove the first photoresist layer 3. Specifically, the first photoresist layer 3 is removed by plasma etching, and isopropanol is used to remove organic matter from the tip growth site 5 and the surface of the upper oxide layer 21.

[0038] Step 40: A titanium-copper alloy layer 6 is formed on the surface of the tip growth site 5 and the upper surface of the upper oxide layer 21 using a sputtering process. Photoresist is then applied to the upper surface of the titanium-copper alloy layer 6 to form a second photoresist layer 11. Preferably, the thickness of the second photoresist layer 11 is 80–90 µm. M second preset positions of the second photoresist layer 11 are exposed and developed to form a needle growth site 9 above each tip growth site.

[0039] Step 50: An electroplating process is used to form a first nickel-cobalt alloy layer on M tip growth sites 5 and needle body growth sites 9. The first nickel-cobalt alloy layer is then planarized to form M probes 12. Each probe 12 includes a needle body and a tip located below the needle body.

[0040] Preferably, before electroplating, the surface of the needle growth site 9 is treated with a plasma surface treatment method and pretreated with dilute sulfuric acid to remove residual organic matter on the surface of the needle growth site 9.

[0041] Step 60: Photoresist is applied to the upper surface of all probes 12 and the upper surface of the retained second photoresist layer 11 to form a third photoresist layer 15. The third photoresist layer 15 is exposed and developed at M predetermined third positions to form a first circuit pattern above each probe 12. M gold layers 16 are electroplated onto the M first circuit patterns. The orthographic projection of the gold layer 16 onto the silicon substrate 1 occupies only a small portion of the orthographic projection of the probe onto the silicon substrate. Preferably, the thickness of the gold layer 16 is 1 ± 0.5 µm.

[0042] Step 70: Photoresist is applied to the upper surfaces of all gold layers 16 and the retained third photoresist layer 15 to form a fourth photoresist layer 17. After exposure and development at N predetermined positions of the fourth photoresist layer 17, limiting block growth sites 18 are formed next to the N probes 12. Here, N is an integer greater than or equal to 1. Preferably, the ratio of N to M is 6 to 8:100.

[0043] Step 80: A second nickel-cobalt alloy layer is formed on the titanium-copper alloy layer 6 at each limiting block growth position 18 using an electroplating method. The second nickel-cobalt alloy layer is then planarized to form N limiting blocks 19.

[0044] Preferably, if the limiting block 19 is too thick, it will warp up and affect the product quality; if it is too thin, it will not be able to abut against the components on the ceramic sheet and will affect the positioning function.

[0045] Step 90: Remove all photoresist layers to obtain a wafer.

[0046] Preferably, before removing all photoresist layers, the process further includes:

[0047] Photoresist is applied to the lower surface of the lower oxide layer 22 to form a fifth photoresist layer 20. The fifth photoresist layer 20 is exposed and developed at a fifth predetermined position, forming a second circuit pattern around the tip of each probe 12 and a third circuit pattern below each gold layer 16. The lower oxide layer 22, silicon substrate 1, and upper oxide layer 21 corresponding to each second circuit pattern are etched sequentially to form M exposure positions 13. This exposes the probe tips, facilitating inspection to ensure they meet requirements. The lower oxide layer 22, silicon substrate 1, and upper oxide layer 21 corresponding to each third circuit pattern are etched to form M detection positions 14. Inspection at the detection positions 14 allows for verification of the gold layer 16's integrity, preventing subsequent bonding defects caused by abnormalities in the gold layer 16.

[0048] Step 100: Based on the positioning of the limiting block 19, the gold layer 16 of the wafer is bonded to the ceramic sheet.

[0049] The titanium-copper alloy layer 6 is etched to remove the silicon substrate 1 and the limiting block 19. Specifically, the bonded product is placed in a Wet Station equipment for a Lift-Off process, where it is immersed in a sulfuric acid solution to cause the titanium-copper alloy layer 6 to chemically react and detach, thereby automatically separating the silicon substrate 1, the upper oxide layer 21, the lower oxide layer 22, and the limiting block 19 from the probe 12.

[0050] The wafer fabrication method of this invention forms N limiting blocks on the wafer, which act as positioning blocks during the bonding of ceramic wafers to the wafer, achieving precise bonding between the wafer and the ceramic wafer, improving product yield, and reducing costs. During wafer fabrication, the existing process is used to fabricate probes. After all probes are formed, the limiting blocks are then selectively fabricated next to the N probes, without changing the original probe fabrication process. The limiting blocks are formed on a titanium-copper alloy layer. After the wafer and ceramic wafer are bonded, the limiting blocks can be peeled off from the wafer along with the silicon substrate by etching the titanium-copper alloy layer, without remaining on the probe card.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A wafer fabrication method for improving alignment accuracy during semiconductor probe card bonding, characterized in that, Includes the following steps: Step 10: An upper oxide layer (21) is formed on the upper surface of the silicon substrate (1), and a lower oxide layer (22) is formed on the lower surface of the silicon substrate (1); and photoresist is applied to the upper surface of the upper oxide layer (21) to form a first photoresist layer (3). Step 20: Expose and develop M first preset positions of the first photoresist layer (3) to form M first etch positions (4); M is an integer greater than or equal to 2; Step 30: The upper oxide layer (21) and the silicon substrate (1) directly below each first etch site (4) are etched sequentially to form M tip growth sites (5); the first photoresist layer (3) is removed. Step 40: A titanium-copper alloy layer (6) is formed on the surface of the tip growth site (5) and the upper surface of the upper oxide layer (21) using a sputtering process; and photoresist is coated on the upper surface of the titanium-copper alloy layer (6) to form a second photoresist layer (11); the M second preset positions of the second photoresist layer (11) are exposed and developed to form a needle body growth site (9) above each tip growth site. Step 50: An electroplating process is used to form a first nickel-cobalt alloy layer at M tip growth sites (5) and needle body growth sites (9), and the first nickel-cobalt alloy layer is planarized to form M probes (12). Step 60: Apply photoresist to the upper surface of all probes (12) and the upper surface of the retained second photoresist layer (11) to form a third photoresist layer (15); expose and develop M third preset positions of the third photoresist layer (15) to form a first circuit pattern above each probe (12); electroplate M gold layers (16) on the M first circuit patterns. Step 70: Photoresist is applied to the upper surface of all gold layers (16) and the retained third photoresist layer (15) to form a fourth photoresist layer (17); after exposure and development of N fourth preset positions of the fourth photoresist layer (17), limit block growth sites (18) are formed next to N probes (12); N is an integer greater than or equal to 1; Step 80: At each limiting block growth site (18), a second nickel-cobalt alloy layer is formed on the titanium-copper alloy layer (6) by electroplating. The second nickel-cobalt alloy layer is planarized to form N limiting blocks (19). Step 90: Remove all photoresist layers to obtain a wafer.

2. The wafer fabrication method according to claim 1, characterized in that, Step 90, before removing all photoresist layers, also includes: Photoresist is applied to the lower surface of the lower oxide layer (22) to form a fifth photoresist layer (20); the fifth preset position of the fifth photoresist layer (20) is exposed and developed to form a second circuit pattern around the tip of each probe (12) and a third circuit pattern under each gold layer (16); the lower oxide layer (22), silicon substrate (1) and upper oxide layer (21) corresponding to each second circuit pattern are etched in sequence to form M exposure positions (13); the lower oxide layer (22), silicon substrate (1) and upper oxide layer (21) corresponding to each third circuit pattern are etched to form M detection positions (14).

3. The wafer fabrication method according to claim 1, characterized in that, The ratio of N to M is 6 to 8:

100.

4. The wafer fabrication method according to claim 1, characterized in that, The thickness of the limiting block (19) is 80-100µm.

5. The wafer fabrication method according to claim 1, characterized in that, In step 30, the first photoresist layer (3) is removed by plasma etching, and isopropanol is used to remove organic matter from the tip growth site (5) and the surface of the upper oxide layer (21).

6. The wafer fabrication method according to claim 1, characterized in that, In step 40, the thickness of the second photoresist layer (11) is 80-90µm.

7. The wafer fabrication method according to claim 1, characterized in that, In step 50, before electroplating, the surface of the needle growth site (9) is treated with plasma surface treatment method and pretreated with dilute sulfuric acid.

8. The wafer fabrication method according to claim 1, characterized in that, In step 60, the thickness of the gold layer (16) is 1 ± 0.5 µm.

9. The wafer fabrication method according to claim 1, characterized in that, In step 80, before electroplating, a plasma surface treatment method is used to treat the surface of the growth site (18) of the limiting block.

10. The wafer fabrication method according to claim 1, characterized in that, Also includes: Step 100: Based on the positioning of the limiting block (19), the gold layer (16) of the wafer is bonded to the ceramic sheet; The titanium-copper alloy layer (6) is etched to remove the silicon substrate (1) and the limiting block (19).

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