Method for testing IOB (Input / Output Block) of FPGA (Field Programmable Gate Array) chip and FPGA chip

Abstract

The embodiment of the invention provides a method for testing IOB (Input / Output Block) of an FPGA (Field Programmable Gate Array) chip and the FPGA chip. The FPGA chip comprises an excitation unit, an inspection unit and a test circuit. The method comprises the following steps: outputting an excitation signal to the test circuit by using the excitation unit; transmitting an excitation signal by using a test circuit; and the test unit is used for checking the signal output by the tail end output port of the test circuit so as to test the IOB of the FPGA chip. According to the technical scheme provided by the embodiment of the invention, the excitation signal is transmitted on the loopback included in the test circuit, the transmission process of the signal in the FPGA chip in practical application is simulated, the IOB performance of the FPGA chip can be effectively verified, the probability of occurrence of conditions such as function damage of an IOB generation circuit of the FPGA chip and integrity damage of the transmitted signal is reduced, and the reliability of the test circuit is improved. The reliability is improved.

Description

Technical Field

[0001] This application relates to the field of testing technology for Field Programmable Gate Array (FPGA) chips, and particularly to a method for testing the input output blocks (IOBs) of an FPGA chip and the FPGA chip itself. Background Technology

[0002] The quality of the IOB (Input Offset) determines the quality of a chip. Therefore, testing the IOB of an FPGA chip is a crucial step in the testing phase.

[0003] In related technologies, the specific testing process for the IOB of an FPGA chip is as follows: The ATE platform outputs an excitation signal to the input port of the FPGA chip, and then the excitation signal flows out from the output port of the FPGA chip, such as... Figure 1 As shown, during the IOB testing process of the FPGA chip, the transmission path of the excitation signal is: FPGA chip input port - FPGA chip internal logic output port - FPGA chip internal logic input port - FPGA chip output port.

[0004] In related technologies, the excitation signal in the FPGA chip is directly input and output. This testing process cannot meet the needs of actual applications, resulting in insufficient performance verification of the IOB of the FPGA chip, which in turn affects the reliability of the IOB of the FPGA chip. Summary of the Invention

[0005] This application provides a method for testing the IOB of an FPGA chip, as well as the FPGA chip itself.

[0006] In a first aspect, embodiments of this application provide a method for testing the IOBs of an FPGA chip. The FPGA chip includes an excitation unit, a verification unit, and a test circuit. The method includes: using the excitation unit to output an excitation signal to the test circuit, the test circuit including at least one loopback, the loopback including a first IOB and a second IOB, the first IOB including a first input terminal and a first output terminal, the second IOB including a second input terminal and a second output terminal, the first output terminal of the first IOB being connected to the first input terminal of the second IOB; and using the verification unit to verify the signal output from the terminal output port of the test circuit to test the IOBs of the FPGA chip.

[0007] Secondly, embodiments of this application provide an FPGA chip, which includes an excitation unit, a verification unit, and a test circuit. The excitation unit is configured to output an excitation signal to the test circuit. The test circuit is configured to transmit the excitation signal and includes at least one loopback, which includes a first IOB and a second IOB. The first IOB includes a first input terminal and a first output terminal, and the second IOB includes a second input terminal and a second output terminal. The first output terminal of the first IOB is connected to the first input terminal of the second IOB. The verification unit is configured to verify the signal output from the end output port of the test circuit to test the IOB of the FPGA chip.

[0008] Compared to related technologies, the technical solution provided in this application, when testing the IOB of an FPGA chip, outputs an excitation signal to the test circuit through an excitation unit. The test circuit includes at least one loop, and the excitation signal is transmitted on the loop included in the test circuit. This simulates the signal transmission process inside the FPGA chip in actual applications, which can effectively verify the performance of the FPGA chip's IOB, reduce the probability of the FPGA chip's IOB circuit function being damaged or the integrity of the transmitted signal being compromised, and improve reliability. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the transmission path of the excitation signal when testing the IOB of an FPGA chip, provided by relevant technologies.

[0011] Figure 2 This is a schematic diagram of an implementation environment provided in one embodiment of this application.

[0012] Figure 3 This is a flowchart of a method for testing the IOB of an FPGA chip according to an embodiment of this application.

[0013] Figure 4 This is a schematic diagram of the transmission path of the excitation signal when testing the IOB of an FPGA chip according to one embodiment of this application.

[0014] Figure 5 This is a flowchart of a method for testing the IOB of an FPGA chip according to another embodiment of this application.

[0015] Figure 6 This is a flowchart of a method for testing the IOB of an FPGA chip according to another embodiment of this application.

[0016] Figure 7 This is a structural block diagram of an FPGA chip provided in one embodiment of this application. Detailed Implementation

[0017] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0018] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] The direct-input, direct-output test schemes provided by related technologies have two main drawbacks. First, they fail to meet practical application requirements, resulting in insufficient performance verification of the IOBs of FPGA chips and consequently affecting the reliability of the FPGA chip's IOBs. Second, the excitation signals are fixed codes provided by external Automated Test Equipment (ATE) platforms, leading to high testing costs. Furthermore, modifying the excitation signals requires modifying complex excitation programs, increasing time costs.

[0020] To address the shortcomings of existing technologies, this application proposes a novel scheme for testing the IOB (Input / Output) of an FPGA chip. During IOB testing, an excitation unit outputs an excitation signal to a test circuit. This test circuit includes at least one loop, and the excitation signal is transmitted along this loop, simulating the signal transmission process within the FPGA chip in real-world applications. This effectively verifies the performance of the FPGA chip's IOB, reduces the probability of IOB circuit malfunctions and signal integrity corruption, and improves reliability. Furthermore, the excitation signal is provided by the excitation unit within the FPGA chip, eliminating the need for an external ATE (Automatic Test Equipment) platform, thus reducing testing costs. The excitation signal provided by the excitation unit can be flexibly set according to testing requirements, saving time and improving testing efficiency by eliminating the need to modify the excitation program.

[0021] The inventors' verification revealed that in related technologies, significant distortion occurs when the signal frequency is below 100MHz. However, the technical solution provided in this application can stably transmit signals above 150MHz under the single-ended input / output standard test procedure, and can stably transmit signals above 1G under the differential standard and double data rate (DDR) standard test procedures. Compared with related technologies, this is a significant improvement.

[0022] The implementation environment involved in the embodiments of this application is described below. This implementation environment includes an FPGA chip, which is a programmable logic chip capable of performing general-purpose functions. Internally, it contains a large number of programmable logic resources, programmable interconnect resources, and input / output blocks. Programmable logic units include lookup tables (LUTs), flip-flops, and other logic units used to implement combinational logic functions and sequential logic functions. Programmable interconnect resources include wiring resources used to connect various logic blocks and input / output blocks to achieve signal transmission. Input / output blocks include input buffers and output buffers used to implement signal input and output between the FPGA chip and external circuits.

[0023] In this embodiment, the FPGA chip includes an excitation unit, a verification unit, and a test circuit. The excitation unit, acting as an excitation source, provides an excitation signal and is configured using programmable logic resources within the FPGA chip. The test circuit, configured using input / output blocks within the FPGA chip, transmits the excitation signal. The verification unit compares the signal output from the final output port of the test circuit with the excitation signal to verify the IOB performance; it is also configured using programmable logic resources within the FPGA chip. In this embodiment, the test circuit includes at least one loopback. After the excitation unit outputs the excitation signal to the test circuit, the excitation signal loops through the test circuit and is finally output to the verification unit for verification. This simulates the signal transmission process within the FPGA chip in real-world applications, effectively verifying the IOB performance of the FPGA chip, reducing the probability of IOB circuit malfunction and signal integrity loss, and improving reliability.

[0024] Please refer to Figure 2 This document illustrates a flowchart of a method for testing the IOB of an FPGA chip according to an embodiment of this application. The method includes the following steps.

[0025] S201 uses the excitation unit to output an excitation signal to the test circuit.

[0026] The excitation unit is also built using the Clock Locking Manager (CLM) resources within the FPGA chip. The excitation signal it provides can be a fixed code, such as 55, AA, BB, or a random code, such as PRBS code. Whether the excitation signal is a fixed or random code depends on whether the test circuit has timing requirements or signal transmission rate requirements. Technicians can set the code pattern of the excitation signal in the relevant configuration file based on at least one of these two factors.

[0027] In this embodiment, the excitation signal is provided by the excitation unit inside the FPGA chip, without the need for an external ATE platform, reducing testing costs. Furthermore, the excitation signal provided by the excitation unit can be flexibly set according to testing requirements, thereby saving time in modifying the excitation program, saving time costs and improving testing efficiency.

[0028] In this embodiment, the test circuit includes at least one loopback, which includes a first IOB and a second IOB. The first IOB includes a first input terminal and a first output terminal, and the second IOB includes a second input terminal and a second output terminal. The first output terminal of the first IOB is connected to the first input terminal of the second IOB. The process of determining the number of loopbacks included in the test circuit will be described in the following embodiments.

[0029] The first input terminal is used to input the excitation signal.

[0030] In some embodiments, the first IOB further includes a third input terminal configured to input a control signal. The control signal enables the first IOB, and in the presence of the control signal input, the first IOB transmits an excitation signal. A first output terminal is used to output the excitation signal.

[0031] like Figure 3 The diagram illustrates a test circuit for testing the IOBs of an FPGA chip according to an embodiment of this application. The test circuit 30 includes at least two loopbacks 300, each loopback 300 including a first IOB 3100 and a second IOB 3200. The first IOB 3100 includes a first input terminal 3110, a third input terminal 3120, and a first output terminal 3130. The second IOB 3200 includes a second input terminal 3210 and a second output terminal 3220.

[0032] When the excitation signal is transmitted in the loop included in the test circuit, it simulates the signal transmission process inside the FPGA chip in actual applications. This can effectively verify the performance of the FPGA chip's IOB, reduce the probability of damage to the FPGA chip's IOB generation circuit function and the integrity of the transmitted signal, and improve reliability.

[0033] S202 uses a test circuit to transmit excitation signals.

[0034] Optionally, the test circuit is used to transmit the excitation signal, specifically implemented by controlling the excitation signal to be transmitted sequentially in multiple loops included in the test circuit; wherein, the transmission of the excitation signal in one loop includes: the output logic resource in the test circuit inputs the excitation signal into the first IOB through the first input terminal, the first IOB transmits the excitation signal to the second input terminal of the second IOB through the first output terminal, the second IOB outputs the excitation signal to the input logic resource in the test circuit through the second output terminal of the excitation signal, and the input logic resource is used to input the excitation signal into the first IOB of the next loop.

[0035] When the first IOB includes a third input terminal, the output logic resource in the test circuit needs to input the excitation signal into the first IOB through the first input terminal, and at the same time, input the control signal into the third input terminal of the first IOB.

[0036] Please refer to this again. Figure 3 The transmission path of the excitation signal in the test circuit is from the 1st loop to the nth loop, where n is the number of loops included in the test circuit. The transmission path of the excitation signal in the i-th loop is: output logic resource (Ologic) 3310 - first IOB 3100 - second IOB 3200 - input logic resource (Ilogic) 3310 - output logic resource 3320.

[0037] S203 uses a verification unit to verify the signal output from the end output port of the test circuit in order to test the IOB of the FPGA chip.

[0038] Optionally, the test unit is used to compare the signal output from the end output port of the test circuit with the expected output signal. The comparison result is used as the test result of the IOB. If the deviation between the two is less than a predetermined threshold, the IOB is determined to meet the design requirements. If the deviation between the two is greater than the predetermined threshold, the IOB is determined to not meet the design requirements, and the problem needs to be debugged and resolved.

[0039] In summary, the technical solution provided in this application, when testing the IOB of an FPGA chip, configures the programmable logic resources of the FPGA chip into a test circuit through a bitstream file. This test circuit includes at least one loop, and the excitation signal is transmitted on the loop included in the test circuit, simulating the signal transmission process inside the FPGA chip in actual applications. This can effectively verify the performance of the FPGA chip's IOB, reduce the probability of damage to the FPGA chip's IOB circuit function and the integrity of the transmitted signal, and improve reliability.

[0040] Please refer to Figure 4 The diagram illustrates a flowchart of a method for testing the IOB of an FPGA chip according to another embodiment of this application.

[0041] S401 configures the programmable logic resources based on the first stream file to obtain the excitation unit and the verification unit.

[0042] A bitstream file is a file used for programming and configuring programmable logic devices. It contains instructions and data for programming the logic device. Through a specific download cable or other mechanism, the bitstream file can be transferred to the FPGA chip to complete the program download and configuration.

[0043] After downloading the first stream file, the FPGA chip configures the programmable logic resources in the FPGA chip according to the first stream file to obtain the verification unit and the excitation unit.

[0044] S402, configure the IOB based on the second bitstream file to obtain the test circuit.

[0045] After downloading the second bitstream file, the FPGA chip configures the input and output blocks in the FPGA chip according to the second bitstream file to obtain the test circuit.

[0046] In some embodiments, S402 is replaced by S4021-S4023.

[0047] S4021, Determine the number of IOBs that need to be covered in this test process based on the second bitstream file.

[0048] In an FPGA chip, the IOB (Input / Output Block) is the interface between the FPGA and external circuits, responsible for driving and matching input and output signals under different electrical characteristics. IOBs within an FPGA chip are categorized into groups, and each group of IOBs can independently support different I / O standards.

[0049] In this embodiment, the technician can determine the number of IOBs to be covered when designing the test process, and then define it in the bit stream file. After downloading the bit stream file, the FPGA chip parses it to determine the number of IOBs to be covered in this test process, and then determines the number of IOBs to be covered in this test process as the number of loopbacks.

[0050] S4022, determine the number of loopbacks that the test circuit should include based on the number of IOBs that need to be covered in this test process.

[0051] Optionally, a group of IOBs can correspond to one or more loopbacks. That is, the number of loopbacks should be an integer multiple of the number of IOBs that need to be covered in this test.

[0052] The number of loopbacks corresponding to a group of IOBs is set according to the test requirements, such as the test time requirements and the completeness of the IOB performance test. Optionally, the shorter the test time requirement, the fewer the number of loopbacks corresponding to a group of IOBs, with a minimum of one. Optionally, the higher the requirement for the completeness of the IOB performance test, the more loopbacks corresponding to a group of IOBs.

[0053] S4023, determine the test circuit based on the number of loops that the test circuit needs to include.

[0054] The above embodiment defines a loop circuit structure. When the number of loops to be included in the test circuit is determined, the corresponding number of loops can be connected sequentially through programmable interconnect resources to obtain the test circuit.

[0055] The execution order of S401 and S402 is not limited in this application embodiment. The FPGA chip can execute S401 first and then S402; or it can execute S402 first and then S401; or it can execute S401 and S402 simultaneously.

[0056] S403 uses the excitation unit to output an excitation signal to the test circuit.

[0057] S404 uses a test circuit to transmit excitation signals.

[0058] S405 uses a verification unit to verify the signal output from the end output port of the test circuit in order to test the IOB of the FPGA chip.

[0059] In summary, the technical solution provided in this application determines the number of loopbacks based on the number of IOBs to be covered in this test process, thereby determining the test circuit. When the excitation signal is looped back and transmitted on the test circuit, it can simulate the situation when the signal is transmitted through the IOB in actual applications. This can effectively verify the performance of the FPGA chip's IOBs, reduce the probability of damage to the FPGA chip's IOB circuit function and the integrity of the transmitted signal, and improve reliability.

[0060] Reference Figure 5 This illustrates a flowchart of a method for testing the IOB of an FPGA chip according to an embodiment of this application. Based on... Figure 2 In the optional embodiments provided by the examples, S201 is replaced by S501 or S502. Based on... Figure 4 In the optional embodiments provided by the examples, S403 is replaced by S501 or S502.

[0061] S501, if there are timing requirements during signal transmission, the excitation unit outputs a random code to the test circuit as an excitation signal.

[0062] Timing requirements refer to the temporal order of a series of steps, ensuring that each step proceeds in a predetermined sequence and at the correct time to guarantee the normal operation of the system and the correct transmission of data. Since the generation process of random codes is random, using random codes can better verify timing requirements in signal transmission.

[0063] S502, if there are no timing requirements during signal transmission, the excitation unit outputs a fixed code as a random signal to the test circuit.

[0064] The generation process of fixed codes is simpler. If there are no timing requirements in signal transmission, using fixed codes can improve the generation efficiency of excitation signals, thereby improving testing efficiency.

[0065] S503 uses a test circuit to transmit excitation signals.

[0066] The S504 uses a verification unit to verify the signal output from the output port at the end of the test circuit in order to test the IOB of the FPGA chip.

[0067] In summary, the technical solution provided in this application selects either a fixed code or a random code as the excitation signal based on whether there are timing requirements during signal transmission. If there are timing requirements during signal transmission, using a random code can better verify the timing. If there are no timing requirements during signal transmission, using a fixed code can improve testing efficiency.

[0068] Reference Figure 6 This illustrates a flowchart of a method for testing the IOB of an FPGA chip according to an embodiment of this application. Based on... Figure 2 In the optional embodiments provided by the examples, S201 is replaced by S601 or S5602. Based on... Figure 4 In the optional embodiments provided by the examples, S403 is replaced by S601 or S5602.

[0069] S601, when the required signal frequency is greater than the preset frequency, uses the excitation unit to output a fixed code as an excitation signal to the test circuit.

[0070] The preset frequency can be set by technicians, for example, 300MHz. When the signal requires a higher frequency, the fixed code is simpler and can improve the reliability of transmission.

[0071] S602, when the required signal frequency is less than or equal to the preset frequency, uses the excitation unit to output a random code as an excitation signal to the test circuit.

[0072] When the required signal frequency is relatively low, a more complex random code can better verify the performance of the IOB.

[0073] S603 uses a test circuit to transmit excitation signals.

[0074] S604 uses a verification unit to verify the signal output from the output port at the end of the test circuit in order to test the IOB of the FPGA chip.

[0075] In summary, the technical solution provided in this application selects either a fixed code or a random code as the excitation signal based on the required signal frequency. When the required signal frequency is high, the fixed code is simpler and can improve transmission reliability. When the required signal frequency is low, the random code is more complex and can better verify the performance of the IOB.

[0076] In other possible implementations, the excitation unit can also determine whether the excitation signal is a fixed code or a random code by combining both timing requirements and signal frequency requirements. For example, the excitation unit scores the signal transmission process based on whether there are timing requirements to obtain a first score, scores it based on the signal transmission rate to obtain a second score, assigns weights to the first score and the second score respectively, sums them up to obtain a total score, and finally determines whether the excitation signal is a fixed code or a random code based on the total score.

[0077] Please refer to Figure 7 The diagram illustrates an embodiment of an FPGA chip 70 provided in this application. The FPGA chip 700 includes an excitation unit 720, a verification unit 730, and a test circuit 710.

[0078] Excitation unit 720 is configured to output excitation signal to test circuit 710.

[0079] The test circuit 710 is configured to transmit an excitation signal. The test circuit 710 includes at least one loopback, which includes a first IOB and a second IOB. The first IOB includes a first input and a first output, and the second IOB includes a second input and a second output. The first output of the first IOB is connected to the first input of the second IOB.

[0080] The verification unit 730 is configured to verify the signal output from the end output port of the test circuit 710 in order to test the IOB of the FPGA chip 70.

[0081] In some embodiments, the FPGA chip includes programmable logic resources and IOBs.

[0082] Programmable logic resource 710 is configured to be configured based on the first bit stream file to obtain 720 and verification unit 730.

[0083] IOB is configured to obtain test circuit 710 based on the second bitstream file.

[0084] In some embodiments, the IOB is configured to: determine the number of IOBs to be covered in this test process based on the second bitstream file; determine the number of loopbacks to be included in the test circuit based on the number of IOBs; and determine the test circuit 710 based on the number of loopbacks.

[0085] In some embodiments, the test circuit 710 is configured to control the excitation signal to be transmitted sequentially in a plurality of loops included in the test circuit 710; wherein, the transmission of the excitation signal in one loop includes: the output logic resource in the test circuit inputs the excitation signal into a first IOB through a first input terminal, the first IOB transmits the excitation signal to a second input terminal of a second IOB through a first output terminal, the second IOB outputs the excitation signal to the input logic resource in the test circuit through a second output terminal, and the input logic resource is used to input the excitation signal into the first IOB of the next loop.

[0086] In some embodiments, the excitation signal is a fixed code or a random code.

[0087] In some embodiments, the excitation unit 720 is configured to: output a random code as an excitation signal to the test circuit 710 if there are timing requirements during signal transmission; and output a fixed code as an excitation signal to the test circuit 710 if there are no timing requirements during signal transmission.

[0088] In some embodiments, the excitation unit 720 is configured to: output a fixed code as an excitation signal to the test circuit 710 when the required signal frequency is greater than a preset frequency; and output a random code as an excitation signal to the test circuit 710 when the required signal frequency is less than or equal to the preset frequency.

[0089] In some embodiments, the verification unit 730 is configured to compare the signal output from the end output port of the test circuit 710 with the desired output signal, and use the comparison result as the test result of the IOB.

[0090] In summary, the technical solution provided in this application, when testing the IOB of an FPGA chip, configures the programmable logic resources of the FPGA chip into a test circuit through a bitstream file. This test circuit includes at least one loop, and the excitation signal is transmitted on the loop included in the test circuit, simulating the signal transmission process inside the FPGA chip in actual applications. This can effectively verify the performance of the FPGA chip's IOB, reduce the probability of damage to the FPGA chip's IOB circuit function and the integrity of the transmitted signal, and improve reliability.

[0091] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0092] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip module, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a terminal, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component within the terminal (e.g., In chips, circuit modules, etc., or in different components, or at least some modules / units can be implemented by software programs that run on the processor integrated inside the terminal, while the remaining (if any) modules / units can be implemented by hardware methods such as circuits.

[0093] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for testing the IOB of an FPGA chip, characterized in that, Applied to an FPGA chip, the FPGA chip including an excitation unit, a verification unit, and a test circuit: the method includes: The excitation unit outputs an excitation signal to the test circuit. The test circuit includes at least one loopback. The loopback includes a first IOB and a second IOB. The first IOB includes a first input terminal and a first output terminal. The second IOB includes a second input terminal and a second output terminal. The first output terminal of the first IOB is connected to the first input terminal of the second IOB. The excitation signal is transmitted using the test circuit. The verification unit is used to verify the signal output from the end output port of the test circuit in order to test the IOB of the FPGA chip.

2. The method according to claim 1, characterized in that, The FPGA chip includes programmable logic resources and the IOB, and before outputting an excitation signal to the test circuit using the excitation unit, it further includes: The programmable logic resources are configured based on the first stream file to obtain the activation unit and the verification unit; and, The test circuit is obtained by configuring the IOB based on the second bitstream file.

3. The method according to claim 2, characterized in that, The base is configured with the IOB based on the second bitstream file to obtain the test circuit, including: The number of IOBs that need to be covered in this test process is determined based on the second bitstream file; The number of loopbacks that the test circuit needs to include is determined based on the number of IOBs; The test circuit is determined based on the number of loopbacks.

4. The method according to claim 3, characterized in that, The transmission of the excitation signal using the test circuit includes: The excitation signal is controlled to be transmitted sequentially in multiple loops included in the test circuit; wherein, the transmission of the excitation signal in one loop includes: the output logic resource in the test circuit inputs the excitation signal into the first IOB through the first input terminal; the first IOB transmits the excitation signal to the second input terminal of the second IOB through the first output terminal; the second IOB outputs the excitation signal to the input logic resource in the test circuit through the second output terminal; and the input logic resource is used to input the excitation signal into the first IOB of the next loop.

5. The method according to claim 1, characterized in that, The excitation signal is a fixed code or a random code.

6. The method according to claim 5, characterized in that, The step of outputting an excitation signal to the test circuit using the excitation unit includes: If there are timing requirements during signal transmission, the excitation unit outputs the random code to the test circuit as the excitation signal. If the timing requirement does not exist during signal transmission, the excitation unit outputs the fixed code to the test circuit as the excitation signal.

7. The method according to claim 5, characterized in that, The step of outputting an excitation signal to the test circuit using the excitation unit includes: When the required signal frequency is greater than the preset frequency, the excitation unit outputs the fixed code to the test circuit as the excitation signal. When the required signal frequency is less than or equal to a preset frequency, the excitation unit outputs the random code to the test circuit as the excitation signal.

8. The method according to any one of claims 1 to 7, characterized in that, The step of verifying the signal output from the terminal output port of the test circuit using the verification unit to test the IOB of the FPGA chip includes: The test unit compares the signal output from the end output port of the test circuit with the expected output signal, and the comparison result is used as the test result of the IOB.

9. The method according to any one of claims 1 to 7, characterized in that, The first IOB also includes a third input terminal, which is configured to input a control signal.

10. An FPGA chip, characterized in that, The FPGA chip includes an excitation unit, a verification unit, and a test circuit. The excitation unit is configured to output an excitation signal to the test circuit; The test circuit is configured to transmit the excitation signal. The test circuit includes at least one loopback, the loopback including a first IOB and a second IOB. The first IOB includes a first input terminal and a first output terminal. The second IOB includes a second input terminal and a second output terminal. The first output terminal of the first IOB is connected to the first input terminal of the second IOB. The verification unit is configured to verify the signal output from the end output port of the test circuit in order to test the IOB of the FPGA chip.

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