Electric vehicle power electronic system efficiency improving method based on silicon substrate GaN HEMT

Abstract

The invention discloses a method for improving the efficiency of an electric vehicle power electronic system based on a silicon substrate GaN HEMT (High Electron Mobility Transistor). According to the invention, through multi-dimensional collaborative optimization, the energy conversion efficiency and reliability of the gallium nitride device under the complex working condition of the electric vehicle are significantly improved. A dynamic grid voltage compensation mechanism is taken as a core, and temperature gradient real-time monitoring and local voltage regulation are combined, so that the problems of switching loss and conduction performance degradation caused by non-uniform heat distribution in a traditional scheme are effectively solved. The dynamic enhancement of the driving voltage in the high-temperature region can accelerate carrier migration and reduce Joule loss caused by on-resistance; and voltage stress and electromagnetic interference caused by switch overshoot are avoided by moderately suppressing the voltage in the low-temperature region. The self-adaptive thermal-electric coupling control enables the device to maintain stable switching characteristics in a wide temperature range, and forms a synergistic effect with three-dimensional micro-channel heat dissipation and a multi-phase topological architecture, so that the overall temperature rise and parasitic parameter influence of the system is further reduced, and the energy loss is controlled at an extremely low level.

Description

Technical Field

[0001] This invention belongs to the field of electric vehicle circuit technology, specifically a method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs), as core devices of third-generation semiconductors, have become an ideal choice for power electronic systems such as electric vehicle on-board chargers, motor drives, and DC / DC converters due to their advantages such as high electron mobility, wide bandgap, and high breakdown field strength. Traditional silicon-based devices are limited by material properties, resulting in a significant decrease in efficiency under high temperature and high frequency conditions. In contrast, GaN HEMTs can achieve switching frequencies in the megahertz range, increasing power density several times over, and theoretically, can significantly reduce system size and energy consumption.

[0003] However, traditional drive circuits use fixed gate voltages, which cannot offset the switching characteristic drift caused by temperature gradients in real time. This leads to a surge in conduction losses in local overheated areas, while additional electromagnetic noise is generated in low-temperature areas due to switching oscillations. The heat dissipation solution relies on passive conduction or homogeneous cooling, which is difficult to accurately match the thermal coupling requirements of high power density chips, thus limiting the power density and reliability limits of electric vehicle power electronic systems. Summary of the Invention

[0004] The purpose of this invention is to provide a method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT in order to solve the problems mentioned above.

[0005] The technical solution adopted in this invention is as follows: A method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT, the method comprising the following steps: S1: Optimize the epitaxial layer structure of gallium nitride high electron mobility transistors by adjusting the aluminum composition gradient and barrier layer thickness to improve the two-dimensional electron gas concentration and electron mobility, thereby reducing the on-resistance; S2: Design a gate drive circuit with adaptive multi-level output, which uses a closed-loop feedback mechanism to dynamically match the transient requirements of switching and reduce switching losses caused by Miller capacitance effect; S3: Introduces a dynamic gate voltage compensation mechanism based on temperature gradient, which monitors the chip's heat distribution in real time through distributed thermoelectric sensors and automatically adjusts the local drive voltage to balance switching speed and conduction loss. S4: It adopts a three-dimensional embedded microchannel heat dissipation structure, integrating micron-level cooling channels on the back of the silicon substrate to achieve direct thermal coupling between the active area of ​​the device and the heat dissipation system. S5: It adopts a multi-phase interleaved parallel topology architecture and combines zero-voltage switching technology to reduce current ripple and core loss under high-frequency operation. S6: Develop a dynamic dead-time adjustment algorithm based on model predictive control to optimize the timing of the commutation process by monitoring load current changes in real time; S7: Integrates high-frequency magnetic components and power devices to form a three-dimensional package module, and uses electromagnetic field co-design to shorten the parasitic parameters of the energy transmission path; S8: Establish an online aging monitoring system to predict device degradation trends through gate charge characteristic analysis and dynamically compensate for efficiency losses caused by threshold voltage drift. S9: Implement a multi-condition joint simulation and experimental verification platform, and optimize the global efficiency curve of the power electronic system by combining the road load spectrum and battery charging and discharging characteristics.

[0006] In a preferred embodiment, in step S1, when optimizing the epitaxial layer structure of the gallium nitride high electron mobility transistor, it is necessary to precisely control the aluminum composition gradient and the barrier layer thickness; the aluminum composition gradient gradually changes from 30% to 15% along the growth direction to form a gradient AlGaN layer, with the thickness controlled between 20 nm and 30 nm to induce a high concentration of two-dimensional electron gas; the barrier layer is selected as an AlN insertion layer with a thickness of 3 nm to 5 nm to enhance the polarization effect, and the two-dimensional electron gas concentration needs to reach 1.2 × 10^13 cm⁻ 2 Above all, the electron mobility needs to exceed 2000 cm⁻¹. 2 / V·s; Epitaxial growth was performed using metal-organic chemical vapor deposition (MOCVD) technology, with the growth temperature set at 1050°C and the reaction chamber pressure maintained at 200 mbar to ensure that the crystal defect density was below 1×10^9 cm⁻. 2 .

[0007] In a preferred embodiment, in step S2, when designing the adaptive multilevel output gate drive circuit, a closed-loop feedback and multilevel modulation module need to be integrated; the drive voltage supports four adjustable output levels, namely -3 V, 0 V, +5 V and +7 V, and the switching frequency covers the range of 100 kHz to 2 MHz; the closed-loop feedback dynamically adjusts the drive voltage amplitude and rise time by detecting the drain-source voltage slope and Miller plateau time, and the voltage regulation accuracy needs to reach ±50 mV, with a response time of less than 50 ns; the Miller capacitance effect is suppressed by using an active Miller clamp circuit, with the clamp current set to 2 A and the reverse recovery charge limited to within 10 nC; this design can reduce switching losses by 35% and reduce voltage overshoot to within 10% of the rated value.

[0008] In a preferred embodiment, in step S3, the thermocouple material is selected as Pt1000 thin film, the thermal response time must be less than or equal to 100 microseconds, and the annual temperature drift error must be less than ±0.5 degrees Celsius. Voltage adjustment range: The gate drive voltage dynamic compensation range is -1.5 volts to +2.0 volts, and the reference drive voltage is set to +6 volts; Thermal balance threshold: When the temperature difference between adjacent sensors is greater than 15 degrees Celsius, regional compensation is triggered; when the global temperature difference is greater than 30 degrees Celsius, a system-level thermal balance strategy is triggered. The specific operating steps include: S3-1. Deployment of Distributed Thermoelectric Sensors: S3-1A. Embed a micro thermocouple array in a key area on the chip surface, prioritizing coverage of high heat-sensitive areas such as the drain edge, gate contact point, and center of the active region. The sensor density should be no less than 5 per square millimeter, the temperature detection resolution should reach 0.1 degrees Celsius, and the sampling frequency should be greater than or equal to 1000 Hz. S3-1B. The sensor layout should focus on covering high power density areas and weak points in heat dissipation to ensure comprehensive thermal distribution monitoring; S3-2. Thermal Field Modeling and Calibration: S3-2A. Establish a three-dimensional thermal conduction model of the chip and calibrate the nonlinear relationship between temperature gradient and gate voltage through experiments. Under typical conditions, the driving voltage needs to be dynamically compensated by 0.3 to 0.5 volts for every 10 degrees Celsius increase in temperature to maintain switching speed stability. S3-2B. The reference temperature range is set to 25 degrees Celsius to 150 degrees Celsius. If the temperature exceeds this range, the over-temperature protection mechanism will be triggered immediately. S3-3. Execution of dynamic voltage compensation algorithm: S3-3A. After the sensor collects temperature data in real time, it inputs the data into the embedded processing unit for heat distribution interpolation calculation. The processing unit can be a high-response device such as FPGA, and finally generates a local temperature rise thermal map. S3-3B. Based on the preset temperature-voltage compensation curve, apply a positive voltage offset to areas with temperatures above 80 degrees Celsius, with a typical compensation value of +0.2 volts to +1.0 volts, to improve switching speed; apply a negative voltage offset to areas with temperatures below 50 degrees Celsius, with a typical compensation value of -0.1 volts to -0.3 volts, to suppress switching oscillations; the voltage regulation step size accuracy must be controlled within ±10 millivolts, and the response delay must be less than or equal to 10 microseconds; S3-4. Closed-loop feedback and adaptive optimization: S3-4A. Monitors the transient characteristics of the switch by the drain current waveform. If an overshoot voltage exceeding 20% ​​of the rated voltage is detected, the drive voltage compensation amount is automatically adjusted back. S3-4B. Iteratively update compensation parameters by combining historical operating data, such as the changing trends of load current and switching frequency, thereby improving system robustness.

[0009] In a preferred embodiment, in step S4, the three-dimensional embedded microchannel heat dissipation structure needs to be fabricated on the back side of the silicon substrate with a depth of 200 micrometers and a width of 100 micrometers, and the channel spacing is 150 micrometers. The vertical sidewall roughness is less than 1 micrometer using deep reactive ion etching process. The cooling medium is a 50% ethylene glycol aqueous solution, the flow rate is controlled at 0.5 L / min to 2 L / min, and the inlet temperature is maintained at 25 degrees Celsius.

[0010] In a preferred embodiment, in step S5, the multiphase interleaved parallel topology adopts a four-phase parallel design, with each phase switching frequency of 250 kHz and a phase difference of 90 degrees. After interleaving, the equivalent frequency is increased to 1 MHz. Zero-voltage switching technology requires a resonant capacitor connected in parallel with the switching transistor, with a capacitance value of 2.2 nF to 4.7 nF. The resonant inductance is 50 nH, and the dead time is compressed to within 20 ns. The peak-to-peak value of the current ripple needs to be controlled below 10% of the full-load current, and the core loss is limited to 300 kW / m² using nanocrystalline materials. 3 This architecture can reduce total harmonic distortion to below 3% and increase efficiency to 98.5% at full load.

[0011] In a preferred embodiment, in step S6, the dynamic dead-time adjustment algorithm is based on model predictive control, with a sampling period of 1 microsecond and a prediction time domain set to 5 switching cycles; the load current change rate is monitored in real time, the current sampling accuracy needs to reach ±1%, the dead-time adjustment range is 15 ns to 100 ns, and the adjustment step size is 1 ns; the timing optimization of the commutation process needs to match the ±5 ns window of the current zero crossing point, and the voltage spike is suppressed to within 15% of the rated value; the algorithm is deployed on a digital signal processor, with an instruction cycle of less than 10 ns, which can reduce commutation loss by 25% and improve overall efficiency by 1.2 percentage points.

[0012] In a preferred embodiment, in step S7, the three-dimensional packaging module of the high-frequency magnetic component and the power device adopts a three-dimensional stacked structure. The magnetic component is made of alternating layers of ferrite and copper foil with a layer thickness of 100 micrometers and a core loss density of less than 200 mW / cm². 3 The parasitic inductance of the power circuit needs to be reduced to below 5 nH, and the parasitic capacitance to less than 10 pF; the module size should be controlled within 20 mm × 20 mm × 5 mm, and the power density should reach 50 W / cm². 3 .

[0013] In a preferred embodiment, in step S8, the online aging monitoring system acquires the gate charge waveform in real time at a sampling frequency of 10 MHz. The characteristic parameters include threshold voltage, transconductance, and gate resistance. The aging model is based on a particle filter algorithm, and the device lifetime prediction error is less than 10%. The threshold voltage drift compensation range is -0.5 V to +0.8 V, the compensation step size is 50 mV, and the dynamic adjustment period is 1 minute.

[0014] In a preferred embodiment, in step S9, the multi-condition joint simulation and experimental verification platform needs to integrate six typical load spectra, such as urban roads, high-speed cruising, and rapid acceleration, and the battery charging and discharging simulation accuracy reaches ±0.5%; the simulation model includes electrothermal and mechanical multi-physics coupling, the mesh generation accuracy is 0.1 mm, and the calculation convergence time is less than 1 hour.

[0015] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention significantly improves the energy conversion efficiency and reliability of gallium nitride (GaN) devices under complex operating conditions in electric vehicles through multi-dimensional collaborative optimization. Based on a dynamic gate voltage compensation mechanism, combined with real-time temperature gradient monitoring and local voltage regulation, it effectively solves the switching losses and conduction performance degradation problems caused by uneven heat distribution in traditional solutions. Dynamically enhanced driving voltage in high-temperature regions accelerates carrier migration and reduces Joule losses caused by on-resistance; moderate voltage suppression in low-temperature regions avoids voltage stress and electromagnetic interference caused by switching overshoot. This adaptive thermo-electric coupling control enables the device to maintain stable switching characteristics over a wide temperature range, while simultaneously forming a synergistic effect with three-dimensional microfluidic heat dissipation and multiphase topology architecture, further reducing the overall system temperature rise and the impact of parasitic parameters, thereby controlling energy loss to an extremely low level.

[0016] 2. This invention achieves high-efficiency, high-power-density operation of power electronic devices through global innovation in materials, structure, algorithms, and packaging. Dynamic dead-time adjustment and high-frequency magnetic integration design shorten the energy transmission path and reduce energy waste during commutation; aging monitoring and multi-condition simulation platforms ensure consistent system efficiency throughout its entire lifecycle. Especially in scenarios involving frequent start-stop cycles and high-current transients in electric vehicles, this solution can significantly improve the response speed and energy efficiency ratio of the motor drive and battery management system, extend driving range, and reduce the risk of thermal runaway. Attached Figure Description

[0017] Figure 1 This is a schematic diagram illustrating the process principle of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Example: Reference Figure 1 A method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT, the method comprising the following steps: S1: Optimize the epitaxial layer structure of gallium nitride high electron mobility transistors by adjusting the aluminum composition gradient and barrier layer thickness to improve the two-dimensional electron gas concentration and electron mobility, thereby reducing the on-resistance.

[0020] S2: Design a gate drive circuit with adaptive multi-level output, which uses a closed-loop feedback mechanism to dynamically match the transient requirements of switching and reduce switching losses caused by Miller capacitance effect.

[0021] S3: Introduces a dynamic gate voltage compensation mechanism based on temperature gradient. It monitors the chip's heat distribution in real time through distributed thermoelectric sensors and automatically adjusts the local drive voltage to balance switching speed and conduction loss.

[0022] S4: It adopts a three-dimensional embedded microfluidic heat dissipation structure, integrating micron-level cooling channels on the back of the silicon substrate to achieve direct thermal coupling between the active area of ​​the device and the heat dissipation system.

[0023] S5: It adopts a multi-phase interleaved parallel topology architecture and combines zero-voltage switching technology to reduce current ripple and core loss under high-frequency operation.

[0024] S6: Develop a dynamic dead-time adjustment algorithm based on model predictive control to optimize the timing of the commutation process by monitoring load current changes in real time.

[0025] S7: Integrates high-frequency magnetic components and power devices to form a three-dimensional package module, and uses electromagnetic field co-design to shorten the parasitic parameters of the energy transmission path.

[0026] S8: Establish an online aging monitoring system to predict device degradation trends through gate charge characteristic analysis and dynamically compensate for efficiency losses caused by threshold voltage drift.

[0027] S9: Implement a multi-condition joint simulation and experimental verification platform, and optimize the global efficiency curve of the power electronic system by combining the road load spectrum and battery charging and discharging characteristics.

[0028] In step S1, optimizing the epitaxial layer structure of gallium nitride high electron mobility transistors requires precise control of the aluminum composition gradient and the barrier layer thickness. The aluminum composition gradient gradually decreases from 30% to 15% along the growth direction, forming a gradient AlGaN layer with a thickness controlled between 20 and 30 nanometers to induce a high concentration of two-dimensional electron gas. The barrier layer is an AlN insertion layer with a thickness of 3 to 5 nanometers to enhance the polarization effect, and the two-dimensional electron gas concentration needs to reach 1.2 × 10^13 cm⁻. 2 Above all, the electron mobility needs to exceed 2000 cm⁻¹. 2 / V·s. Epitaxial growth was performed using metal-organic chemical vapor deposition (MOCVD) technology, with the growth temperature set at 1050°C and the reaction chamber pressure maintained at 200 mbar to ensure that the crystal defect density was below 1×10^9 cm⁻. 2 Through this optimization, the on-resistance can be reduced to 0.2 mΩ·cm. 2 The following is a 40% reduction compared to the traditional structure.

[0029] In step S2, when designing the adaptive multi-level output gate drive circuit, a closed-loop feedback and multi-level modulation module must be integrated. The drive voltage supports four adjustable output levels: -3 V, 0 V, +5 V, and +7 V, with a switching frequency covering the range of 100 kHz to 2 MHz. The closed-loop feedback dynamically adjusts the drive voltage amplitude and rise time by detecting the drain-source voltage slope and Miller plateau time, with a voltage regulation accuracy of ±50 mV and a response time of less than 50 ns. Miller capacitance effect suppression employs an active Miller clamp circuit, with a clamp current set to 2 A and reverse recovery charge limited to within 10 nC. This design can reduce switching losses by 35% and reduce voltage overshoot to within 10% of the rated value.

[0030] In step S3, the thermocouple material is selected as Pt1000 thin film, the thermal response time must be less than or equal to 100 microseconds, and the annual temperature drift error must be less than ±0.5 degrees Celsius.

[0031] Voltage adjustment range: The gate drive voltage dynamic compensation range is -1.5 volts to +2.0 volts, and the reference drive voltage is set to +6 volts.

[0032] Thermal balance threshold: Regional compensation is triggered when the temperature difference between adjacent sensors is greater than 15 degrees Celsius, and a system-level thermal balance strategy is triggered when the global temperature difference is greater than 30 degrees Celsius.

[0033] The specific operating steps include: S3-1. Deployment of Distributed Thermoelectric Sensors: S3-1A. Embed a micro thermocouple array in a key area on the chip surface, prioritizing coverage of high heat-sensitive areas such as the drain edge, gate contact point, and center of the active region. The sensor density should be no less than 5 per square millimeter, the temperature detection resolution should reach 0.1 degrees Celsius, and the sampling frequency should be greater than or equal to 1000 Hz.

[0034] S3-1B. The sensor layout should focus on covering high power density areas and weak points in heat dissipation to ensure comprehensive heat distribution monitoring.

[0035] S3-2. Thermal Field Modeling and Calibration: S3-2A. Establish a three-dimensional thermal conduction model of the chip and calibrate the nonlinear relationship between temperature gradient and gate voltage through experiments. Under typical conditions, the drive voltage needs to be dynamically compensated by 0.3 to 0.5 volts for every 10 degrees Celsius increase in temperature to maintain switching speed stability.

[0036] S3-2B. The reference temperature range is set to 25 degrees Celsius to 150 degrees Celsius. If the temperature exceeds this range, the over-temperature protection mechanism will be triggered immediately.

[0037] S3-3. Execution of dynamic voltage compensation algorithm: After the S3-3A sensor collects temperature data in real time, it inputs the data into the embedded processing unit for heat distribution interpolation calculation. The processing unit can use high-response devices such as FPGAs to generate a local temperature rise thermal map.

[0038] S3-3B. Based on the preset temperature-voltage compensation curve, a positive voltage offset is applied to areas with temperatures above 80 degrees Celsius, with a typical compensation value of +0.2 volts to +1.0 volts, to improve switching speed; a negative voltage offset is applied to areas with temperatures below 50 degrees Celsius, with a typical compensation value of -0.1 volts to -0.3 volts, to suppress switching oscillations. The voltage regulation step size accuracy must be controlled within ±10 millivolts, and the response delay must be less than or equal to 10 microseconds.

[0039] S3-4. Closed-loop feedback and adaptive optimization: S3-4A. Monitors the transient characteristics of the switch by the drain current waveform. If an overshoot voltage exceeding 20% ​​of the rated voltage is detected, the drive voltage compensation amount is automatically adjusted back.

[0040] S3-4B. Iteratively update compensation parameters by combining historical operating data, such as the changing trends of load current and switching frequency, thereby improving system robustness.

[0041] In step S4, the three-dimensional embedded microchannel heat dissipation structure requires the fabrication of serpentine microchannels with a depth of 200 micrometers and a width of 100 micrometers on the back side of a silicon substrate, with a channel spacing of 150 micrometers. Deep reactive ion etching (DRIE) is used to achieve a vertical sidewall roughness of less than 1 micrometer. A 50% ethylene glycol aqueous solution is used as the cooling medium, with a flow rate controlled between 0.5 L / min and 2 L / min, and the inlet temperature maintained at 25 degrees Celsius. The microchannels and the gallium nitride active region are directly thermally coupled via copper pillars, and the thermal interface material must have a thermal conductivity greater than 5 W / m·K. This structure can reduce the junction temperature by 40 degrees Celsius, decrease the thermal resistance from 1.2 K / W to 0.3 K / W, and increase the heat dissipation capacity to 500 W / cm². 2 .

[0042] In step S5, the multiphase interleaved parallel topology adopts a four-phase parallel design, with each phase switching at a frequency of 250kHz and a phase difference of 90 degrees. After interleaving, the equivalent frequency is increased to 1MHz. Zero-voltage switching technology requires a resonant capacitor connected in parallel with the switching transistor, with a capacitance value of 2.2 nF to 4.7 nF. The resonant inductor is 50 nH, and the dead time is compressed to within 20 ns. The peak-to-peak current ripple needs to be controlled below 10% of the full-load current, and the core loss is limited to 300kW / m² using nanocrystalline materials. 3 This architecture can reduce total harmonic distortion to below 3% and increase efficiency to 98.5% at full load.

[0043] In step S6, the dynamic dead-time adjustment algorithm is based on model predictive control, with a sampling period of 1 microsecond and a prediction time domain set to 5 switching cycles. The load current change rate is monitored in real time, with a current sampling accuracy of ±1%. The dead-time adjustment range is 15 ns to 100 ns, with an adjustment step size of 1 ns. The timing optimization during the commutation process needs to match a ±5 ns window for the current zero-crossing point, and voltage spikes are suppressed to within 15% of the rated value. The algorithm is deployed on a digital signal processor with an instruction cycle of less than 10 ns, achieving a 25% reduction in commutation losses and a 1.2 percentage point improvement in overall efficiency.

[0044] In step S7, the three-dimensional packaging module for the high-frequency magnetic components and power devices adopts a three-dimensional stacked structure. The magnetic components are made of alternating layers of ferrite and copper foil, with a layer thickness of 100 micrometers and a core loss density of less than 200 mW / cm². 3 The parasitic inductance of the power circuit needs to be reduced to below 5 nH, and the parasitic capacitance to less than 10 pF. The module size should be controlled within 20 mm × 20 mm × 5 mm, achieving a power density of 50 W / cm². 3 Electromagnetic field co-design optimizes winding layout through finite element simulation, reducing leakage inductance to below 0.5% and extending efficiency bandwidth to 10 MHz.

[0045] In step S8, the online aging monitoring system acquires the gate charge waveform in real time at a sampling frequency of 10MHz. Characteristic parameters include threshold voltage, transconductance, and gate resistance. The aging model is based on a particle filter algorithm, predicting device lifetime with an error of less than 10%. The threshold voltage drift compensation range is -0.5 V to +0.8 V, with a compensation step size of 50 mV and a dynamic adjustment period of 1 minute. The system must operate continuously for 1000 hours within a temperature range of -40°C to 150°C, with a threshold voltage stability deviation of less than 3%, conforming to the AEC-Q101 Grade 1 standard.

[0046] In step S9, the multi-condition joint simulation and experimental verification platform needs to integrate six typical load spectra, including urban roads, high-speed cruising, and rapid acceleration, with a battery charge-discharge simulation accuracy of ±0.5%. The simulation model includes electrothermal-mechanical multi-physics coupling, with a mesh generation accuracy of 0.1 mm and a computational convergence time of less than 1 hour. The error between measured data and simulation needs to be controlled within 5%. After global efficiency curve optimization, the system efficiency fluctuation within the 20% to 100% load range should be less than 1.5%, and the overall energy efficiency should be improved to over 94%.

[0047] From the above, we can conclude that: This invention significantly improves the energy conversion efficiency and reliability of gallium nitride (GaN) devices under complex operating conditions in electric vehicles through multi-dimensional collaborative optimization. Based on a dynamic gate voltage compensation mechanism, combined with real-time temperature gradient monitoring and local voltage regulation, it effectively solves the switching losses and conduction performance degradation problems caused by uneven heat distribution in traditional solutions. Dynamically enhanced driving voltage in high-temperature regions accelerates carrier migration and reduces Joule losses caused by on-resistance; moderate voltage suppression in low-temperature regions avoids voltage stress and electromagnetic interference caused by switching overshoot. This adaptive thermo-electric coupling control enables the device to maintain stable switching characteristics over a wide temperature range, while simultaneously forming a synergistic effect with three-dimensional microfluidic heat dissipation and multiphase topology architecture, further reducing the overall system temperature rise and the impact of parasitic parameters, thereby controlling energy loss to an extremely low level.

[0048] This invention achieves high-efficiency, high-power-density operation of power electronic devices through global innovation in materials, structure, algorithms, and packaging. Dynamic dead-time adjustment and high-frequency magnetic integration design shorten the energy transmission path and reduce energy waste during commutation; aging monitoring and multi-condition simulation platforms ensure consistent system efficiency throughout its entire lifecycle. Especially in scenarios involving frequent start-stop cycles and high-current transients in electric vehicles, this solution can significantly improve the response speed and energy efficiency ratio of the motor drive and battery management system, extend driving range, and reduce the risk of thermal runaway.

[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0050] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT, characterized in that: The method includes the following steps: S1: Optimize the epitaxial layer structure of gallium nitride high electron mobility transistors by adjusting the aluminum composition gradient and barrier layer thickness to improve the two-dimensional electron gas concentration and electron mobility, thereby reducing the on-resistance; S2: Design a gate drive circuit with adaptive multi-level output, which uses a closed-loop feedback mechanism to dynamically match the transient requirements of switching and reduce switching losses caused by Miller capacitance effect; S3: Introduces a dynamic gate voltage compensation mechanism based on temperature gradient, which monitors the chip's heat distribution in real time through distributed thermoelectric sensors and automatically adjusts the local drive voltage to balance switching speed and conduction loss. S4: It adopts a three-dimensional embedded microchannel heat dissipation structure, integrating micron-level cooling channels on the back of the silicon substrate to achieve direct thermal coupling between the active area of ​​the device and the heat dissipation system. S5: It adopts a multi-phase interleaved parallel topology architecture and combines zero-voltage switching technology to reduce current ripple and core loss under high-frequency operation. S6: Develop a dynamic dead-time adjustment algorithm based on model predictive control to optimize the timing of the commutation process by monitoring load current changes in real time; S7: Integrates high-frequency magnetic components and power devices to form a three-dimensional package module, and uses electromagnetic field co-design to shorten the parasitic parameters of the energy transmission path; S8: Establish an online aging monitoring system to predict device degradation trends through gate charge characteristic analysis and dynamically compensate for efficiency losses caused by threshold voltage drift. S9: Implement a multi-condition joint simulation and experimental verification platform, and optimize the global efficiency curve of the power electronic system by combining the road load spectrum and battery charging and discharging characteristics.

2. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S1, when optimizing the epitaxial layer structure of gallium nitride high electron mobility transistors, it is necessary to precisely control the aluminum composition gradient and the barrier layer thickness. The aluminum composition gradient gradually changes from 30% to 15% along the growth direction to form a gradient AlGaN layer, with the thickness controlled between 20 nm and 30 nm to induce a high concentration of two-dimensional electron gas. The barrier layer is selected as an AlN insertion layer with a thickness of 3 nm to 5 nm to enhance the polarization effect, and the two-dimensional electron gas concentration needs to reach 1.2 × 10^13 cm⁻. 2 Above all, the electron mobility needs to exceed 2000 cm⁻¹. 2 / V·s; Epitaxial growth was performed using metal-organic chemical vapor deposition (MOCVD) at a growth temperature of 1050°C and a reaction chamber pressure maintained at 200 mbar to ensure a crystal defect density of less than 1×10^9 cm⁻. 2 .

3. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S2, when designing the adaptive multi-level output gate drive circuit, a closed-loop feedback and multi-level modulation module needs to be integrated; the drive voltage supports four adjustable output levels, namely -3 V, 0 V, +5 V and +7 V, and the switching frequency covers the range of 100 kHz to 2 MHz; the closed-loop feedback dynamically adjusts the drive voltage amplitude and rise time by detecting the drain-source voltage slope and Miller plateau time, and the voltage regulation accuracy needs to reach ±50 mV, with a response time of less than 50 ns; the Miller capacitance effect is suppressed by using an active Miller clamp circuit, with the clamp current set to 2 A and the reverse recovery charge limited to within 10 nC; this design can reduce switching losses by 35% and reduce voltage overshoot to within 10% of the rated value.

4. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S3, the thermocouple material is selected as Pt1000 thin film, the thermal response time must be less than or equal to 100 microseconds, and the annual temperature drift error must be less than ±0.5 degrees Celsius. Voltage adjustment range: The gate drive voltage dynamic compensation range is -1.5 volts to +2.0 volts, and the reference drive voltage is set to +6 volts; Thermal balance threshold: When the temperature difference between adjacent sensors is greater than 15 degrees Celsius, regional compensation is triggered; when the global temperature difference is greater than 30 degrees Celsius, a system-level thermal balance strategy is triggered. The specific operating steps include: S3-1. Deployment of Distributed Thermoelectric Sensors: S3-1A. Embed a micro thermocouple array in a key area on the chip surface, prioritizing coverage of high heat-sensitive areas such as the drain edge, gate contact point, and center of the active region. The sensor density should be no less than 5 per square millimeter, the temperature detection resolution should reach 0.1 degrees Celsius, and the sampling frequency should be greater than or equal to 1000 Hz. S3-1B. The sensor layout should focus on covering high power density areas and weak points in heat dissipation to ensure comprehensive thermal distribution monitoring; S3-2. Thermal Field Modeling and Calibration: S3-2A. Establish a three-dimensional thermal conduction model of the chip and calibrate the nonlinear relationship between temperature gradient and gate voltage through experiments. Under typical conditions, the driving voltage needs to be dynamically compensated by 0.3 to 0.5 volts for every 10 degrees Celsius increase in temperature to maintain switching speed stability. S3-2B. The reference temperature range is set to 25 degrees Celsius to 150 degrees Celsius. If the temperature exceeds this range, the over-temperature protection mechanism will be triggered immediately. S3-3. Execution of dynamic voltage compensation algorithm: S3-3A. After the sensor collects temperature data in real time, it inputs the data into the embedded processing unit for heat distribution interpolation calculation. The processing unit can be a high-response device such as FPGA, and finally generates a local temperature rise thermal map. S3-3B. Based on the preset temperature-voltage compensation curve, apply a positive voltage offset to areas with temperatures above 80 degrees Celsius, with a typical compensation value of +0.2 volts to +1.0 volts, to improve switching speed; apply a negative voltage offset to areas with temperatures below 50 degrees Celsius, with a typical compensation value of -0.1 volts to -0.3 volts, to suppress switching oscillations; the voltage regulation step size accuracy must be controlled within ±10 millivolts, and the response delay must be less than or equal to 10 microseconds; S3-4. Closed-loop feedback and adaptive optimization: S3-4A. Monitors the transient characteristics of the switch by the drain current waveform. If an overshoot voltage exceeding 20% ​​of the rated voltage is detected, the drive voltage compensation amount is automatically adjusted back. S3-4B. Iteratively update compensation parameters by combining historical operating data, such as the changing trends of load current and switching frequency, thereby improving system robustness.

5. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S4, the three-dimensional embedded microchannel heat dissipation structure needs to be fabricated on the back of the silicon substrate with a depth of 200 micrometers and a width of 100 micrometers, and the channel spacing is 150 micrometers. The vertical sidewall roughness is less than 1 micrometer using deep reactive ion etching process. The cooling medium is a 50% ethylene glycol aqueous solution, the flow rate is controlled at 0.5 L / min to 2 L / min, and the inlet temperature is maintained at 25 degrees Celsius.

6. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S5, the multiphase interleaved parallel topology adopts a four-phase parallel design, with each phase switching at a frequency of 250 kHz and a phase difference of 90 degrees. After interleaving, the equivalent frequency is increased to 1 MHz. Zero-voltage switching technology requires a resonant capacitor connected in parallel with the switching transistor, with a capacitance value of 2.2 nF to 4.7 nF. The resonant inductance is 50 nH, and the dead time is compressed to within 20 ns. The peak-to-peak value of the current ripple needs to be controlled below 10% of the full-load current, and the core loss is limited to 300 kW / m² using nanocrystalline materials. 3 This architecture can reduce total harmonic distortion to below 3% and increase efficiency to 98.5% at full load.

7. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S6, the dynamic dead time adjustment algorithm is based on model predictive control, with a sampling period of 1 microsecond and a prediction time domain set to 5 switching cycles; the load current change rate is monitored in real time, the current sampling accuracy needs to reach ±1%, the dead time is adjusted from 15 ns to 100 ns, and the adjustment step size is 1 ns; the timing optimization of the commutation process needs to match the ±5 ns window of the current zero crossing point, and the voltage spike is suppressed to within 15% of the rated value.

8. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S7, the three-dimensional packaging module for the high-frequency magnetic components and power devices adopts a three-dimensional stacked structure. The magnetic components are made of alternating layers of ferrite and copper foil, with a layer thickness of 100 micrometers and a core loss density of less than 200 mW / cm². 3 The parasitic inductance of the power circuit needs to be reduced to below 5 nH, and the parasitic capacitance to less than 10 pF; the module size should be controlled within 20 mm × 20 mm × 5 mm, and the power density should reach 50 W / cm². 3 .

9. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S8, the online aging monitoring system acquires the gate charge waveform in real time at a sampling frequency of 10 MHz. The characteristic parameters include threshold voltage, transconductance, and gate resistance. The aging model is based on a particle filter algorithm, and the device lifetime prediction error is less than 10%. The threshold voltage drift compensation range is -0.5 V to +0.8 V, the compensation step size is 50 mV, and the dynamic adjustment period is 1 minute.

10. The method for improving the efficiency of electric vehicle power electronic systems based on silicon substrate GaN HEMT as described in claim 1, characterized in that: In step S9, the multi-condition joint simulation and experimental verification platform needs to integrate six typical load spectra, such as urban roads, high-speed cruising, and rapid acceleration, and the battery charging and discharging simulation accuracy should reach ±0.5%. The simulation model includes electrothermal and mechanical multi-physics coupling, the mesh generation accuracy is 0.1 mm, and the calculation convergence time is less than 1 hour.

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