operational amplifiers and chips

Abstract

The application relates to an operational amplifier and a chip, wherein: an input end of a gain stage circuit is used for inputting an input signal, and the gain stage circuit is used for amplifying the signal; an input end of an impedance isolation circuit is connected with an output end of the gain stage circuit; an input end of an intermediate stage circuit is connected with an output end of the impedance isolation circuit, and the intermediate stage circuit is used for performing level shifting on the input signal; and an input end of an output stage circuit is connected with an output end of the intermediate stage circuit, and the output stage circuit is used for outputting an operational amplifier signal. The impedance isolation circuit is used for isolating the impedance of the intermediate stage circuit and the output impedance of the gain stage circuit. The operational amplifier has high working reliability, and under the condition that the operational amplifier is overloaded, the high output impedance of the gain stage circuit is not affected by the intermediate stage circuit, so that the operational amplifier can maintain high gain.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of operational amplifiers, in particular to an operational amplifier and a chip. BACKGROUND

[0002] When a MOS tube with a low threshold voltage is used as an output stage in a traditional CLASS-AB operational amplifier structure, the cascode stage MOS tube of the operational amplifier works in a linear region due to insufficient voltage margin, so that the output noise of the operational amplifier is increased and the gain is decreased, and meanwhile, when the output is driven under heavy load, the gain of the operational amplifier is further decreased, and the overall gain of the operational amplifier can be reduced to about fifty dB. SUMMARY

[0003] Therefore, it is necessary to provide an operational amplifier and a chip capable of maintaining high gain and stable operation.

[0004] In a first aspect, an operational amplifier is provided, comprising:

[0005] a gain stage circuit, an input end of the gain stage circuit being used for inputting an input signal, and the gain stage circuit being used for amplifying the signal;

[0006] an impedance isolation circuit, an output end of the gain stage circuit being connected to an input end of the impedance isolation circuit;

[0007] a middle stage circuit, an output end of the impedance isolation circuit being connected to an input end of the middle stage circuit, and the middle stage circuit being used for performing level shifting on the input signal;

[0008] an output stage circuit, an output end of the middle stage circuit being connected to an input end of the output stage circuit, and the output stage circuit being used for outputting an operational amplifier signal;

[0009] The impedance isolation circuit is used for isolating the impedance of the middle stage circuit and the output impedance of the gain stage circuit.

[0010] In an embodiment, the output stage circuit is a Class-AB output stage circuit.

[0011] In an embodiment, the impedance isolation circuit is a unity-gain impedance isolation circuit.

[0012] In an embodiment, the impedance isolation circuit comprises:

[0013] a first current source, an input end of the first current source being used for connecting to a power supply;

[0014] a first current mirror;

[0015] The first differential pair has its input terminal connected to the output terminal of the gain stage circuit, its output terminal connected to the input terminal of the intermediate stage circuit, its power supply terminal connected to the power supply via the first current source, and its ground terminal grounded via the first current mirror.

[0016] In one embodiment, the first differential pair is a PMOS differential pair and the first current mirror is an NMOS current mirror.

[0017] In one embodiment, the impedance isolation circuit includes:

[0018] Multiple cascaded single-stage amplifiers have input and output terminals. The input terminals of the multiple cascaded single-stage amplifiers are connected to the output terminal of the gain stage circuit, and the output terminals of the multiple cascaded single-stage amplifiers are connected to the input terminal of the intermediate stage circuit.

[0019] In one embodiment, the first single-stage amplifier of the plurality of cascaded single-stage amplifiers includes a second current source, a first PMOS transistor, and a first resistor connected in series between a power supply and ground.

[0020] The second single-stage amplifier of the multiple cascaded single-stage amplifiers includes a second resistor, a first NMOS transistor, and a third current source connected in series between the power supply and ground.

[0021] In this circuit, the gate of the first PMOS transistor is connected to the output of the gain stage circuit, the source of the first PMOS transistor is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is connected to the input of the intermediate stage circuit.

[0022] In one embodiment, the operational amplifier further includes:

[0023] The input differential pair transistors are connected to the input of the gain stage circuit, and their inputs are used to receive the input signal.

[0024] In one embodiment, the intermediate stage circuit includes:

[0025] Fourth current source;

[0026] Fifth current source;

[0027] The level shifter has its input connected to the output of an impedance isolation circuit, its output connected to the input of an output stage circuit, its power supply connected to a power source via a fourth current source, and its grounding point connected to ground via a fifth current source.

[0028] Secondly, a chip is provided, which includes the aforementioned operational amplifier.

[0029] The aforementioned operational amplifier and chip, by separating the level-shifting intermediate stage circuit from the gain stage circuit and using it as an intermediate stage between the gain stage and output stage circuits, avoids operational amplifier malfunctions due to insufficient voltage margin. Since the intermediate stage circuit does not use a cascode structure, the on-state voltage of the output stage circuit's switching transistor is related to the output voltage of the intermediate stage circuit. Therefore, even when the on-state threshold voltage of the output stage circuit is at a low level, the intermediate stage circuit can still operate in the saturation region. For example, a drop in threshold voltage can cause the cascode stage MOSFET to enter the linear region, resulting in a decrease in gain and an increase in input noise. In other words, the operational amplifier provided in this application improves operational amplifier reliability by setting an independent intermediate stage circuit between the gain stage and output stage circuits.

[0030] Furthermore, by setting an impedance isolation circuit between the gain stage circuit and the intermediate stage circuit, the impedance of the intermediate stage circuit and the output impedance of the gain stage circuit are isolated. The impedance isolation circuit acts as impedance isolation between the output node of the gain stage circuit and the input node of the intermediate stage circuit. When the operational amplifier is under heavy load, the high output impedance of the gain stage circuit is not affected by the intermediate stage circuit, thus allowing the operational amplifier to maintain high gain. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the circuit structure of an operational amplifier in an exemplary technology;

[0033] Figure 2 This is a schematic diagram of the circuit structure of an operational amplifier in another exemplary technology;

[0034] Figure 3 One of the circuit structure schematic diagrams of an operational amplifier in one or more embodiments;

[0035] Figure 4 One of the circuit structure schematic diagrams of an operational amplifier in one or more embodiments;

[0036] Figure 5 One of the circuit structure schematic diagrams of an operational amplifier in one or more embodiments;

[0037] Figure 6 One of the circuit structure schematic diagrams of an operational amplifier in one or more embodiments;

[0038] Figure 7 One of the circuit structure schematic diagrams of an operational amplifier in one or more embodiments;

[0039] Figure 8 This is a schematic diagram of the circuit structure of an operational amplifier according to one or more embodiments. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0043] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0044] Traditional CLASS AB operational amplifiers typically consist of a two-stage structure. The first stage uses a cascode structure to increase the output impedance of the first stage, thereby improving the overall gain of the op-amp. The second stage uses a pair of NMOS and PMOS transistors with high transconductance Gm as a rail-to-rail output stage, which gives the op-amp a large drive capability, typically capable of driving tens or even hundreds of mA of current.

[0045] like Figure 1The diagram illustrates an exemplary technique using a CLASS-AB operational amplifier structure with a transconductance linear loop. It primarily comprises input differential pairs MP1 and MP2, a first-stage cascode 1, and a second-stage output stage 2. Assuming the operational amplifier operates under ideal voltage conditions and the MOSFETs are ideal transistors, the operational amplifier exhibits good performance when its threshold voltage Vth is around 0.7V. However, in practical applications, operational amplifiers may need to operate at a power supply voltage of 1.8V or lower. To ensure proper circuit operation, low threshold voltage MOSFETs (threshold voltage below 0.7V) are typically required. For example, low threshold voltage core devices usually have a threshold voltage of only around 300mV, or some advanced 1.8V devices may also have a threshold voltage of only slightly over 300mV.

[0046] When the threshold voltage of the MOSFET in the operational amplifier is too low, Figure 1 Operational amplifiers with certain structures may malfunction at high temperatures due to insufficient voltage margin. For example, Figure 1 In the circuit, the VGS (gate-source voltage) of switching transistor PM10 is equal to the VDS (drain-source voltage) of switching transistor MP6 plus the VDS of switching transistor MP4. Similarly, the VGS of switching transistor NM8 is equal to the VDS of switching transistor NM2 plus the VDS of switching transistor NM4. When the threshold voltage Vth of switching transistor PM10 or NM8 is only about 300mV, its corresponding VGS is also very small (according to the MOSFET current formula I=KW(VGS-Vth)2 / L (K is the transconductance parameter, characterizing the conductivity of the MOSFET), when the quiescent current I remains constant, in order to increase the driving capability of the operational amplifier, the width-to-length ratio (W / L) of the output stage MOSFET is usually very large, so VGS-Vth will be very small, and the value of VGS will also become very small, close to 300mV). In addition, according to Vdsat=VGS-Vth, it is necessary to ensure that the value of Vdsat (drain-source saturation voltage) is greater than 200mV so that the MOSFET operates in the saturation region. Therefore, the sum of VDS of switching transistor MP6 and VDS of switching transistor MP4, and the sum of VDS of switching transistor NM2 and VDS of switching transistor NM4, must be greater than 400mV to ensure that each MOSFET operates in the saturation region. Obviously, the VGS voltage of approximately 300mV for switching transistors PM10 and NM8 in the output stage circuit cannot meet the requirements. Therefore, operational amplifier malfunctions due to insufficient voltage margin will occur.

[0047] Under some extreme conditions, such as at 120°C in a Fast-Fast Corner (FF Corner), the threshold voltage may drop further, possibly to only around 200mV. This could potentially lead to… Figure 1If the switching transistors NM2, NM4, MP6, or MP4 enter the linear region, the gain of the operational amplifier will decrease, and even the equivalent input noise will increase, thus reducing the performance of the operational amplifier.

[0048] To solve this problem, in one exemplary technology, such as Figure 2 As shown, an operational amplifier structure is proposed that can avoid the problem of the cascode stage MOS transistors of the operational amplifier entering the linear region due to a too small threshold voltage Vth. Specifically, as... Figure 2 As shown, the transconducting linear loop is separated from the first-stage cascode 1 and used as intermediate stage 3 between the first-stage cascode 1 and the second-stage output stage 2. Since intermediate stage 3 does not use a cascode structure, the VGS of the switching transistor PM20 in the second-stage output stage 2 is equal to the VDS of the current source M5, and the VGS of the switching transistor NM18 is equal to the VDS of the current source M6. Therefore, as long as the threshold voltage Vth of the switching transistors PM20 and NM18 is maintained at around 200mV, the P current source M5 and N current source M6 can operate in the saturation region. That is, even in core devices with low threshold voltages or some advanced 1.8V device applications, the operational amplifier can still operate normally.

[0049] Figure 2 The impedance at point C is equal to the output impedance of the first cascode stage 1 (Gm). NM14 *R NM12 *R NM14 ,Gm NM14 For the transconductance of NM14, R NM12 R is the equivalent impedance of NM12. NM14 The equivalent impedance of NM14 is connected in parallel with the output impedance R5 of the intermediate stage 3 current mirror M5. Since intermediate stage 3 does not use a cascode structure, its impedance is lower than the output impedance (Gm) of the first cascode stage 1. NM14 *R NM12 *R NM14 / / Gm MP16 *R MP16 *R MP14 The gain of the operational amplifier is reduced by several orders of magnitude, resulting in a decrease in the gain of the Gm amplifier. MP11 *(Gm) NM14 *R NM12 *R NM14 / / Gm MP16 *R MP16 *R MP14 )*G NM18 *R out Reduce to Gm MP11 *(R5 / / R6)*GNM18 *R out Because the equivalent impedance Rout of the second output stage 2 is very low, the gain Av = Gm * Rout of the second output stage 2 is also very small. When the operational amplifier is heavily driven, it may even have a negative gain, resulting in a very small overall gain of the operational amplifier. Simulations show that... Figure 2 In a test case under the structure, when the operational amplifier output drives a 32-ohm resistor, the operational amplifier only has a gain of more than 40 dB, which means that there is a problem of gain reduction caused by the operational amplifier being heavily loaded.

[0050] To address the above problems, in one embodiment, such as Figure 3 As shown, an operational amplifier is provided, including: a gain stage circuit 10, an impedance isolation circuit 20, an intermediate stage circuit 30, and an output stage circuit 40.

[0051] The input terminal of the gain stage circuit 10 is used to receive the input signal VIN, and the gain stage circuit 10 is used to amplify the signal. The gain stage circuit 10 may include a gain circuit composed of multiple MOSFETs to provide signal amplification capability. After amplifying the input signal VIN, it outputs the signal. For example, the gain stage circuit 10 may be a cascode circuit.

[0052] The input of impedance isolation circuit 20 is connected to the output of gain stage circuit 10. The input of intermediate stage circuit 30 is connected to the output of impedance isolation circuit 20. Intermediate stage circuit 30 is used to level-shift the input signal. Intermediate stage circuit 30 has no cascode structure and is used to level-shift the input signal to provide a DC operating point for output stage circuit 40. The input of output stage circuit 40 is connected to the output of intermediate stage circuit 30. Output stage circuit 40 is used to output the operational amplifier signal Vout. Impedance isolation circuit 20 isolates the impedance of intermediate stage circuit 30 from the output impedance of gain stage circuit 10.

[0053] The operational amplifier provided in this application embodiment uses an intermediate stage circuit 30 for level shifting, which is independent of the gain stage circuit 10 and serves as an intermediate stage between the gain stage circuit 10 and the output stage circuit 40. Since no cascode structure is used, the on-state voltage of the switch in the output stage circuit 40 depends on the output voltage of the intermediate stage circuit 30. Therefore, even when the on-state threshold voltage of the switch in the output stage circuit 40 is at a low level, the intermediate stage circuit 30 can still operate in the saturation region, thus avoiding operational amplifier malfunctions due to insufficient voltage margin. For example, a drop in threshold voltage can cause the MOSFET to enter the linear region, resulting in a decrease in gain and an increase in input noise. In other words, the operational amplifier provided in this application embodiment improves operational amplifier reliability by providing an independent intermediate stage circuit 30 between the gain stage circuit 10 and the output stage circuit 40.

[0054] Furthermore, by providing an impedance isolation circuit 20 between the gain stage circuit 10 and the intermediate stage circuit 30, the impedance of the intermediate stage circuit 30 and the output impedance of the gain stage circuit 10 are isolated. The impedance isolation circuit 20 serves as impedance isolation between the output node of the gain stage circuit 10 and the input node of the intermediate stage circuit 30. When the operational amplifier is under heavy load, the high output impedance of the gain stage circuit 10 is not affected by the intermediate stage circuit 30, thereby allowing the operational amplifier to maintain high gain.

[0055] In one embodiment, the output stage circuit is a Class-AB output stage circuit.

[0056] Compared to Class-A output stage circuits, Class-AB output stage circuits consume less power when processing signals of the same power, reducing energy waste and improving efficiency. Furthermore, by using appropriate bias circuitry, the Class-AB output stage circuit allows a certain quiescent current to flow through the output stage's switching transistors, placing them in a slightly conductive state. Even with a small input signal, the switching transistors can still linearly amplify the signal, smoothly connecting the positive and negative half-cycles of the output signal and reducing crossover distortion. Additionally, when the operational amplifier's output stage circuit is Class-AB, the switching transistors can dynamically adjust their conduction level according to the amplitude of the input signal, making it suitable for various applications with different output power requirements.

[0057] In one embodiment, the impedance isolation circuit is a unity-gain impedance isolation circuit.

[0058] When the impedance isolation circuit is a unity-gain impedance isolation circuit, its overall gain is 1, serving as an isolation impedance and providing no gain. Therefore, the output impedance of each node in a unity-gain impedance isolation circuit is very low, providing only high-frequency poles, and no low-frequency poles are introduced in the intermediate stages. In frequency response, poles cause signal phase lag. High-frequency poles mean that significant phase lag only occurs at higher frequencies, while low-frequency phase changes are small, making it less prone to stability problems caused by large phase shifts at low frequencies. When high-frequency poles are dominant, the phase shift is small in the low-frequency range, giving the operational amplifier a wider stable phase margin in the low-frequency range. This makes the gain distribution across the entire frequency range easier to manage, and makes it easier to ensure that the loop gain is less than 1 when the phase shift reaches 180° during compensation design, satisfying the stability condition and reducing the difficulty of operational amplifier loop compensation.

[0059] In one embodiment, such as Figure 4 As shown, the impedance isolation circuit 20 includes: a first current source M11, a first current mirror 21, and a first differential pair transistor 22.

[0060] The input terminal of the first current source M11 is used to connect to the power supply. The input terminal of the first differential pair transistor 22 is connected to the output terminal of the gain stage circuit 10, the output terminal of the first differential pair transistor 22 is connected to the input terminal of the intermediate stage circuit 30, the power supply terminal of the first differential pair transistor 22 is connected to the power supply through the first current source M11, and the ground terminal of the first differential pair transistor 22 is grounded through the first current mirror 21.

[0061] The first current source M11, the first current mirror 21, and the first differential pair transistor 22, utilizing their high impedance characteristics and current handling capabilities, work together to effectively reduce the impedance interaction between the gain stage circuit 10 and the intermediate stage circuit 30, thereby achieving impedance isolation. Specifically, the first current source M11 has a high output impedance characteristic and a constant output current. The current in the first current source M11 is obtained by mirroring the input current provided by the input current source (not shown in the figure). Therefore, due to the large input impedance of the impedance isolation circuit 20 (which is why...), the impedance isolation circuit 20... Figure 4 The gate resistance of the MOS transistor MP37 shown is very large. When a large resistor is connected in parallel with a relatively small resistor, the total resistance is approximately equal to the relatively small resistor. Therefore, the output impedance of the gain stage circuit 10 is approximately equal to its own output resistance. Meanwhile, the impedance of the intermediate stage circuit 30 is connected to the output stage of the impedance isolation circuit 20. The input and output of the impedance isolation circuit 20 are not connected, so the impedance of the intermediate stage circuit 30 is isolated from the impedance of the gain stage circuit 10. This ensures that the output impedance of the gain stage circuit 10 is not directly affected by changes in the impedance of the intermediate stage circuit 30, maintaining the stability of the signal in the gain stage circuit 10. When the first differential pair transistor 22 obtains a signal from the gain stage circuit 10, it draws very little current, reducing the load effect on the gain stage circuit 10.

[0062] In one embodiment, such as Figure 4 and Figure 5 As shown, the first differential pair 22 is a PMOS differential pair, for example, Figure 4 and Figure 5 The PMOS transistors MP37 and MP38 are described. MP37's gate is connected to the output terminal F of the gain stage circuit 10, its source is connected to the power supply VCC via the first current source M11, and its drain is grounded via the first current mirror 21. Similarly, MP38's gate is connected to the input terminal G of the intermediate stage circuit 30, its source is connected to the power supply VCC via the first current source M11, and its drain is grounded via the first current mirror 21. The gate and drain of MP38 are connected in series.

[0063] The PMOS differential pair transistors have high input impedance and draw very little current from the signal source, thus reducing the load effect on the signal source of the gain stage circuit 10. This ensures that the output signal of the gain stage circuit 10 is not affected by the intermediate stage circuit 30, enabling more accurate signal transmission. Furthermore, due to the structural characteristics of the differential pair transistors, they can effectively suppress common-mode signal interference. Because the MOS transistor MP38 is connected in a diode configuration, its equivalent impedance is approximately 1 / Gm. MP38 (Gm) MP38 Because of the transconductance of MP38, the output impedance of impedance isolation circuit 20 is very low, which allows the output signal to be transmitted more stably to intermediate stage circuit 30.

[0064] In one embodiment, such as Figures 4-5 As shown, the first current mirror 21 is an NMOS current mirror. For example, the first current mirror includes, as shown below... Figure 4 and Figure 5 The NM35 and NM36 are described above. The drain of NM35 is connected to the drain of MP37, the source of NM35 is grounded, the gate of NM35 is connected to the gate of NM36, and the gate and drain of NM35 are also connected. The drain of NM36 is connected to the drain of MP38, and the source of NM36 is grounded.

[0065] Specifically, the NMOS current mirror provides a stable bias current for the PMOS differential pair, ensuring that the PMOS differential pair operates at a suitable quiescent operating point. In addition, the NMOS current mirror has a high output impedance, enabling it to provide a relatively stable current source to the load, reducing the impact of load variations on the output current and ensuring circuit stability and performance.

[0066] To better illustrate the implementation process of the operational amplifier provided in the embodiments of this application, as follows... Figure 5 The following is an example of a specific circuit:

[0067] The unity-gain impedance isolation circuit is a unity-gain five-transistor operational amplifier structure, including a P-current mirror M11, PMOS differential pairs MP37 and MP38, and NMOS current mirrors NM35 and NM36. Among them, MP37 and MP38, and NM35 and NM36 are of equal size and have the same quiescent current.

[0068] In this structure, the output terminal F of the gain stage circuit 10 and the input terminal G of the intermediate stage circuit 30 are connected to the gates of MP37 and MP38 in the first differential pair transistor 22, respectively. Therefore, the impedance isolation circuit 20 successfully separates the impedances of points F and G, making them independent of each other. The output impedance at point F is equal to the output impedance Gm of the gain stage circuit 10. NM34 *R NM32 *R NM34 / / Gm MP36 *R MP36 *R MP34 The gain is Gm of the input differential pair transistor 50 multiplied by the output impedance of the gain stage circuit 10, i.e., Gm MP32 *(Gm) NM34 *R NM32 *R NM34 / / Gm MP36 *R MP36 *R MP34 ), where Gm represents transconductance, R represents resistance, and the subscript indicates the corresponding device. The gain from point F to point G is (GM MP37 / GM NM35 )*(GM NM36 / GM MP38 Since MP37 and MP38, and NM35 and NM36 have the same size and quiescent current, their Gm values ​​are also equal. Therefore, the overall gain of impedance isolation circuit 20 is 1, serving only to isolate impedance and not providing any gain. Furthermore, the output impedance of each node in impedance isolation circuit 20 is very low, so it only provides high-frequency poles, reducing the difficulty of loop compensation. The output impedance of output stage circuit 40 is equal to the impedance of PM41 in parallel with the impedance of NM40 in parallel with the impedance of Rout. Under heavy load conditions, Rout is much smaller than the impedances of PM41 and NM40, so the output impedance of output stage circuit 40 is approximately equal to Rout, and the output stage gain is G. NM40 *Rout. The overall gain of the operational amplifier is Gm. MP32 *(Gm) NM34 *R NM32 *R NM34 / / Gm MP36 *R MP36 *R MP34 )*G NM40 *R OUTThe impedance isolation circuit 20 effectively isolates the gain stage circuit 10 from the intermediate stage circuit 30, enabling the operational amplifier to achieve high gain.

[0069] In one embodiment, such as Figures 6-7 As shown, the impedance isolation circuit 20 includes multiple cascaded single-stage amplifiers.

[0070] Multiple cascaded single-stage amplifiers have input and output terminals. The input terminals of the multiple cascaded single-stage amplifiers are connected to the output terminal of the gain stage circuit, and the output terminals of the multiple cascaded single-stage amplifiers are connected to the input terminal of the intermediate stage circuit.

[0071] Single-stage amplifiers 23 typically have high input impedance. When multiple single-stage amplifiers 23 are cascaded, the current drawn from the gain stage circuit 10 is minimal, significantly reducing the load effect on the output impedance of the gain stage circuit 10. This ensures that the output characteristics of the gain stage circuit 10 are not significantly altered by the connection of the intermediate stage circuit 30, guaranteeing that the gain stage circuit 10 can operate relatively independently. Furthermore, the output impedance of single-stage amplifiers 23 is relatively low, making their output signal less susceptible to changes in the input impedance of the intermediate stage circuit 30. Even if the input impedance of the intermediate stage circuit 30 fluctuates, the outputs of the multiple cascaded single-stage amplifiers can still provide a relatively stable signal, preventing the impedance characteristics of the intermediate stage circuit 30 from feeding back into the gain stage circuit 10. During the transmission of the input signal from the gain stage circuit 10 to the intermediate stage circuit 30 and the output stage circuit 40, each single-stage amplifier 23 reduces mutual coupling through its own input and output characteristics, enhancing the isolation effect between the gain stage circuit 10 and the intermediate stage circuit 30.

[0072] In one embodiment, such as Figure 7 As shown, the first single-stage amplifier of the multiple cascaded single-stage amplifiers includes a second current source, a first PMOS transistor, and a first resistor connected in series between the power supply and ground. The second single-stage amplifier of the multiple cascaded single-stage amplifiers includes a second resistor, a first NMOS transistor, and a third current source connected in series between the power supply and ground.

[0073] In this circuit, the gate of the first PMOS transistor is connected to the output of the gain stage circuit, the source of the first PMOS transistor is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is connected to the input of the intermediate stage circuit.

[0074] Specifically, such as Figure 7As shown, the second current source M15 acts as a pull-up current source, providing a constant current. Its high output impedance characteristic makes the drain of the first PMOS transistor MP47 (connected to the first resistor R3) equivalent to a high-impedance node, reducing the load effect of the subsequent circuit on the gain stage circuit 10. The gate of the first PMOS transistor MP47 (connected to the output of the gain stage circuit 10) is a high-impedance node, drawing almost no current, thus avoiding a load effect on the gain stage circuit 10. Due to the high impedance of the second current source M15, the drain voltage change of MP47 is mainly determined by the first resistor R3. The source voltage of the first PMOS transistor MP47 depends only on the gate voltage and is independent of the input impedance of the subsequent circuit, achieving impedance isolation from the subsequent circuit.

[0075] Meanwhile, the third current source M16 acts as a pull-down current source, providing a constant current. Its high output impedance makes the source of the first NMOS transistor NM46 (connected to the input terminal J of the intermediate stage circuit 30) equivalent to a high-impedance node, thereby isolating the input impedance of the intermediate stage circuit 30 from the preceding stage circuit and reducing the load effect of the preceding stage circuit on the intermediate stage circuit 30. The gate of the first NMOS transistor NM46 (connected to the source of the first PMOS transistor) is also a high-impedance node, further isolating the impedance interaction between the preceding and following stages.

[0076] The first and second single-stage amplifiers work together. The gates of the first PMOS transistor MP47 and the first NMOS transistor NM46 are both high-impedance nodes, ensuring that the output of the gain stage circuit 10 does not need to drive a low-impedance load, effectively isolating the output impedance of the gain stage circuit 10. Furthermore, the source output impedance of the first NMOS transistor NM46 is low, providing a stable signal to the intermediate stage circuit 30 without being affected by changes in the input impedance of the intermediate stage circuit 30. This maintains the operational amplifier's reliability even under heavy load conditions.

[0077] To better illustrate the implementation process of the operational amplifier provided in the embodiments of this application, as follows... Figure 7 The structure shown is used as an example for explanation:

[0078] Figure 7 The impedance isolation circuit 20 includes two source-output single-stage amplifiers: one using MP47 as the source output and the other using NM45 as the source output. The output of the gain stage circuit 10 is connected to the gate of MP47 in the impedance isolation circuit 20, therefore the output impedance at point H is determined by the gain stage circuit 10, and the output impedance is Gm. NM44 *R NM44 *R NM42 / / Gm MP46 *R MP46 *R MP44 Among them, Gm NM44 For NM 44transconductance, R NM44 For NM 44 Equivalent impedance, R NM42 For NM 42 Equivalent impedance, Gm MP46 For MP 46 Transconductance, R MP46 For MP 46 Equivalent impedance, R MP44 For MP 44 Equivalent impedance. The gain at point H is Gm. MP42 *(Gm) NM44 *R NM42 *R NM44 / / Gm MP46 *R MP46 *R MP44 Among them, Gm MP42 For NM 42 The transconductance. Because the gain of the cascaded source amplifier composed of MP47 and NM45 is very small, close to unity gain. The impedance isolation circuit 20 mainly serves to isolate the impedance and does not provide gain. The output impedance of the output stage circuit 40 is equal to the impedance of PM50 in parallel with the impedance of NM50 in parallel with the impedance of Rout. Under heavy load conditions, Rout is much smaller than the impedance of MOSFETs PM50 and NM50 in the output stage circuit 40. Therefore, the output impedance of the output stage circuit 40 is approximately equal to Rout, and the output stage gain is G. NM50 *R out The overall gain of the operational amplifier is Gm. MP42 *(Gm) NM44 *R NM42 *R NM44 / / Gm MP46 *R MP46 *R MP44 )*G NM50 *R out Impedance isolation circuit 20 effectively isolates the gain stage circuit 10 from the intermediate stage circuit 30, ensuring that the operational amplifier maintains high gain even under heavy load conditions.

[0079] In one embodiment, such as Figures 4-7 As shown, the operational amplifier also includes an input differential pair transistor 50. The output terminal of the input differential pair transistor 50 is connected to the input terminal of the gain stage circuit 10, and the input terminal of the input differential pair transistor 50 is used to receive the input signal, which is a differential signal. The input differential pair transistor 50 amplifies the received differential signal, but its amplification capability for common-mode signals is extremely weak, thus effectively suppressing common-mode interference. For example, in the application scenario of operational amplifiers for sensor signals, the weak differential signal output by the sensor is often accompanied by strong common-mode noise (such as power frequency interference). The input differential pair transistor 50 can filter out the noise and retain the true signal.

[0080] In one embodiment, the input differential pair transistor 50 is a MOSFET. The gate of the MOSFET is insulated and it draws almost no current, so the load effect on the signal source connected to the operational amplifier is negligible.

[0081] In one embodiment, such as Figure 7 As shown, the input differential pair transistors 50 may include PMOS transistors MP41 and MP42. MP41's gate is connected to the signal VIN, and MP42's gate is connected to the signal VCM. The source of MP41 is connected to the power supply VCC via a current source M14, and the drain of MP41 is connected to the input terminal of the gain stage circuit 10. The source of MP42 is connected to the power supply VCC via a current source M14, and the drain of MP42 is connected to the input terminal of the gain stage circuit 10.

[0082] Optionally, the drains of MP41 and MP42 are connected to the current mirror in the gain stage circuit 10 to realize the transmission of the input signal to the gain stage circuit 10.

[0083] For example, such as Figure 8 As shown, the input differential pair transistor 50 transmits the input signals VIN and VCM to the amplifier circuit 12 through the current mirror 11 in the gain stage circuit 10. After being amplified by the amplifier circuit 12, the signals are transmitted to the impedance isolation circuit 20. This achieves current-mode signal amplification, avoids voltage-to-current conversion losses, and improves efficiency.

[0084] In one embodiment, such as Figure 8 As shown, the intermediate stage circuit 30 includes a fourth current source M8, a fifth current source M9, and a level shifter 31.

[0085] like Figure 8 In this embodiment, the input terminal of the level shifter 31 is connected to the output terminal E of the impedance isolation circuit 20, the output terminal of the level shifter 31 is connected to the input terminal of the output stage circuit 40, the power supply terminal of the level shifter 31 is connected to the power supply VCC through the fourth current source M8, and the grounding point of the level shifter 31 is grounded through the fifth current source M9.

[0086] like Figure 8 The diagram illustrates the process of intermediate signal processing achieved through the coordination between a current source and a level shifter.

[0087] The fourth current source M8 is connected to the power supply VCC and the power supply terminal of the level shifter 31, and a constant current is supplied to the high potential terminal of the level shifter 31 (e.g., Figure 8 A stable DC bias is provided at the source of the PMOS transistor MP27 or the drain of the NMOS transistor NM25. This ensures that the input stage transistor of the level shifter 31 operates in the saturation region, avoiding bias point drift caused by voltage fluctuations in the power supply VCC or load changes, and achieving linear level conversion.

[0088] In addition, the high output impedance of the fourth current source M8 can isolate high-frequency noise in the power supply VCC, prevent noise from being directly coupled to the power supply terminal of the level shifter 31, and suppress power supply noise.

[0089] The fifth current source M9 is connected to the ground point of the level shifter 31 and ground GND respectively, and provides a constant current to the low potential terminal of the level shifter 31 (e.g., Figure 8 The source of the NMOS transistor NM26 or the drain of the PMOS transistor MP28 provides a stable DC reference. This ensures that the low-level output of the level shifter 31 is not affected by changes in the input impedance of the subsequent circuit, maintaining the accuracy of the level shift.

[0090] The operational amplifier provided in this application embodiment can ensure the reliability and accuracy of level shifting by connecting a current source in series at the high potential end and the low potential end of the level shifter.

[0091] To better illustrate the implementation process of the operational amplifier in the embodiments of this application, the following will be used as an example. Figure 8 The structure shown is illustrated with an example as follows:

[0092] MOSFETs MP21 and MP22 form the input differential pair 50. The transconductances of MP21 and MP22 are Gm and Gm, respectively. MP21 and Gm MP22 NM21, NM22, NM23, NM24 and MP23, MP24, MP25, MP26 constitute the gain stage circuit 10, whose output impedance is (Gm) NM24 *R NM22 *R NM24 / / Gm MP26 *R MP26 *R MP24 The intermediate stage circuit 30 includes current mirrors M8 and M9, and MOSFETs NM25, MP27, MP28, and NM26. NM25, MP27, MP28, and NM26 form a level shifter, ensuring a stable quiescent DC operating point for MOSFETs PM30 and NM28 in the output stage circuit 40. The output impedance of the intermediate stage circuit 30 is equal to the impedance R8 of M8 in parallel with the impedance R9 of M9 (i.e., R8 / / R9). The output stage circuit 40 can use two large-sized MOSFETs, PM30 and NM28, to meet strong drive requirements. The output impedances of PM30 and NM28 are R... PM30 and R NM28 If the output terminal Vout of the operational amplifier is connected to a small resistor Rout as a load, then the equivalent output impedance of the output stage circuit 40 is Rout.

[0093] In this circuit structure, the input signal is input from the input differential pair transistor 50, and after being amplified to point D by the gain stage circuit 10, the input signal is amplified by Av1=Gm. MP21 *(Gm) NM24 *R NM22 *R NM24 / / Gm MP26 *R MP26 *R MP24 The signal amplified by the gain stage circuit 10 is output from point D to point E through the impedance isolation circuit 20. This circuit isolates the impedances of points D and E, but does not amplify the input signal at point D. Therefore, the signal at point E is equal to the signal at point D, and the signal from the input differential pair transistor 50 to point E is still only amplified by Av1. Furthermore, because the level shifter composed of NM25, MP27, MP28, and NM26 provides a stable quiescent operating point for the MOS transistors in the output stage circuit 40, it does not provide impedance isolation. Therefore, the impedance at point E is equal to R8 / / R9 / / R buffer (R) buffer (This is the equivalent impedance of the impedance isolation circuit 20). Since the impedance isolation circuit 20 mainly functions as an isolation impedance, its gain is very small, close to 1, so the output impedance R of the impedance isolation circuit 20 is... buffer The impedance at point E is very small; R8 / / R9 / / R buffer It is also very small, so the intermediate stage circuit 30 will not introduce low-frequency poles, reducing the difficulty of loop compensation.

[0094] The impedance isolation circuit 20 isolates the gain stage circuit 10 from the intermediate stage circuit 30. Figure 8 The gain of the operational amplifier is determined by Gm when there is no impedance isolation circuit 20. MP21 *(R8 / / R9)*G NM28 *Rout increases to Gm MP21 *(Gm) NM24 *R NM22 *R NM24 / / Gm MP26 *R MP26 *R MP24 )*G NM28 *Rout increases the gain by several orders of magnitude.

[0095] It should be noted that, in the examples of the above embodiments, in Figures 3-8 In different embodiments, the components of each circuit are labeled differently, but this does not affect those skilled in the art's understanding of the working principles of, for example, the gain stage circuit 10, the intermediate stage circuit 30, and the output stage circuit 40. Under the same circuit structure, its working principle can be referred to the description in the above embodiments, and will not be repeated here.

[0096] The operational amplifiers provided in this application are applicable not only to single-ended operational amplifiers but also to fully differential operational amplifiers.

[0097] In the two test cases, the operational amplifier provided in the embodiments of this application was used, and the gain was significantly improved to 88dB and 91dB respectively compared to the original 47dB under high temperature and heavy load at FF Corner.

[0098] In one embodiment, this application also provides a chip including the aforementioned operational amplifier. The chip equipped with the operational amplifier achieves reliable operation by providing an independent intermediate stage circuit 30 between the gain stage circuit 10 and the output stage circuit 40. Furthermore, under heavy load conditions, the high output impedance of the gain stage circuit 10 is unaffected by the intermediate stage circuit 30, maintaining high gain.

[0099] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An operational amplifier characterized by comprising: The application relates to an operational amplifier circuit, comprising: a gain stage circuit, an input end of the gain stage circuit being used for accessing an input signal, the gain stage circuit being used for amplifying the signal; an impedance isolation circuit, an input end of the impedance isolation circuit being connected with an output end of the gain stage circuit; an intermediate stage circuit, an input end of the intermediate stage circuit being connected with an output end of the impedance isolation circuit, the intermediate stage circuit being used for performing level shifting on the accessed signal; an output stage circuit, an input end of the output stage circuit being connected with an output end of the intermediate stage circuit, the output stage circuit being used for outputting an operational signal; wherein the impedance isolation circuit is used for isolating the impedance of the intermediate stage circuit and the output impedance of the gain stage circuit; the impedance isolation circuit is a unit gain impedance isolation circuit; the impedance isolation circuit comprises: a first current source, an input end of the first current source being used for connecting with a power supply; a first current mirror; a first differential pair transistor, an input end of the first differential pair transistor being connected with an output end of the gain stage circuit, an output end of the first differential pair transistor being connected with an input end of the intermediate stage circuit, a power supply end of the first differential pair transistor being connected with the power supply through the first current source, a grounding end of the first differential pair transistor being grounded through the first current mirror; the intermediate stage circuit comprises: a fourth current source; a fifth current source; a level shifter, an input end of the level shifter being connected with an output end of the impedance isolation circuit, an output end of the level shifter being connected with an input end of the output stage circuit, a power supply end of the level shifter being connected with a power supply through the fourth current source, a grounding end of the level shifter being grounded through the fifth current source.

2. The operational amplifier of claim 1, wherein, the output stage circuit is a Class-AB output stage circuit.

3. The operational amplifier according to claim 1 or 2, characterized by the first differential pair transistor is a PMOS differential pair transistor, and the first current mirror is an NMOS current mirror.

4. The operational amplifier according to claim 1 or 2, wherein The application further comprises: an input differential pair transistor, an output end of the input differential pair transistor being connected with an input end of the gain stage circuit, an input end of the input differential pair transistor being used for accessing the input signal.

5. An operational amplifier characterized by comprising: The application relates to an operational amplifier circuit, comprising: a gain stage circuit, an input end of the gain stage circuit being used for accessing an input signal, the gain stage circuit being used for amplifying the signal; an impedance isolation circuit, an input end of the impedance isolation circuit being connected with an output end of the gain stage circuit; an intermediate stage circuit, an input end of the intermediate stage circuit being connected with an output end of the impedance isolation circuit, the intermediate stage circuit being used for performing level shifting on the accessed signal; an output stage circuit, an input end of the output stage circuit being connected with an output end of the intermediate stage circuit, the output stage circuit being used for outputting an operational signal; wherein the impedance isolation circuit is used for isolating the impedance of the intermediate stage circuit and the output impedance of the gain stage circuit; the impedance isolation circuit is a unit gain impedance isolation circuit; the impedance isolation circuit comprises: a plurality of cascaded single-stage amplifiers, having an input end and an output end, the input end of the plurality of cascaded single-stage amplifiers being connected with an output end of the gain stage circuit, the output end of the plurality of cascaded single-stage amplifiers being connected with an input end of the intermediate stage circuit; the intermediate stage circuit comprises: a fourth current source; a fifth current source; a level shifter, an input end of the level shifter being connected with an output end of the impedance isolation circuit, an output end of the level shifter being connected with an input end of the output stage circuit, a power supply end of the level shifter being connected with a power supply through the fourth current source, a grounding end of the level shifter being grounded through the fifth current source. A level shifter, an input terminal of the level shifter is connected to an output terminal of the impedance isolation circuit, an output terminal of the level shifter is connected to an input terminal of the output stage circuit, a power supply terminal of the level shifter is connected to a power supply through the fourth current source, and a ground terminal of the level shifter is grounded through the fifth current source.

6. The operational amplifier of claim 5, wherein, The output stage circuit is a Class-AB output stage circuit.

7. The operational amplifier according to claim 5 or 6, characterized in that, The first single-stage amplifier of the plurality of cascaded single-stage amplifiers comprises a second current source, a first PMOS tube and a first resistor connected in series between a power supply and a ground in sequence; The second single-stage amplifier of the plurality of cascaded single-stage amplifiers comprises a second resistor, a first NMOS tube and a third current source connected in series between the power supply and the ground in sequence; The gate of the first PMOS tube is connected to an output terminal of the gain stage circuit, the source of the first PMOS tube is connected to the gate of the first NMOS tube, and the source of the first NMOS tube is connected to an input terminal of the intermediate stage circuit.

8. The operational amplifier of claim 5 or 6, wherein, Further comprising: An input differential pair tube, an output terminal of the input differential pair tube is connected to an input terminal of the gain stage circuit, and an input terminal of the input differential pair tube is used to input the input signal.

9. A chip, characterized by The chip comprises the operational amplifier according to any one of claims 1-8.

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