Dynamic self-bias comparator

Abstract

The invention discloses a dynamic self-bias comparator, which comprises a preamplification device and a latch, and is characterized in that the preamplification device comprises a dynamic self-bias module; the preamplification device is used for amplifying a tiny input signal difference of an input signal to a voltage range which can be identified by the latch, and the latch is used for outputting a comparison result according to a result of the preamplification device through a positive feedback mechanism; and the dynamic self-bias module enables a part of bias voltage of the comparator to dynamically change along with the working state of the comparator. The comparator has the same comparator speed as the existing comparator under the condition of small signal input, and has higher comparison speed, the comparison time is saved, and the sampling rate is improved under the condition of large signal input.

Description

Technical Field

[0001] This invention relates to digital-to-analog converters in the field of analog integrated circuit design, and more particularly to a dynamic self-biased comparator in digital-to-analog converters. Background Technology

[0002] As a bridge between the analog and digital domains, comparators play a crucial role in the field of analog-to-digital converters (ADCs), and their performance has a decisive impact on the overall performance of the ADC. SA comparators are widely popular in high-speed ADCs, especially successive approximation ADCs (SAR ADCs), which offer advantages such as high comparator speed, zero static power consumption, and low input equivalent noise. However, achieving low input equivalent noise requires methods such as reducing bias current, increasing the size of the input differential pair, and increasing the voltage at the preamplifier output node in the reset state. Reducing the bias current decreases the comparator speed, increasing the size of the input differential pair increases the load on the pre-stage buffer, and increasing the node voltage presents reliability issues at some advanced process nodes. Therefore, comparator design requires trade-offs in power consumption, speed, and noise. In high-speed SerDes applications such as DSP-based systems, a comparator with high comparison speed and suitable input equivalent noise is often desired. Although many comparator structures have improved performance—for example, the Elzakker comparator increases operating speed, and comparators with degraded capacitor sources and floating inverter amplifiers reduce input equivalent noise—SA comparators remain popular in high-speed, mid-precision ADCs due to trade-offs in speed, power consumption, noise, and area. To meet the requirements of mid-precision ADCs with single-channel sampling rates above 1 GS / s, the speed of the comparators in the ADC needs to be increased. However, application requirements dictate the comparator noise, thus limiting the comparator's speed. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a dynamic self-biased comparator. By adjusting the size of the bias current transistor, and due to the different rates of decrease in the common-mode voltage at the dynamic self-biased node, the comparator achieves the same comparator speed as existing comparators under small-signal input conditions, and exhibits even faster comparison speed under large-signal input conditions.

[0004] The specific technical solution is as follows:

[0005] A dynamic self-biased SA comparator includes a preload amplifier and a latch. The preload amplifier includes a dynamic self-biasing module. The preload amplifier includes MOSFETs M01, M02, and M07-M11, and capacitors C1 and C2. The dynamic self-biasing module includes MOSFETs M07-M11. The latch includes MOSFETs M03-M06. It also includes MOSFET switches S1-S4, with the following connection relationship:

[0006] The drain of MOSFET M01 is connected to node VP, the source to node VB, and the gate to node INP; the drain of M02 is connected to node VQ, the source to node VB, and the gate to node INN; the drain of M03 is connected to node VX, the source to node VP, and the gate to node VY; the drain of M04 is connected to node VY, the source to node VQ, and the gate to node VX; the drain of M05 is connected to node VX, the source to VDD, and the gate to node VY; the drain of M06 is connected to node VY, the source to VDD, and the gate to node VX; the drain of M07 is connected to node VB, the source to the drain of M09, and the gate to node VP; the drain of M08 is connected to node VB, the source to the drain of M10, and the gate to node VQ; the drain of M09 is connected to node VP. The drain of M07 is connected to the source of M07, the source is connected to GND, and the gate is connected to EN; the source of M10 is connected to the source of M08, the source is connected to GND, and the gate is connected to EN; the drain of M11 is connected to node VB, the source is connected to GND, and the gate is connected to EN; the drain of the MOS switch S1 is connected to node VP, the source is connected to VDD, and the gate is connected to EN; the drain of S2 is connected to node VQ, the source is connected to VDD, and the gate is connected to EN; the drain of S3 is connected to node VX, the source is connected to VDD, and the gate is connected to EN; the drain of S4 is connected to node VY, the source is connected to VDD, and the gate is connected to EN; one end of the capacitor C1 is connected to GND, and the other end is connected to node VP; one end of the capacitor C2 is connected to GND, and the other end is connected to node VQ;

[0007] INP and INN are differential input signals, VX and VY are differential output signals; EN is the clock enable signal for the comparator; the threshold voltages of M01 and M02 are the same, the threshold voltages of M03 and M04 are the same, the threshold voltages of M05 and M06 are the same, the threshold voltages of M07 and M08 are the same, and the threshold voltages of M09, M10, and M11 are the same.

[0008] Furthermore, the comparator includes the following four stages in its operating state:

[0009] In the first stage, the comparator's clock enable signal EN is low, which turns on switches S1-S4 and turns off MOSFETs M09-M11, resetting nodes VP, VQ, VX, and VY to VDD. After the comparator reset is complete and the clock enable signal EN is high, the second stage begins.

[0010] In the second stage, the comparator's clock enable signal EN is high, switches S1-S4 are turned off, MOSFETs M09-M11 are turned on, the preamplifier starts to amplify the input signal, and the output common-mode voltage of the preamplifier starts to drop. When the common-mode voltage drops by the threshold voltage of M03 and M04, the third stage begins.

[0011] In the third stage, the preamplifier continues to amplify the input signal, the latch starts to work, and the common-mode voltage of the latch output begins to decrease. When the common-mode voltage decreases by the threshold voltage of M05 and M06, the fourth stage begins.

[0012] In the fourth stage, the preamplifier continues to amplify the input signal. When the voltages of nodes VP and VQ continue to decrease to below the threshold voltages of M07 and M08, M07 and M08 are turned off. At the same time, the output common-mode voltage of the latch continues to decrease, and the latch enters the regeneration state. The positive feedback mechanism of the latch outputs the comparison result based on the result of the preamplifier. That is, when INP > INN, node VY is pulled to VDD and node VX is pulled to GND; when INP < INN, node VX is pulled to VDD and node VY is pulled to GND.

[0013] A dynamic self-biased Elzakker comparator includes a preload amplifier and a latch. The preload amplifier includes a dynamic self-biasing module. The preload amplifier includes: MOSFETs M01'-M09', MOSFET switches S1' and S2', and capacitors C1' and C2'. The dynamic self-biasing module includes: MOSFETs M05'-M09'. The latch includes: MOSFETs M10'-M15', and MOSFET switches S3' and S4', with the following connection relationship:

[0014] The drain of MOSFET M01' is connected to node VP, the source to node VB, and the gate to INP; the drain of M02' is connected to node VQ, the source to node VB, and the gate to INN; the drain of M03' is connected to node VP, the source to VDD, and the gate to EN; the drain of M04' is connected to node VQ, the source to VDD, and the gate to EN; the drain of M05' is connected to node VB, the source to the drain of M07', and the gate to node VP; the drain of M06' is connected to node VB, the source to the drain of M08', and the gate to node VQ; the drain of M07'... The drain of M08' is connected to the source of M06', the source is connected to GND, and the gate is connected to EN; the drain of M09' is connected to node VB, the source is connected to GND, and the gate is connected to EN; the drain of MOS switch S1' is connected to node VP, the source is connected to VDD, and the gate is connected to EN; the drain of switch S2' is connected to node VQ, the source is connected to VDD, and the gate is connected to EN; one end of capacitor C1' is connected to GND, and the other end is connected to node VP; one end of capacitor C2' is connected to GND, and the other end is connected to node VQ.

[0015] The drain of MOSFET M10' is connected to node VX, the source is connected to GND, and the gate is connected to node VY; the drain of M11' is connected to node VY, the source is connected to GND, and the gate is connected to node VX; the drain of M12' is connected to node VX, the source is connected to the drain of M14', and the gate is connected to node VP; the drain of M13' is connected to node VY, the source is connected to the drain of M15', and the gate is connected to node VQ; the drain of M14' is connected to the source of M12', the source is connected to VDD, and the gate is connected to node VY; the drain of M15' is connected to the source of M13', the source is connected to VDD, and the gate is connected to node VX; the drain of MOSFET S3' is connected to node VX, the source is connected to GND, and the gate is connected to ENB; the drain of MOSFET S4' is connected to node VY, the source is connected to GND, and the gate is connected to ENB.

[0016] INP and INN are differential input signals, and VX and VY are differential output signals; EN is the clock enable signal of the comparator, and ENB is the clock reset signal of the latch, which is the inverted signal of EN; the threshold voltages of M01' and M02' are the same, the threshold voltages of M03' and M04' are the same, the threshold voltages of M05' and M06' are the same, the threshold voltages of M07', M08', and M09' are the same, the threshold voltages of M10' and M11' are the same, the threshold voltages of M12' and M13' are the same, and the threshold voltages of M14' and M15' are the same.

[0017] Furthermore, the comparator includes the following four stages in its operating state:

[0018] In the first stage, the clock enable signal EN is low and the clock reset signal ENB is high, which turns on switches S1'-S4' and turns off M07'-M09', resetting nodes VP and VQ to VDD and nodes VX and VY to GND; after the comparator reset is completed and EN is high and ENB is low, the second stage begins.

[0019] In the second stage, the clock enable signal EN is high and ENB is low. S1'-S4' are turned off and M07'-M09' are turned on. The preamplifier starts to amplify the input signal, and the output common-mode voltage of the preamplifier starts to drop. When the common-mode voltage drops by the threshold voltage of M12' and M13', the third stage begins.

[0020] In the third stage, the preamplifier continues to amplify the input signal, the latch starts to work, and the common-mode voltage of the latch output begins to rise. When the common-mode voltage rises by a threshold voltage of M10' and M11', it enters the fourth stage.

[0021] In the fourth stage, the preamplifier continues to amplify the input signal. When the voltages of nodes VP and VQ continue to decrease to below the threshold voltages of M05' and M06', M05' and M06' are turned off. At the same time, the common-mode voltage of the latch continues to rise, and the latch enters the regeneration state. The positive feedback mechanism of the latch outputs a comparison result based on the result of the preamplifier. That is, when INP > INN, node VX is pulled to VDD and node VY is pulled to GND; when INP < INN, node VY is pulled to VDD and node VX is pulled to GND.

[0022] The beneficial effects of this invention are:

[0023] The dynamic self-biased comparator proposed in this invention controls the bias current through the output node of the preamplifier. As the comparator's operating state changes, the bias current also changes. Furthermore, the common-mode voltage changes of nodes VP and VQ differ for different input signal sizes, resulting in different bias currents. Compared to traditional fixed-voltage bias comparators, when both have the same comparison speed for small signal inputs, the dynamic self-biased comparator of this invention can achieve a higher comparison speed for large signal inputs, enabling a higher sampling rate ADC. On the other hand, for ADCs with the same sampling rate, the dynamic comparator has a faster speed for large signal inputs, saving comparison time. This provides more comparison time when the comparator experiences metastability, which helps reduce the ADC's bit error rate. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of the dynamic self-biased SA comparator proposed in Embodiment 1 of the present invention.

[0025] Figure 2 This is a graph showing the voltage changes of nodes VP and VQ over time in Embodiment 1 of the present invention.

[0026] Figure 3 This is a graph showing the change of current flowing through the drains of M07 and M08 over time in Embodiment 1 of the present invention.

[0027] Figure 4 This is a schematic diagram showing the relationship between the common-mode voltages of VP and VQ and the input signal and time in Embodiment 1 of the present invention.

[0028] Figure 5 This is a schematic diagram showing the relationship between the current flowing through node VB and the input signal and time in Embodiment 1 of the present invention.

[0029] Figure 6 This is a schematic diagram showing the relationship between the speed of the dynamic self-biased SA comparator and the traditional SA comparator proposed in Embodiment 1 of the present invention and the input signal.

[0030] Figure 7 This is a circuit diagram of the dynamically self-biased Elzakker comparator proposed in Embodiment 2 of the present invention. Detailed Implementation

[0031] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The objectives and effects of the present invention will become clearer as a result. The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0032] Before providing a further detailed description of the embodiments of the present invention, the nouns and terms involved in the embodiments of the present invention will be explained, and the nouns and terms involved in the embodiments of the present invention shall be subject to the following interpretations.

[0033] (1) MOS: Metal-Oxide-Semiconductor, a semiconductor device that uses an electric field to control the conductive channel. It consists of a metal (gate), an oxide layer (insulating layer), and a semiconductor (substrate), and has three functional terminals: gate (G), drain (D), and source (S). MOS transistors can be divided into two types: NMOS (electron conduction) and PMOS (hole conduction). The core structure of a comparator usually consists of a pair of NMOS or PMOS transistors forming a differential input stage, which converts the input voltage difference into a current difference.

[0034] Vth: Threshold Voltage, the turn-on threshold voltage of the MOSFET.

[0035] (2) VX: Voltage node X. VY: Voltage node Y. VB: Voltage node B.

[0036] INN: Negative Input, the negative voltage input of the comparator. INP: Positive Input, the positive voltage input of the comparator. The comparator is used to compare the magnitudes of INN and INP.

[0037] (4) EN: Enable Signal, clock enable signal. The clock enable signal controls the on / off state of the comparator circuit through a MOSFET (such as a transmission gate) to achieve low power consumption design.

[0038] (5) SA: StrongARM, a comparator structure name. Elzakker: a comparator named after a person. The input equivalent noise of a dynamic comparator is related to the overdrive voltage of the input transistor pair. Generally, the larger the overdrive voltage, the larger the input equivalent noise. For a given input common-mode voltage, the smaller the current flowing through the input transistor pair, the smaller the overdrive voltage, and the closer the operating state of the input transistor pair is to the subthreshold region, the smaller the input equivalent noise of the comparator. The speed of the dynamic comparator is related to the magnitude of the bias current of the preamplifier and the process node of the latch. The speed of the preamplifier is proportional to the bias current, that is, the larger the bias current, the faster the preamplifier, but the worse the noise of the comparator. The working behavior of almost all dynamic comparators can be roughly summarized into three stages: reset, preamplification, and latching. The reset stage resets the comparator to the initial state; the preamplification stage amplifies the input signal to improve the signal-to-noise ratio and prepares for latching; the latching stage generates the comparison result based on the output of the preamplifier.

[0039] Example 1

[0040] Based on the above architecture, this invention proposes a dynamic self-biased SA comparator, such as... Figure 1 As shown, the comparator includes: 11 MOSFETs M01-M11, 4 MOSFET switches S1-S4, and 2 capacitors C1 and C2. The specific connection relationship between the components is as follows:

[0041] For MOSFET M01, the drain is connected to node VP, the source to node VB, and the gate to INP; for M02, the drain is connected to node VQ, the source to node VB, and the gate to INN; for M03, the drain is connected to node VX, the source to node VP, and the gate to node VY; for M04, the drain is connected to node VY, the source to node VQ, and the gate to node VX; for M05, the drain is connected to node VX, the source to VDD, and the gate to node VY; for M06, the drain is connected to node VY, and the source to V... M07's drain is connected to node VX, its source is connected to the drain of M09, and its gate is connected to node VP. M08's drain is connected to node VB, its source is connected to the drain of M10, and its gate is connected to node VQ. M09's drain is connected to the source of M07, its source is connected to GND, and its gate is connected to EN. M10's source is connected to the source of M08, its source is connected to GND, and its gate is connected to EN. M11's drain is connected to node VB, its source is connected to GND, and its gate is connected to EN. MOS switches S1, S2, S3, and S4 are connected to nodes VY, VDD, and EN. One end of capacitor C1 is connected to GND, and the other end is connected to node VP; one end of capacitor C2 is connected to GND, and the other end is connected to node VQ.

[0042] Wherein, EN is the comparator's clock enable signal, used to control the comparator's operating state; INP and INN are differential input signals, VX and VY are differential output signals; GND is ground, and VDD is power supply. M01 and M02 have the same threshold voltage, denoted as Vth1; M03 and M04 have the same threshold voltage, denoted as Vth2; M05 and M06 have the same threshold voltage, denoted as Vth3; M07 and M08 have the same threshold voltage, denoted as Vth4; and M09, M10, and M11 have the same threshold voltage, denoted as Vth5.

[0043] The dynamic self-biased SA comparator consists of a preamplifier and a latch. The dynamic self-biasing module within the preamplifier implements the core dynamic self-biasing function. Specifically, the preamplifier includes MOSFETs M01, M02, M07, M08, M09, M10, and M11, and capacitors C1 and C2. The dynamic self-biasing module includes MOSFETs M07, M08, M09, M10, and M11. The latch includes MOSFETs M03, M04, M05, and M06.

[0044] The comparator proposed in this embodiment is an SA comparator. Compared with the fixed bias voltage of the traditional SA comparator, a portion of the bias voltage of the comparator in this embodiment dynamically changes with the comparator's operating state. The operating state of the dynamically self-biased SA comparator in this embodiment can be divided into the following four stages:

[0045] In the first stage, the comparator's clock enable signal EN is low, turning on switches S1-S4 and resetting nodes VP, VQ, VX, and VY to VDD. Simultaneously, MOSFETs M09-M11 are turned off to prevent short-circuit current from VDD to GND. Once the reset is complete and the clock enable signal EN is high, the second stage begins.

[0046] In the second stage, the comparator's clock enable signal EN is high, switches S1-S4 are turned off, MOSFETs M09-M11 are turned on, the preamplifier starts working, and the preamplifier starts amplifying the input signals INP and INN. The common-mode voltage (denoted as VPQ) of nodes VP and VQ begins to gradually decrease, and the gate voltages of MOSFETs M07 and M08 decrease accordingly, thereby gradually reducing the bias current flowing through M07 and M08. When the common-mode voltage of nodes VP and VQ drops by one Vth2, the third stage begins.

[0047] In the third stage, the comparator's preamplifier continues to amplify the input signal, the voltages at nodes VP and VQ continue to decrease, and the bias current flowing through M07 and M08 further decreases. Since the voltage drop at nodes VP and VQ exceeds Vth2, the gate-source voltages (i.e., gate-source voltages) of M03 and M04 begin to exceed their threshold voltage Vth2, and M03 and M04 begin to operate. The voltages at nodes VX and XY begin to gradually decrease. When the common-mode voltages at nodes VX and VY drop by one Vth3, the latch prepares to enter the regeneration state, i.e., enters the fourth stage.

[0048] In the fourth stage, the comparator's preventative amplifier continues to amplify the input signal. When the voltages at nodes VP and VQ continue to decrease to below Vth4, M07 and M08 are turned off. Meanwhile, the common-mode voltages at nodes VX and VY also continue to decrease. Since the decrease exceeds one Vth3, the latch enters regenerative mode. Its positive feedback mechanism generates a comparison result based on the preamplifier's output. The latch's positive feedback mechanism pulls one node of VX and VY to VDD and the other to GND, depending on the magnitudes of the input signals INP and INN. If INP > INN, then node VY is pulled to VDD and node VX to GND; if INP < INN, then node VX is pulled to VDD and node VY to GND.

[0049] The dynamic self-biasing of this invention is mainly reflected in the second, third, and fourth stages of comparator operation. This is because the output node voltages VP and VQ of the comparator's preamplifier change dynamically, such as... Figure 2 As shown, after the EN signal goes high, the voltages of VP and VQ gradually decrease as the amplifier operates. Therefore, the current flowing through the biased M07 and M08 also changes dynamically. Figure 3 As shown, since the EN signal has just gone high, the current will gradually increase to a peak value and then gradually decrease. Further analysis is performed on the changes in the common-mode voltages of VP and VQ under different input signal values, as follows... Figure 4 As shown, the common-mode voltage change rates of nodes VP and VQ differ under different input signal magnitudes. The larger the input signal, the slower the common-mode voltage of VP and VQ decreases, allowing their bias terminals M07 and M08 to maintain a large voltage bias for a longer period, thus providing a large current for an extended period. Correspondingly, as... Figure 5 As shown, the different rates of change of the common-mode voltage also result in different currents flowing through node VB. Figure 5 It can be seen that, compared with the 1mV input signal, the common-mode voltage of VP and VQ drops more slowly (i.e., the duration is longer) and the voltage is larger, while the current flowing through node VB drops more slowly (i.e., the duration is longer) and the current is larger.

[0050] On the other hand, such as Figure 6 As shown, with an input signal of 0.5mV (small signal), the conventional SA comparator and the dynamically self-biased SA comparator of this embodiment have the same speed. With an input signal of 100mV (large signal), the dynamically self-biased SA comparator of this embodiment is 10ps faster than the conventional SA comparator. Figure 6 As can be seen, compared with the traditional SA comparator, the dynamic self-biased SA comparator proposed in this embodiment has the same comparison speed for small signal inputs, i.e., maintaining the same noise; for large signal inputs, the dynamic self-biased comparator has a faster comparator speed than the traditional SA comparator, which is beneficial to improving the maximum achievable sampling rate of the ADC. For example, for a 7-bit ADC, in the 7 comparisons, the comparator has at most one small signal input, while the remaining 6 are large signal inputs. Compared with the traditional SA comparator, the dynamic self-biased comparator consumes less time in the 6 large signal comparisons, and the comparison completion time is shorter, thus improving the maximum achievable sampling rate of the ADC. If for the same sampling rate ADC, the time saved by the dynamic self-biased comparator can free up more comparison time when the comparator becomes metastable, which is beneficial to reducing the bit error rate of the ADC.

[0051] Example 2

[0052] As another embodiment of the present invention, this embodiment proposes a dynamic self-biased Elzakker comparator, such as... Figure 7 As shown, this comparator also includes a preamplifier and a latch, with the preamplifier also incorporating a dynamic self-biasing module to implement the core dynamic self-biasing function. From a component perspective, the comparator includes: 15 MOSFETs M01'-M15', 4 MOSFET switches S1'-S4', and 2 capacitors C1' and C2'. The specific connections between these components are as follows:

[0053] The preamplifier includes: MOSFETs M01'-M09', MOSFET switches S1' and S2', and capacitors C1' and C2'. The drain of MOSFET M01' is connected to node VP, the source to node VB, and the gate to INP; the drain of M02' is connected to node VQ, the source to node VB, and the gate to INN; the drain of M03' is connected to node VP, the source to VDD, and the gate to EN; the drain of M04' is connected to node VQ, the source to VDD, and the gate to EN; the drain of M05' is connected to node VB, the source to the drain of M07', and the gate to node VP; the drain of M06' is connected to node VB, the source to the drain of M08', and the gate to node VQ; the drain of M07' is connected to the source of M05', the source to GND, and the gate to EN; the drain of M08' is connected to the source of M06', the source to GND, and the gate to EN; the drain of M09' is connected to node VB, the source to GND, and the gate to EN. The drain of MOS switch S1' is connected to node VP, the source is connected to VDD, and the gate is connected to EN; the drain of switch S2' is connected to node VQ, the source is connected to VDD, and the gate is connected to EN. One end of capacitor C1' is connected to GND, and the other end is connected to node VP; one end of capacitor C2' is connected to GND, and the other end is connected to node VQ.

[0054] EN is the clock enable signal for the preamplifier, used to control its operating state. M01' and M02' have the same threshold voltage, denoted as Vth1'; M03' and M04' have the same threshold voltage, denoted as Vth2'; M05' and M06' have the same threshold voltage, denoted as Vth3'; M07', M08', and M09' have the same threshold voltage, denoted as Vth4'.

[0055] The latch includes: MOSFETs M10'-M15', MOSFET switches S3' and S4'. The drain of MOSFET M10' is connected to node VX, the source is connected to GND, and the gate is connected to node VY; the drain of M11' is connected to node VY, the source is connected to GND, and the gate is connected to node VX; the drain of M12' is connected to node VX, the source is connected to the drain of M14', and the gate is connected to node VP of the preamplifier; the drain of M13' is connected to node VY, the source is connected to the drain of M15', and the gate is connected to node VQ of the preamplifier; the drain of M14' is connected to the source of M12', the source is connected to VDD, and the gate is connected to node VY; the drain of M15' is connected to the source of M13', the source is connected to VDD, and the gate is connected to node VX. The drain of MOS switch S3' is connected to node VX, the source is connected to GND, and the gate is connected to ENB; the drain of MOS switch S4' is connected to node VY, the source is connected to GND, and the gate is connected to ENB.

[0056] Here, ENB is the latch's clock reset signal, which is the inverted signal of the preamplifier's clock enable signal EN. Whether the latch enters regeneration mode is controlled by VP and VQ. M10' and M11' have the same threshold voltage, denoted as Vth5'; M12' and M13' have the same threshold voltage, denoted as Vth6'; M14' and M15' have the same threshold voltage, denoted as Vth7'.

[0057] The comparator proposed in this embodiment is an Elzakker comparator. Unlike traditional Elzakker comparators where the preamplifier has a fixed bias voltage, a portion of the bias voltage in this embodiment dynamically changes with the comparator's operating state. The operation of this dynamically self-biased Elzakker comparator can be divided into the following four stages:

[0058] In the first stage, the clock enable signal EN is low and the clock reset signal ENB is high, turning on switches S1'-S4' and resetting nodes VP and VQ to VDD and nodes VX and VY to GND. Simultaneously, switches M07'-M09' are turned off to prevent short-circuit current from VDD to GND. When the reset is complete and EN is high and ENB is low, the second stage begins.

[0059] In the second stage, the clock enable signal EN is high and ENB is low. S1'-S4' are turned off, M07'-M09' are turned on, the preamplifier starts working, and the preamplifier starts to amplify the input signals INP and INN. The common-mode voltages of node voltages VP and VQ begin to gradually decrease, and the gate voltages of M05' and M06' decrease accordingly, thereby gradually reducing the bias current flowing through M05' and M06'. When the voltages of nodes VP and VQ drop by one Vth6', the third stage begins.

[0060] In the third stage, the preamplifier continues to amplify the input signal, the voltages at nodes VP and VQ continue to decrease, and the bias current flowing through M05' and M06' further decreases. Since the voltage drop at nodes VP and VQ exceeds Vth6', the absolute values ​​of the gate-source voltages at M12' and M13' begin to exceed their threshold voltage Vth6', and M12' and M13' begin to operate. The voltages at nodes VX and VY begin to gradually rise. When the voltages at nodes VX and VY rise by Vth5', the latch prepares to enter the regeneration state, i.e., enters the fourth stage.

[0061] In the fourth stage, the preamplifier continues to amplify the input signal. When the voltages at nodes VP and VQ continue to decrease to below Vth3', M05' and M06' are cut off. On the other hand, as the common-mode voltages at nodes VX and VY continue to rise above one Vth5', the latch enters the regeneration stage. Its positive feedback mechanism generates a comparator result based on the preamplifier's result. The latch's positive feedback mechanism pulls one of nodes VX and VY to VDD and the other to GND, depending on the magnitudes of the input signals INP and INN. If INP > INN, node VX is pulled to VDD and node VY is pulled to GND; if INP < INN, node VY is pulled to VDD and node VX is pulled to GND.

[0062] The dynamic self-biasing in this embodiment is mainly reflected in the second, third, and fourth stages of the comparator's operation. Since the voltages of the preamplifier output nodes VP and VQ of the Elzakker comparator change dynamically, the current flowing through its bias M05 and M06 also changes dynamically. Furthermore, for different input signals, the voltage change rates of nodes VP and VQ, as well as the common-mode voltage change of VP and VQ, are different, resulting in different currents flowing through node VB.

[0063] It will be understood by those skilled in the art that the above descriptions are merely preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A dynamic self-biased SA comparator, characterized in that, This includes a preventer and a latch, with the preventer including a dynamic self-biasing module; The preventative device includes: MOSFETs M01, M02, M07-M11, and capacitors C1 and C2; the dynamic self-biasing module includes: MOSFETs M07-M11; the latch includes: MOSFETs M03-M06; and it also includes MOSFET switches S1-S4, whose connection relationship is as follows: The drain of MOSFET M01 is connected to node VP, the source to node VB, and the gate to node INP; the drain of M02 is connected to node VQ, the source to node VB, and the gate to node INN; the drain of M03 is connected to node VX, the source to node VP, and the gate to node VY; the drain of M04 is connected to node VY, the source to node VQ, and the gate to node VX; the drain of M05 is connected to node VX, the source to VDD, and the gate to node VY; the drain of M06 is connected to node VY, the source to VDD, and the gate to node VX; the drain of M07 is connected to node VB, the source to the drain of M09, and the gate to node VP; the drain of M08 is connected to node VB, the source to the drain of M10, and the gate to node VQ; the drain of M09 is connected to node VP. The drain of M07 is connected to the source of M07, the source is connected to GND, and the gate is connected to EN; the source of M10 is connected to the source of M08, the source is connected to GND, and the gate is connected to EN; the drain of M11 is connected to node VB, the source is connected to GND, and the gate is connected to EN; the drain of the MOS switch S1 is connected to node VP, the source is connected to VDD, and the gate is connected to EN; the drain of S2 is connected to node VQ, the source is connected to VDD, and the gate is connected to EN; the drain of S3 is connected to node VX, the source is connected to VDD, and the gate is connected to EN; the drain of S4 is connected to node VY, the source is connected to VDD, and the gate is connected to EN; one end of the capacitor C1 is connected to GND, and the other end is connected to node VP; one end of the capacitor C2 is connected to GND, and the other end is connected to node VQ; INP and INN are differential input signals, VX and VY are differential output signals; EN is the clock enable signal for the comparator; the threshold voltages of M01 and M02 are the same, the threshold voltages of M03 and M04 are the same, the threshold voltages of M05 and M06 are the same, the threshold voltages of M07 and M08 are the same, and the threshold voltages of M09, M10, and M11 are the same.

2. The dynamic self-biased SA comparator according to claim 1, characterized in that, The comparator operates in the following four stages: In the first stage, the comparator's clock enable signal EN is low, which turns on switches S1-S4 and turns off MOSFETs M09-M11, resetting nodes VP, VQ, VX, and VY to VDD. After the comparator reset is complete and the clock enable signal EN is high, the second stage begins. In the second stage, the comparator's clock enable signal EN is high, switches S1-S4 are turned off, MOSFETs M09-M11 are turned on, the preamplifier starts to amplify the input signal, and the output common-mode voltage of the preamplifier starts to drop. When the common-mode voltage drops by the threshold voltage of M03 and M04, the third stage begins. In the third stage, the preamplifier continues to amplify the input signal, the latch starts to work, and the common-mode voltage of the latch output begins to decrease. When the common-mode voltage decreases by the threshold voltage of M05 and M06, the fourth stage begins. In the fourth stage, the preamplifier continues to amplify the input signal. When the voltages of nodes VP and VQ continue to decrease to below the threshold voltages of M07 and M08, M07 and M08 are turned off. At the same time, the output common-mode voltage of the latch continues to decrease, and the latch enters the regeneration state. The positive feedback mechanism of the latch outputs the comparison result based on the result of the preamplifier. That is, when INP > INN, node VY is pulled to VDD and node VX is pulled to GND; when INP < INN, node VX is pulled to VDD and node VY is pulled to GND.

3. A dynamic self-biased Elzakker comparator, characterized in that, The system includes a protection device and a latch. The protection device includes a dynamic self-biasing module. The protection device includes: MOSFETs M01'-M09', MOSFET switches S1' and S2', and capacitors C1' and C2'. The dynamic self-biasing module includes: MOSFETs M05'-M09'. The latch includes: MOSFETs M10'-M15', and MOSFET switches S3' and S4', with the following connection relationship: The drain of MOSFET M01' is connected to node VP, the source to node VB, and the gate to INP; the drain of M02' is connected to node VQ, the source to node VB, and the gate to INN; the drain of M03' is connected to node VP, the source to VDD, and the gate to EN; the drain of M04' is connected to node VQ, the source to VDD, and the gate to EN; the drain of M05' is connected to node VB, the source to the drain of M07', and the gate to node VP; the drain of M06' is connected to node VB, the source to the drain of M08', and the gate to node VQ; the drain of M07'... The drain of M08' is connected to the source of M06', the source is connected to GND, and the gate is connected to EN; the drain of M09' is connected to node VB, the source is connected to GND, and the gate is connected to EN; the drain of MOS switch S1' is connected to node VP, the source is connected to VDD, and the gate is connected to EN; the drain of switch S2' is connected to node VQ, the source is connected to VDD, and the gate is connected to EN; one end of capacitor C1' is connected to GND, and the other end is connected to node VP; one end of capacitor C2' is connected to GND, and the other end is connected to node VQ. The drain of MOSFET M10' is connected to node VX, the source is connected to GND, and the gate is connected to node VY; the drain of M11' is connected to node VY, the source is connected to GND, and the gate is connected to node VX; the drain of M12' is connected to node VX, the source is connected to the drain of M14', and the gate is connected to node VP; the drain of M13' is connected to node VY, the source is connected to the drain of M15', and the gate is connected to node VQ; the drain of M14' is connected to the source of M12', the source is connected to VDD, and the gate is connected to node VY; the drain of M15' is connected to the source of M13', the source is connected to VDD, and the gate is connected to node VX; the drain of MOSFET S3' is connected to node VX, the source is connected to GND, and the gate is connected to ENB; the drain of MOSFET S4' is connected to node VY, the source is connected to GND, and the gate is connected to ENB. INP and INN are differential input signals, and VX and VY are differential output signals; EN is the clock enable signal of the comparator, and ENB is the clock reset signal of the latch, which is the inverted signal of EN; the threshold voltages of M01' and M02' are the same, the threshold voltages of M03' and M04' are the same, the threshold voltages of M05' and M06' are the same, the threshold voltages of M07', M08', and M09' are the same, the threshold voltages of M10' and M11' are the same, the threshold voltages of M12' and M13' are the same, and the threshold voltages of M14' and M15' are the same.

4. The dynamic self-biased Elzakker comparator according to claim 3, characterized in that, The comparator operates in the following four stages: In the first stage, the clock enable signal EN is low and the clock reset signal ENB is high, which turns on switches S1'-S4' and turns off M07'-M09', resetting nodes VP and VQ to VDD and nodes VX and VY to GND; after the comparator reset is completed and EN is high and ENB is low, the second stage begins. In the second stage, the clock enable signal EN is high and ENB is low. S1'-S4' are turned off and M07'-M09' are turned on. The preamplifier starts to amplify the input signal, and the output common-mode voltage of the preamplifier starts to drop. When the common-mode voltage drops by the threshold voltage of M12' and M13', the third stage begins. In the third stage, the preamplifier continues to amplify the input signal, the latch starts to work, and the common-mode voltage of the latch output begins to rise. When the common-mode voltage rises by a threshold voltage of M10' and M11', it enters the fourth stage. In the fourth stage, the preamplifier continues to amplify the input signal. When the voltages of nodes VP and VQ continue to decrease to below the threshold voltages of M05' and M06', M05' and M06' are turned off. At the same time, the common-mode voltage of the latch continues to rise, and the latch enters the regeneration state. The positive feedback mechanism of the latch outputs a comparison result based on the result of the preamplifier. That is, when INP > INN, node VX is pulled to VDD and node VY is pulled to GND; when INP < INN, node VY is pulled to VDD and node VX is pulled to GND.

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