System and method for realizing wireless frequency synchronization of controllable clock signals based on hardware triggering and stacking of quartz crystal wafers

Abstract

The invention discloses a system and a method for realizing wireless frequency synchronization of controllable clock signals based on hardware triggering and stacking of quartz crystal wafers. The system comprises an alternating voltage generator, a transmitting voltage transformer, a receiving voltage transformer, a voltage-frequency converter, an FPGA (Field Programmable Gate Array) and a quartz crystal wafer group. A system transmitting module generates corresponding alternating voltage through an alternating voltage generator according to transmitting frequency, mutual inductance alternating voltage is obtained through a mutual inductance receiving module, then the mutual inductance alternating voltage is converted into digital signals through a voltage-frequency converter and transmitted to an FPGA, an FPGA chip calculates and selects a quartz crystal wafer combination through an algorithm, oscillation starting voltage is given for oscillation starting, and the system transmitting module transmits the digital signals to a receiving module. Therefore, a controllable and accurate clock signal is obtained. According to the method, the problems that communication is asynchronous due to the fact that the crystal oscillator frequency of the receiving end in traditional wireless communication is affected by temperature, and wireless communication synchronization is affected by the environment and the encoding and decoding speed are solved. The parallel data processing capability of the FPGA is fully utilized, the oscillation starting quartz crystal wafer combination is rapidly selected, and the purpose of controlling the crystal oscillation frequency clock source is achieved.

Description

Technical Field

[0001] This invention belongs to the field of wireless frequency synchronization control, and in particular relates to a system and method for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips. Background Technology

[0002] High-precision wireless synchronization technology is widely used in aerospace, precision navigation, wireless communication, power electronics, and financial transactions. In these fields, even minute clock errors can have catastrophic consequences. Traditional wireless synchronization methods involve the transmitter encoding the signal and then transmitting electromagnetic waves via an antenna; the receiver receives the waves, decodes them, and obtains the synchronization information. However, this method has several problems in practical applications and is easily affected by environmental factors, such as electromagnetic wave reflection from obstacles and the impact of different weather conditions on propagation speed, leading to asynchrony between transmission and reception. Furthermore, the encoding and decoding speed also affects the wireless synchronization speed.

[0003] In traditional distributed wireless communication systems, crystal oscillators are often used as frequency standards. However, crystal oscillators have some drawbacks; they are easily affected by factors such as temperature and aging over long periods of operation, leading to a decrease in the actual crystal frequency and consequently, the accumulation of wireless communication errors. To address this problem in distributed systems, traditional solutions include using high-precision atomic clocks or temperature-controlled crystal oscillators as the frequency source. However, these methods not only fail to completely eliminate accumulated errors but are also costly and difficult to truly achieve wireless frequency synchronization.

[0004] Based on the above situation, this invention proposes a system and method for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips. This system and method greatly reduces the impact of environment and encoding / decoding speed on synchronization during wireless transmission of distributed systems through the mutual inductance principle. At the same time, by stacking crystal chips to control the thickness of the crystal chips, a controllable crystal frequency can be achieved, effectively ensuring that the crystal frequency is not affected by temperature and aging. Summary of the Invention

[0005] To ensure frequency synchronization during the wireless synchronization process of a distributed system, this invention provides a system and method for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips.

[0006] The technical solution of this invention is:

[0007] This invention provides a system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips, comprising: a transmitting module and a receiving module.

[0008] The transmitting module includes an alternating voltage generator and a transmitting voltage transformer, and the alternating voltage generator and the transmitting voltage transformer are connected.

[0009] The receiving module includes a receiving voltage transformer, a voltage-to-frequency converter, an FPGA, and a quartz crystal chip group. The receiving voltage transformer is connected to both the voltage-to-frequency converter and the FPGA. Both the voltage-to-frequency converter and the quartz crystal chip group are connected to the FPGA. The quartz crystal chip group is used to provide a clock frequency for the FPGA and the voltage-to-frequency converter. The quartz crystal chip group includes multiple quartz crystal chips of different thicknesses. The FPGA selects the combination of quartz crystal chips to be oscillated as needed.

[0010] Preferably, the quartz crystal sheets are in horizontal contact with each other and have the same contact area.

[0011] Preferably, the quartz crystal sheets are arranged and bonded in order of thickness.

[0012] Preferably, the receiving voltage transformer provides an oscillation voltage for the selected quartz crystal assembly.

[0013] Preferably, an electrode sheet is sandwiched in the gap between the quartz crystal sheets of different thicknesses, and the electrode sheet is connected to the FPGA programmable input / output (IO) pin.

[0014] Preferably, the voltage-to-frequency converter is also connected to the FPGA programmable input / output (IO) pins.

[0015] Preferably, the FPGA includes a voltage transformer control module, a voltage-to-frequency converter control module, a quartz crystal chip group control module, a frequency multiplier module, and a data buffer read / write module.

[0016] The receiving voltage transformer control module is used to adjust the starting voltage and drive the selected quartz crystal wafer combination to work.

[0017] The voltage-to-frequency converter control module is used to generate the clock frequency required by the voltage-to-frequency converter and drive the voltage-to-frequency converter to work.

[0018] The quartz crystal assembly control module is used to select the quartz crystal assembly and apply an oscillation voltage to the corresponding pin to drive the quartz crystal assembly to oscillate.

[0019] The frequency multiplier module is used to multiply the initial frequency generated by the oscillation of the quartz crystal wafer combination to obtain the target frequency;

[0020] The data cache read / write module utilizes embedded resources within the FPGA to generate a data cache area for storing and reading resonant frequency table data of quartz crystal wafer combinations of different thicknesses.

[0021] This invention also provides a method for achieving wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips. The system for achieving wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips includes the following steps:

[0022] S1, label each quartz crystal electrode in the quartz crystal sheet group with a serial number to obtain the electrode sheet serial number;

[0023] S2, Construct a resonant frequency thickness table for combinations of quartz crystal sheets of different thicknesses;

[0024] S3. Through parallel lookup using FPGA, find the electrode sheet number corresponding to the common resonant frequency of the target crystal oscillator in the resonant frequency thickness table.

[0025] S4, the FPGA applies an oscillation voltage to the quartz crystal combination between the electrode sheets corresponding to the electrode sheet number to obtain the initial frequency;

[0026] S5, the FPGA uses a frequency multiplier module to multiply the initial frequency to obtain the target frequency.

[0027] Compared with the prior art, the present invention has the following obvious features and significant advantages:

[0028] 1. This invention, by adding voltage transformers at both the transmitting and receiving ends, converts the transmitting frequency into an alternating voltage of the same frequency. With hardware contact between the transmitting and receiving ends, a receiving voltage of the same frequency is obtained at the receiving end through mutual inductance. This effectively solves the problem of frequency synchronization signals in wireless communication being easily affected by the environment and encoding / decoding speed, ensuring the synchronization of communication frequencies. Simultaneously, it gives the system good resettableness and sustainability.

[0029] 2. This invention employs a stacked arrangement of quartz crystal wafers and controls the overall crystal oscillator frequency by adjusting the stack thickness. When determining the quartz crystal wafer combination, the parallel data processing capability of the FPGA is utilized to treat the large-scale quartz crystal wafer combination as a data table for FPGA processing, significantly improving the selection speed. This not only avoids the frequency reduction problem caused by temperature changes and aging over long-term use in quartz crystal oscillators but also effectively ensures the stability of the single-ended crystal oscillator frequency in wireless communication. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a system structure for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips, according to Embodiment 1 of the present invention.

[0031] Figure 2This is a diagram of the internal structure of the FPGA in Embodiment 2 of the present invention;

[0032] Figure 3 This is a diagram showing the stacking arrangement of the quartz crystal sheet assembly in Embodiment 3 of the present invention;

[0033] Figure 4 This is a flowchart of the synchronization method in Embodiment 4 of the present invention. Detailed Implementation

[0034] This invention proposes a system and method for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips. It aims to solve the problems of asynchronous communication caused by temperature-induced fluctuations in the receiver's crystal oscillator frequency in traditional wireless communication, and the impact of environmental factors and encoding / decoding speeds on wireless communication synchronization. This invention fully utilizes the parallel data processing capabilities of a Field-Programmable Gate Array (FPGA) to quickly select the combination of oscillating quartz crystal chips, achieving a controllable crystal oscillator frequency clock source. Through the principle of mutual inductance, the impact of environmental factors and encoding / decoding speeds on synchronization during wireless transmission in distributed systems is reduced. Simultaneously, stacked crystal chips are used to control the thickness of the crystal chips, achieving a controllable crystal oscillator frequency and ensuring that the crystal oscillator frequency is unaffected by temperature and aging.

[0035] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0036] Example 1:

[0037] Figure 1 This is a schematic diagram of a system structure for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips, as described in Embodiment 1 of the present invention.

[0038] like Figure 1 As shown, this embodiment 1 provides a system 100 for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips, including: a transmitting module 10 and a receiving module 20.

[0039] The transmitting module 10 includes an alternating voltage generator 11 and a transmitting voltage transformer 12, which are connected together.

[0040] The receiving module 20 includes a receiving voltage transformer 21, a voltage-to-frequency converter 22, an FPGA 23, and a quartz crystal chip group 24. The receiving voltage transformer is connected to both the voltage-to-frequency converter and the FPGA. The voltage-to-frequency converter 22 and the quartz crystal chip group 24 are both connected to the FPGA 23. The quartz crystal chip group 24 is used to provide a clock frequency for the FPGA 23 and the voltage-to-frequency converter 22. The quartz crystal chip group 24 includes multiple quartz crystal chips of different thicknesses. The FPGA 23 selects the combination of quartz crystal chips to be oscillated as needed.

[0041] This embodiment uses an FPGA, which fully utilizes the FPGA's parallel data processing capabilities and precise timing control capabilities to improve data processing speed.

[0042] In this embodiment, the main principle of the system 100 for achieving controllable clock signal wireless frequency synchronization based on hardware triggering and stacked quartz crystal chips is as follows:

[0043] According to the transmission frequency, the transmitting module 10 generates a corresponding alternating voltage through the alternating voltage generator 11. After the alternating voltage is mutually induced by the transmitting voltage transformer 12 and the receiving voltage transformer 21, the corresponding mutual inductance alternating voltage is obtained in the receiving module 20. The mutual inductance alternating voltage is then converted into a digital signal by the voltage-to-frequency converter 22 and transmitted to the FPGA chip. The FPGA chip uses an algorithm to calculate and select the combination of quartz crystal chips, and applies an oscillation voltage to make it oscillate, thereby obtaining a controllable and precise clock signal.

[0044] Example 2:

[0045] This embodiment 2 is basically the same as embodiment 1 above, except that:

[0046] In this embodiment, the quartz crystal sheets of different thicknesses in the quartz crystal sheet group 24 are bonded together in the horizontal direction with the same bonding contact area.

[0047] Furthermore, the individual quartz crystal sheets are arranged and bonded together in order of thickness.

[0048] In this embodiment, the receiving voltage transformer 21 provides the starting voltage for the selected quartz crystal wafer combination.

[0049] In this embodiment, electrode plates are sandwiched in the gaps between quartz crystal sheets of different thicknesses. These electrode plates are connected to the FPGA programmable input / output (IO) pins, and the voltage-to-frequency converter 22 is also connected to the FPGA programmable input / output (IO) pins.

[0050] Figure 2 This is a diagram of the internal structure of the FPGA in Embodiment 2 of the present invention.

[0051] like Figure 2 As shown, the FPGA includes the following modules: a voltage transformer control module, a voltage-to-frequency converter control module, a quartz crystal chip group control module, a frequency multiplier module, and a data cache read / write module.

[0052] The receiving voltage transformer control module is used to adjust the starting voltage and drive the selected quartz crystal wafer combination to work;

[0053] The voltage-to-frequency converter control module is used to generate the clock frequency required by the voltage-to-frequency converter 22 and drive the voltage-to-frequency converter 22 to work.

[0054] The quartz crystal assembly control module is used to select the quartz crystal assembly and apply an oscillation voltage to the corresponding pin to drive the quartz crystal assembly to oscillate.

[0055] The frequency multiplier module is used to multiply the initial frequency generated by the combined oscillation of the frequency multiplier quartz crystal chips to obtain the target frequency;

[0056] The data cache read / write module utilizes embedded resources within the FPGA to generate a data cache area for storing and reading resonant frequency table data of quartz crystal wafers of different thicknesses.

[0057] In this embodiment, by incorporating a receiving voltage transformer control module, a voltage-to-frequency converter control module, a data buffer read / write module, a quartz crystal chip group control module, and a frequency multiplier module within the FPGA, the received alternating voltage of the mutual inductance is acquired and processed. Utilizing the FPGA's precise timing control and parallel data processing capabilities, rapid selection of the quartz crystal chip combination is achieved. Furthermore, the data buffer read / write module stores and retrieves resonant frequency table data for quartz crystal chip combinations of different thicknesses, fully utilizing the FPGA's internal resources and saving costs. The frequency multiplier module proportionally reduces the received alternating voltage of the mutual inductance to the oscillation voltage of the selected quartz crystal chip combination, utilizing the piezoelectric resonance effect to achieve crystal oscillation, thereby achieving frequency synchronization between the wireless transceiver.

[0058] Example 3:

[0059] This Example 3 is basically the same as Example 2 above, except that:

[0060] In this embodiment, the quartz crystal sheets are stacked in sequence according to their thickness, with electrode sheets of the same thickness sandwiched in between. Electrode sheets are also attached to both ends of the stacked quartz crystal sheet assembly.

[0061] Figure 3 This is a diagram showing the stacking arrangement of the quartz crystal sheets in Embodiment 3 of the present invention.

[0062] like Figure 3As shown, the main principle of the system 100 in this embodiment is as follows:

[0063] Various control modules for controlling peripherals are set up inside the FPGA. The resonant frequency table data of quartz crystal chip combinations with different thicknesses is stored in the data cache read / write module inside the FPGA. When the FPGA is powered on, it is mutually inducted with the receiving voltage transformer 21 through the transmitting voltage transformer 12. The FPGA reduces the mutual inductance alternating voltage to the starting voltage through the internal receiving voltage transformer control module and frequency multiplier module. The alternating voltage from the receiving voltage transformer 21 is converted into a frequency through the voltage-to-frequency converter control module. Based on this frequency, the FPGA searches in parallel for the resonant frequency table data of quartz crystal chip combinations with different thicknesses stored in the internal data cache read / write module to find the quartz crystal chip combination with the common frequency of the mutual inductance alternating voltage. The corresponding quartz crystal chip combination is selected by the quartz crystal chip group control module, and the starting voltage is applied to the electrode plates at both ends of the combination to realize the piezoelectric resonance of the quartz crystal chip group 24, drive the oscillation of the quartz crystal chip group 24, and then multiply the frequency by the frequency multiplier module to obtain the desired frequency.

[0064] Example 4:

[0065] Figure 4 This is a flowchart of the synchronization method in Embodiment 4 of the present invention.

[0066] like Figure 4 As shown, this embodiment provides a method for achieving wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips. Using the systems for achieving wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips described in Embodiments 2 and 3 above, the method includes the following steps:

[0067] S1, label each quartz crystal electrode in the quartz crystal sheet group 24 with a serial number to obtain the electrode sheet serial number, i.e., ep i , i∈[1,n+1].

[0068] S2, Construct a resonant frequency thickness table for combinations of quartz crystal sheets of different thicknesses, where each element in the table is f. ij This represents the resonant frequency of a quartz crystal composed of two quartz crystal sheets of different thicknesses, electrode number i and electrode number j, in relation to the total thickness. ij =(f ij d ij ), where i∈[1, b], j∈[2, n+1].

[0069] In S2, the resonant frequencies of combinations of quartz crystal sheets of different thicknesses and the rate of change of the resonant frequency of a single crystal sheet satisfy the Sauerbrey equation:

[0070] Δf=KF 2 ΔMA

[0071] Where Δf represents the rate of change of the resonant frequency of the obtained combinations of quartz crystal sheets of different thicknesses from the inherent resonant frequency of the reference quartz crystal sheet; K = -2126 × 10 -6 F represents the inherent resonant frequency of the reference crystal, ΔM represents the rate of change of the total mass of the assembly and the mass of the reference crystal in the assembly, and A represents the bonding area of ​​quartz crystals of various thicknesses.

[0072] In the Sauerbrey equation, the reference crystal is the quartz crystal with the smallest thickness in the selected quartz crystal combination, i.e.:

[0073] d base =min{d v}, v∈[i,j]

[0074] Where d base d represents the thickness of the reference quartz crystal sheet. v This indicates the thickness of any quartz crystal in the quartz crystal assembly.

[0075] In the Sauerbrey equation, Δf and ΔM can be expressed as:

[0076]

[0077] Where f total The resonant frequency of the quartz crystal assembly is represented by F, where F represents the inherent resonant frequency of the reference quartz crystal, and M represents the resonant frequency of the reference quartz crystal. total M represents the total mass of the quartz crystal assembly. base Indicates the quality of the reference quartz crystal.

[0078] In this embodiment, the bonding area of ​​the combination of quartz crystal sheets of different thicknesses obtained in S2 is a constant, that is:

[0079] A = const

[0080] Where A represents the bonding area of ​​quartz crystal sheets of different thicknesses.

[0081] Furthermore, the resonant frequencies of the combinations of quartz crystal sheets of different thicknesses obtained by s2 satisfy the same resonant frequency as the thickness of a single crystal sheet:

[0082] f ij =F + Δf.

[0083] S3, through parallel lookup using FPGA, find the electrode sheet number i,j corresponding to the common resonant frequency of the target crystal oscillator in the resonant frequency thickness table.

[0084] S4, the FPGA applies an oscillation voltage to the quartz crystal combination between the electrode plates corresponding to the electrode plate number to obtain the initial frequency.

[0085] S5, the FPGA obtains the target frequency through the frequency multiplier module and the initial frequency.

[0086] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A system for wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips, characterized in that, include: Sending module and receiving module, The transmitting module includes an alternating voltage generator and a transmitting voltage transformer, and the alternating voltage generator and the transmitting voltage transformer are connected. The receiving module includes a receiving voltage transformer, a voltage-to-frequency converter, an FPGA, and a quartz crystal chip group. The receiving voltage transformer is connected to both the voltage-to-frequency converter and the FPGA. Both the voltage-to-frequency converter and the quartz crystal chip group are connected to the FPGA. The quartz crystal chip group is used to provide a clock frequency for the FPGA and the voltage-to-frequency converter. The quartz crystal chip group includes multiple quartz crystal chips of different thicknesses. The FPGA selects the combination of quartz crystal chips to be oscillated as needed.

2. The system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips according to claim 1, characterized in that: The quartz crystal sheets are horizontally aligned, with each surface having the same contact area.

3. The system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips according to claim 2, characterized in that: The quartz crystal sheets are arranged and bonded together in order of thickness.

4. The system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips according to claim 3, characterized in that: The receiving voltage transformer provides the starting voltage for the selected quartz crystal wafer combination.

5. The system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips according to claim 4, characterized in that: Electrode plates are sandwiched in the gaps between the quartz crystal sheets of different thicknesses, and the electrode plates are connected to the programmable input / output (IO) pins of the FPGA.

6. The system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips according to claim 5, characterized in that: The voltage-to-frequency converter is also connected to the FPGA's programmable input / output (IO) pins.

7. The system for wireless frequency synchronization of controllable clock signals based on hardware triggering and stacked quartz crystal chips according to claim 6, characterized in that: The FPGA includes a receiving voltage transformer control module, a voltage-to-frequency converter control module, a quartz crystal chip group control module, a frequency multiplier module, and a data buffer read / write module. The receiving voltage transformer control module is used to adjust the starting voltage and drive the selected quartz crystal wafer combination to work. The voltage-to-frequency converter control module is used to generate the clock frequency required by the voltage-to-frequency converter and drive the voltage-to-frequency converter to work. The quartz crystal assembly control module is used to select the quartz crystal assembly and apply an oscillation voltage to the corresponding pin to drive the quartz crystal assembly to oscillate. The frequency multiplier module is used to multiply the initial frequency generated by the oscillation of the quartz crystal wafer combination to obtain the target frequency; The data cache read / write module utilizes embedded resources within the FPGA to generate a data cache area for storing and reading resonant frequency table data of quartz crystal wafer combinations of different thicknesses.

8. A method for wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips, using the system for wireless frequency synchronization of a controllable clock signal based on hardware triggering and stacked quartz crystal chips as described in claims 5-7, characterized in that... include: S1, label each quartz crystal electrode in the quartz crystal sheet group with a serial number to obtain the electrode sheet serial number; S2, Construct a resonant frequency thickness table for combinations of quartz crystal sheets of different thicknesses; S3. Through parallel lookup using FPGA, find the electrode sheet number corresponding to the common resonant frequency of the target crystal oscillator in the resonant frequency thickness table. S4, the FPGA applies an oscillation voltage to the quartz crystal combination between the electrode sheets corresponding to the electrode sheet number to obtain the initial frequency; S5, the FPGA uses a frequency multiplier module to multiply the initial frequency to obtain the target frequency.

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