Calibration method of memory and storage device

Abstract

The invention discloses a memory calibration method and a memory device, and relates to the technical field of storage, systematic calibration is carried out on reference voltage, receiving delay and sending delay of a first signal and receiving delay and sending delay of each data line by staged steps, the influence caused by factors such as individual difference of memory hardware can be effectively eliminated, and the memory reliability is improved. Accurate sampling and identification of the data in the transmission process are ensured, the data read-write error rate is greatly reduced, and the data transmission reliability is improved. Meanwhile, by expanding the reference voltage range and testing a plurality of preset delay values, the reference voltage most suitable for working of the current memory, the target receiving delay and sending delay of the first signal and the target receiving delay and sending delay of each data line can be screened out, and the storage performance of the memory is effectively improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a calibration method and storage device for a memory. Background Technology

[0002] With the rapid development of information technology, memory, as a core component for data storage and processing, plays a crucial role in the operation of the entire electronic system due to its performance and reliability. In related technologies, memory operates using preset, fixed operating parameters.

[0003] However, fixed operating parameters are difficult to cover different hardware configurations, making the operating status of different batches of memory unstable, resulting in poor storage performance of some memory. Summary of the Invention

[0004] This application provides a calibration method and storage device for a memory, so as to at least solve the problem of poor memory storage performance in related technologies.

[0005] This application provides a method for calibrating a memory, including:

[0006] The initial reference voltage and the first receive delay of each data line in the memory are determined. The first receive delay is determined based on the second receive delay of the first signal, which is used to synchronize data transmission.

[0007] The initial reference voltage is extended to obtain multiple first reference voltages. Based on the multiple first reference voltages, multiple preset reception delays of the first signal, and the first reception delay of each data line, the second reference voltage for data reading from the memory and the target reception delay of the first signal are determined.

[0008] Based on the second reference voltage and the target reception delay of the first signal, the first reception delay of each data line is calibrated to obtain the target reception delay of each data line.

[0009] Based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, the transmission delay of the first signal and the transmission delay of each data line are calibrated.

[0010] This application also provides a memory calibration apparatus, comprising:

[0011] The determination module is used to determine the initial reference voltage and the first reception delay of each data line in the memory. The first reception delay is determined based on the second reception delay of the first signal, which is used to synchronize data transmission.

[0012] The processing module is used to perform extended processing on the initial reference voltage to obtain multiple first reference voltages, and based on the multiple first reference voltages, multiple preset receiving delays of the first signal and the first receiving delay of each data line, determine the second reference voltage for data reading from the memory and the target receiving delay of the first signal.

[0013] The calibration module is used to calibrate the first reception delay of each data line based on the second reference voltage and the target reception delay of the first signal, so as to obtain the target reception delay of each data line.

[0014] The calibration module is also used to calibrate the transmission delay of the first signal and the transmission delay of each data line based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the calibration method of any of the above-described memory when executing the computer program.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described memory calibration methods.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described memory calibration methods.

[0018] The calibration method and storage device provided in this application systematically calibrate the reference voltage, the receiving and transmitting delays of the first signal, and the receiving and transmitting delays of each data line through a phased process. This effectively eliminates the influence of factors such as individual differences in memory hardware, ensuring that data is accurately sampled and identified during transmission, significantly reducing data read / write error rates, and improving data transmission reliability. Simultaneously, by expanding the reference voltage range and testing multiple preset delay values, the most suitable reference voltage, target receiving and transmitting delays of the first signal, and target receiving and transmitting delays of each data line can be selected, effectively improving the storage performance of the memory. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1A flowchart illustrating the memory calibration method provided in this application embodiment. Figure 1 ;

[0021] Figure 2 A flowchart illustrating the memory calibration method provided in this application embodiment. Figure 2 ;

[0022] Figure 3 A schematic diagram illustrating the second reference voltage and the target reception delay of the first signal provided in an embodiment of this application;

[0023] Figure 4 A schematic diagram illustrating the target transmission delay of the fourth reference voltage and the first signal provided in an embodiment of this application;

[0024] Figure 5 A schematic diagram of the structure of a memory calibration device provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0027] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] Storage devices include memory and processor. The processor controls the memory to perform read and write operations based on operating parameters (such as drive strength, on-chip termination resistance, reference voltage, receive delay, and transmit delay). Therefore, appropriate operating parameters can effectively improve the storage performance of the memory.

[0029] In related technologies, storage device manufacturers typically select a small sample from a large number of finished storage devices for testing and calibration to obtain fixed operating parameters. These fixed operating parameters are then written into the storage device. Each time the storage device is powered on, the processor calls these fixed operating parameters to control the memory to perform read and write operations.

[0030] However, due to the limited number of test samples and the hardware differences in processors and memory between different batches of storage devices, the fixed operating parameters cannot be applied to each storage device, resulting in poor storage performance of some storage devices.

[0031] To address the aforementioned technical issues, the following technical concept is proposed: Since fixed operating parameters do not take into account individual differences in memory, calibration can be performed on the memory device itself, based on the fixed operating parameters, when the memory device is powered on, to obtain operating parameters more suitable for the memory, thereby improving the memory's storage performance.

[0032] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Figure 1 A flowchart illustrating the memory calibration method provided in this application embodiment. Figure 1 Embodiments of this application provide a memory calibration method applicable to any storage device. For example... Figure 1 As shown, the method includes:

[0034] In one possible implementation, prior to S101, write data tests and read data tests are performed on pre-stored test data in the memory to obtain the number of bit errors. The read / write rate of the memory is less than a first threshold. If the number of bit errors is less than or equal to a second threshold, the memory hardware is determined to be normal. If the number of bit errors is greater than the second threshold, the memory hardware is determined to be abnormal, and the calibration of the memory is terminated.

[0035] In low-speed scenarios where the memory read / write rate is less than the first threshold, by performing write and read tests on pre-stored test data and counting the number of bit errors, we can not only eliminate interference from non-hardware-related problems in the low-speed environment and accurately determine whether the memory hardware is normal, but also terminate invalid calibration in advance in case of hardware abnormality to save system resources and improve process efficiency. We can also avoid subsequent data risks caused by hardware failures from the source. At the same time, the low complexity of low-speed testing also reduces the cost of testing and calibration, providing an efficient, reliable and economical solution for hardware "entry screening" before memory calibration.

[0036] S101. Determine the initial reference voltage and the first reception delay of each data line in the memory. The first reception delay is determined based on the second reception delay of the first signal, which is used to synchronize data transmission.

[0037] The reference voltage serves as a reference voltage to determine the high or low level state of the data signal, and is used to determine whether the signal transmitted in the Q channel is a logic "0" or a logic "1". Data lines indicate the physical lines in the memory used for data transmission; each data line corresponds to an independent data transmission channel. The first receive delay indicates the delay parameter when the data line receives data, ensuring that data is sampled within the correct time window. The first signal indicates the clock signal or control signal for synchronous data transmission, ensuring the timing consistency of data transmission and reception. The second receive delay indicates the receive delay of the first signal itself and serves as a reference for determining the data line receive delay.

[0038] Specifically, the initial reference voltage is usually determined based on fixed operating parameters. Since the first signal is the synchronization reference for data transmission, the second reception delay directly affects the reception timing of the data lines. Therefore, it is necessary to first obtain the second reception delay of the first signal, and then use this as a reference to calculate or measure the first reception delay of each data line to ensure that the initial reception timing of the data lines matches the synchronization signal.

[0039] For example, the initial reference voltage might be set to 0.5V (assuming a power supply voltage of 1V, using the midpoint as a reference). The first signal is the Data Strobe (DQS), whose second receive delay is measured to be 5ns. For the memory's eight data lines (DQ0-DQ7, where DQ indicates the data line), the first receive delay of each data line needs to be adjusted based on the 5ns delay of the DQS. For example, the first receive delay of DQ0 might be ultimately determined to be 5.2ns, and that of DQ1 to be 4.9ns, etc., to initially ensure synchronization between the data and the DQS signal.

[0040] In one possible implementation, the preset receiving delays are iterated, and the memory is trained by reading the data bus. The median value between the maximum and minimum receiving delays of the successful data bus training is determined as the second receiving delay of the first signal, and the read / write rate of the memory is greater than or equal to a first threshold. Based on the second receiving delay of the first signal, the memory is trained by reading the data bus, and the successful receiving delay is determined as the first receiving delay of each data line in the memory.

[0041] S102. The initial reference voltage is extended to obtain multiple first reference voltages. Based on the multiple first reference voltages, multiple preset receiving delays of the first signal, and the first receiving delay of each data line, the second reference voltage for data reading from the memory and the target receiving delay of the first signal are determined.

[0042] The extended processing is used to adjust the initial reference voltage vertically, generating a series of different voltage values ​​to cover possible voltage fluctuations. The first reference voltage indicates the multiple reference voltages obtained after the extended processing, used to test memory performance under different voltages. The preset receive delay indicates a series of delay values ​​pre-set for the first signal, used to test synchronization effects under different timing sequences. The second reference voltage indicates the reference voltage for data reading, determined after testing and verification, exhibiting high stability and compatibility. The target receive delay of the first signal indicates the optimal receive delay of the first signal determined after testing, ensuring the timing accuracy of the synchronization signal.

[0043] Specifically, the initial reference voltage is extended to generate multiple first reference voltages. Multiple preset receiving delays are set for the first signal. Under the first reference voltage, data reading tests are performed by combining the preset receiving delay of the first signal and the first receiving delay of each data line. Based on the test results, the voltage value (i.e., the second reference voltage) and the delay value of the first signal (i.e., the target receiving delay of the first signal) that makes data reading most stable are selected.

[0044] For example, the first signal is a DQS signal. The initial reference voltage of 0.5V is extended to obtain five first reference voltages: 0.3V, 0.4V, 0.5V, 0.6V, and 0.7V. Five preset receive delays of 3ns, 4ns, 5ns, 6ns, and 7ns are set for the DQS signal. At 0.5V, when the DQS delay is 5ns, the data read error rate is 0; however, at 0.3V, even if the DQS delay is adjusted to 6ns, the error rate remains high. Finally, a second reference voltage of 0.5V is selected, and the target receive delay for the DQS is 5ns.

[0045] S103. Based on the second reference voltage and the target reception delay of the first signal, the first reception delay of each data line is calibrated to obtain the target reception delay of each data line.

[0046] The calibration process involves adjusting the delay parameters of the data lines based on defined reference parameters (second reference voltage, target reception delay of the first signal) to eliminate timing deviations caused by individual differences or environmental interference. The target reception delay of the data lines indicates the optimal reception delay of the data lines obtained after calibration, ensuring that each data line can accurately receive data under the second reference voltage and the target delay of the first signal.

[0047] Specifically, based on the determined second reference voltage and the target reception delay of the first signal, the initial reception delay of each data line is tested one by one to determine whether it meets the requirements for accurate data reception. Since different data lines have different physical characteristics, even with the same initial delay, the actual reception effect may differ. Therefore, it is necessary to fine-tune the reception delay of each data line until each data line can stably receive data under the current voltage and synchronization signal delay, ultimately obtaining the target reception delay for each data line.

[0048] For example, the first signal is a DQS signal. Based on a second reference voltage of 0.5V and a target DQS reception delay of 5ns, testing revealed occasional errors when the first reception delay of DQ0 was 5.2ns. After adjusting it to 5.3ns, the errors were eliminated. The first reception delay of DQ1 was unstable at 4.9ns, and it returned to normal after being adjusted to 4.8ns. Finally, the target reception delay of DQ0 was determined to be 5.3ns, and that of DQ1 was 4.8ns, and so on to complete the calibration of each data line.

[0049] S104. Based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, the transmission delay of the first signal and the transmission delay of each data line are calibrated.

[0050] The transmission delay indicates the time required for data to travel from the sender to the receiver, and together with the reception delay, determines the overall transmission timing. The transmission delay of the first signal indicates the time required for the first signal to travel from the sender to the receiver, and must be coordinated with the reception delay to ensure synchronization accuracy. The transmission delay of the data line indicates the transmission delay of the data signal on the data line, and must match its target reception delay to ensure correct overall transmission timing.

[0051] Specifically, based on the established second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, the transmission delay of the first signal and the transmission delay of each data line are adjusted respectively. For the first signal, the sum of the transmission delay and the target reception delay must meet the timing requirements of the system design. For each data line, the transmission delay must be matched with its target reception delay to ensure that the total delay of the data signal from transmission to reception is stable, ultimately achieving complete timing matching between the transmitting and receiving ends and ensuring the reliability of data transmission.

[0052] For example, assuming the system requires a total delay of 10ns for the DQS signal and its target receive delay is known to be 5ns, the DQS transmit delay needs to be calibrated to 5ns. For DQ0, its target receive delay is 5.3ns. If the required total delay for the data signal is 11ns, the DQ0 transmit delay needs to be calibrated to 5.7ns to ensure the timing consistency of data transmission and reception.

[0053] In one possible implementation, a preset transmission delay is traversed, and the memory is trained by writing to the data bus. The median value between the maximum and minimum transmission delays of the successful data bus training is determined as the transmission delay of the first signal. Based on the transmission delay of the first signal, the memory is trained by writing to the data bus, and the successful transmission delay is determined as the transmission delay of each data line.

[0054] In one possible implementation, between steps S101 to S104, the processor in the storage device performs at least one of long zero quantization calibration and short zero quantization calibration on the memory; and performs differential clock calibration on the memory.

[0055] The memory calibration method provided in this application systematically calibrates the reference voltage, the receiving and transmitting delays of the first signal, and the receiving and transmitting delays of each data line through a phased process. This effectively eliminates the influence of factors such as individual differences in memory hardware, ensuring that data is accurately sampled and identified during transmission, significantly reducing data read / write error rates, and improving data transmission reliability. Simultaneously, by expanding the reference voltage range and testing multiple preset delay values, the most suitable reference voltage, target receiving and transmitting delays of the first signal, and target receiving and transmitting delays of each data line can be selected, effectively improving the memory's storage performance.

[0056] Figure 2 A flowchart illustrating the memory calibration method provided in this application embodiment. Figure 2 .like Figure 2 As shown, the method includes:

[0057] S201. Determine the initial reference voltage and the first reception delay of each data line in the memory. The first reception delay is determined based on the second reception delay of the first signal, which is used to synchronize data transmission.

[0058] S202. The initial reference voltage is expanded to obtain multiple first reference voltages.

[0059] S203. Based on multiple first reference voltages, multiple preset receiving delays of the first signal, and the first receiving delay of each data line, perform a data reading test on the memory to obtain multiple data reading results corresponding to multiple preset receiving delays for each first reference voltage.

[0060] The data read test is a verification process that sends a read command to the memory (e.g., ChangeReadColumn(randomdataout)) and checks whether the data read result is correct. The data read result indicates the output of the data read test, usually "correct" or "incorrect," and is used to determine the validity of the current parameter combination.

[0061] S204. Based on multiple data reading results of multiple preset receiving delays corresponding to each first reference voltage, determine a second reference voltage among multiple first reference voltages.

[0062] Specifically, based on the test results corresponding to each first reference voltage, the most suitable data reading reference voltage, i.e., the second reference voltage, is selected from multiple first reference voltages. Based on the determined second reference voltage, the optimal value is selected from its corresponding preset receiving delay as the target receiving delay of the first signal.

[0063] In one possible implementation, for any first reference voltage, a plurality of preset receiving delays for which the data reading result is correct are determined, and the difference between the maximum and minimum values ​​among the plurality of preset receiving delays for which the data reading result is correct is determined; among the plurality of differences, the largest difference is determined, and the first reference voltage corresponding to the largest difference is determined as the second reference voltage.

[0064] Specifically, Figure 3 A schematic diagram illustrating the second reference voltage and the target reception delay of the first signal provided in the embodiments of this application is shown below. Figure 3 As shown, for the first reference voltage, preset receiving delays that ensure correct data reading are first selected, and the difference between the maximum and minimum values ​​of these delays is calculated. Then, the differences corresponding to each first reference voltage are compared, and the reference voltage with the largest difference is selected as the second reference voltage. The larger the difference, the higher the tolerance of the reference voltage to fluctuations in the first signal delay, and the better it can adapt to timing deviations in actual operation, resulting in stronger stability.

[0065] In one possible implementation, a first interval is determined based on multiple preset reception delays where the data reading result corresponding to the second reference voltage is correct; the preset reception delay corresponding to the midpoint of the first interval is determined as the target reception delay of the first signal.

[0066] Specifically, such as Figure 3 As shown, the first interval is the interval between the maximum preset reception delay and the minimum preset reception delay corresponding to the second reference voltage when the data reading result is correct. The target reception delay of the first signal is the midpoint of the first interval, that is, the midpoint between the minimum and maximum values.

[0067] In one possible implementation, multiple third reception delays corresponding to the data line are determined; based on the second reference voltage, the target reception delay of the first signal, and the multiple third reception delays, a data read test is performed on the memory to obtain the data read results for each third reception delay; based on the third reception delay where the data read results are correct, the target reception delay of the data line is determined.

[0068] Specifically, a short-zero ohm calibration is performed. A series of preset receive delay values ​​are determined for a single data line, forming multiple third receive delays. These third receive delays are used to test the data line's reception performance under different delays. Under fixed conditions of a second reference voltage and a first signal target receive delay, data reading tests are conducted using these third receive delays, and the correct reading results for each delay value are recorded. Based on the third receive delay corresponding to the correct results, the target receive delay for the data line is determined.

[0069] For example, taking the DQ0 data line, its first receive delay is 5.2ns, and the third receive delays are set to 5.0ns, 5.1ns, 5.2ns, 5.3ns, and 5.4ns. Testing was conducted under the conditions of a second reference voltage of 0.5V and a first signal target delay of 5ns. It was found that the reads were correct at 5.1ns, 5.2ns, and 5.3ns. Based on these results, the target receive delay of DQ0 can be determined.

[0070] In one possible implementation, a second interval is determined based on the third reception delay where the data reading result is correct; the third reception delay corresponding to the midpoint of the second interval is determined as the target reception delay of the data line.

[0071] The second interval is used to indicate the continuous range (from minimum to maximum) of the third receiving delay in which each data line is read correctly during the read test.

[0072] Specifically, for a single data line, based on the correct third reception delay of each data reading, a continuous second interval (e.g., from the minimum delay value to the maximum delay value) is determined. The midpoint of the second interval is calculated, and the delay value corresponding to the midpoint is taken as the target reception delay for that data line.

[0073] S205. Determine the target reception delay of the first signal based on the second reference voltage.

[0074] S206. Based on the second reference voltage and the target reception delay of the first signal, the first reception delay of each data line is calibrated to obtain the target reception delay of each data line.

[0075] S207. Based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, the transmission delay of the first signal and the transmission delay of each data line are calibrated.

[0076] In one possible implementation, a first transmission delay for each data line is determined, the first transmission delay being determined based on a second transmission delay of a first signal; a second reference voltage is extended to obtain multiple third reference voltages; based on the multiple third reference voltages, multiple preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, a fourth reference voltage for data writing to the memory and the target transmission delay of the first signal are determined; based on the fourth reference voltage and the target transmission delay of the first signal, the first transmission delay of each data line is calibrated to obtain the target transmission delay of each data line.

[0077] The first transmission delay indicates the initial delay parameter when the data line transmits data, and is determined based on the second transmission delay of the first signal. The third reference voltage indicates multiple voltage values ​​obtained after expanding the second reference voltage, used to test voltage adaptability during data writing. The preset transmission delay indicates a series of transmission delay values ​​pre-set for the first signal, used to test the data writing effect under different transmission timings. The fourth reference voltage indicates the optimal reference voltage for data writing, determined through testing. The target transmission delay of the first signal indicates the optimal delay value for transmitting the first signal, determined through testing.

[0078] Specifically, a first transmission delay is determined for each data line as the initial transmission delay parameter. The second reference voltage is extended to obtain multiple third reference voltages, covering the possible write voltage range. Combining these multiple third reference voltages, multiple preset transmission delays for the first signal, the first transmission delay of each data line, and the determined target receive delays for the first signal and data lines, data write tests are performed to determine a suitable fourth reference voltage and target transmission delay for the first signal. Based on the fourth reference voltage and the target transmission delay of the first signal, the first transmission delay of each data line is calibrated to obtain the target transmission delay.

[0079] In one possible implementation, a data write test is performed on the memory based on multiple third reference voltages, multiple preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, to obtain multiple data write results for multiple preset transmission delays corresponding to each third reference voltage; based on the multiple data write results for multiple preset transmission delays corresponding to each third reference voltage, a fourth reference voltage is determined among the multiple third reference voltages; based on the multiple preset transmission delays for which the data write result corresponding to the fourth reference voltage is correct, the target transmission delay of the first signal is determined.

[0080] The data write test is used to indicate the process of sending a write command to the memory and verifying whether the data is stored correctly. The data write result indicates the output of the data write test, usually "correct" or "incorrect," and is used to determine the validity of the write parameters.

[0081] Specifically, multiple sets of data write tests were conducted by combining multiple third reference voltages, multiple preset transmission delays of the first signal, the first transmission delay of each data line, and the determined target reception delay of the first signal and the target reception delay of the data line, and the write results under each set of parameter combinations were recorded. Figure 4 A schematic diagram illustrating the target transmission delay of the fourth reference voltage and the first signal provided in the embodiments of this application is shown below. Figure 4 As shown, for the third reference voltage, firstly, preset transmission delays that ensure correct data reading are selected, and the difference between the maximum and minimum values ​​of these delays is calculated. Then, the differences corresponding to each first reference voltage are compared, and the reference voltage with the largest difference is selected as the fourth reference voltage. Based on the preset transmission delays for correct writing under the fourth reference voltage, the target transmission delay of the first signal is the midpoint between the minimum and maximum values.

[0082] In one possible implementation, the fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line are stored; when the memory is powered on, the stored fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line are read to configure the memory.

[0083] The storage function is used to indicate that the parameters obtained from the calibration are saved to a non-volatile area of ​​the memory to ensure that they are not lost after power failure.

[0084] Specifically, the key parameters obtained from calibration are stored to avoid repeated calibration each time it is used. When the memory is powered on, these pre-stored parameters are automatically read, and the hardware circuit is configured according to the parameters, so that the memory directly enters the calibrated working state.

[0085] The memory calibration method provided in this application systematically calibrates the reference voltage, the receiving and transmitting delays of the first signal, and the receiving and transmitting delays of each data line through a phased process. This effectively eliminates the influence of factors such as individual differences in memory hardware, ensuring that data is accurately sampled and identified during transmission, significantly reducing data read / write error rates, and improving data transmission reliability. Simultaneously, by expanding the reference voltage range and testing multiple preset delay values, the most suitable reference voltage, target receiving and transmitting delays of the first signal, and target receiving and transmitting delays of each data line can be selected, effectively improving the memory's storage performance. Furthermore, by clearly defining the process of conducting data read tests based on multiple sets of reference voltages and preset delays, and then selecting the second reference voltage and the target receiving delay of the first signal based on the test results, the selected parameters are ensured to be actually verified, avoiding deviations between theoretical settings and actual hardware characteristics. This improves the scientific rigor and reliability of parameter selection, laying an accurate foundation for subsequent calibration steps.

[0086] By calculating the boundary value difference of the effective reception delay under each reference voltage and selecting the reference voltage with the largest difference as the second reference voltage, the operating voltage with the highest tolerance for delay fluctuations can be selected. This selection method makes the memory more adaptable to factors such as timing offsets and hardware differences in actual operation, significantly improving the stability of data reading and anti-interference capability.

[0087] By defining the target reception delay of the first signal as the midpoint of the effective delay interval, the target delay is positioned at the center of a safe range, maximizing its distance from the upper and lower boundaries. This design effectively addresses potential delay fluctuations in practical applications, reduces the risk of data errors caused by delays exceeding the effective range, and further ensures the reliability of the synchronization signal.

[0088] By setting multiple third-order receive delays individually for each data line and testing them, and then determining the target receive delay based on the correct results, timing deviations caused by differences in the physical characteristics of different data lines can be specifically eliminated. This fine-grained calibration ensures that each data line operates at the optimal delay, improving the consistency and accuracy of overall data transmission.

[0089] By defining the target reception delay of a data line as the midpoint of its effective delay range, the reception delay of a single data line is placed within a safe center, reducing the impact of delay offsets caused by environmental interference or hardware aging on data reception. This design further enhances the anti-interference capability of a single data line, ensuring stable data reception under complex operating conditions.

[0090] By symmetrically calibrating the transmission parameters and matching them with the predetermined reception parameters, a complete "receive-transmit" closed-loop calibration mechanism is formed. This mechanism ensures the timing consistency of the entire data transmission link, solves the transmission-reception mismatch problem that may occur if only the reception is calibrated, and improves the reliability of data writing.

[0091] By filtering the fourth reference voltage and the first signal target transmission delay through actual data write tests, the matching of write parameters with the actual hardware characteristics was ensured. In particular, the filtering logic for the reference receiver parameters gives the transmitter parameters high resistance to fluctuations, further guaranteeing the stability of data writing. This complements the receiver calibration and improves the overall read and write performance of the memory.

[0092] By storing calibration parameters and automatically loading them upon power-on, the calibration process is avoided from being repeated every time the system boots up, significantly shortening the memory's boot time and reducing system resource consumption. Simultaneously, the pre-stored optimal parameters ensure that the memory can directly enter the appropriate working state upon each power-on, improving system stability and ease of use, making it particularly suitable for applications requiring fast boot times.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0094] Figure 5 This is a schematic diagram of the structure of a memory calibration device provided in an embodiment of this application. Figure 5 As shown, embodiments of this application also provide a memory calibration device 50, including: a determination module 501, a processing module 502, and a calibration module 503.

[0095] The determination module 501 is used to determine the initial reference voltage and the first reception delay of each data line in the memory. The first reception delay is determined based on the second reception delay of the first signal, which is used to synchronize data transmission.

[0096] The processing module 502 is used to perform extended processing on the initial reference voltage to obtain multiple first reference voltages, and based on the multiple first reference voltages, multiple preset receiving delays of the first signal and the first receiving delay of each data line, determine the second reference voltage for data reading from the memory and the target receiving delay of the first signal.

[0097] The calibration module 503 is used to calibrate the first reception delay of each data line based on the second reference voltage and the target reception delay of the first signal, so as to obtain the target reception delay of each data line.

[0098] The calibration module 503 is also used to calibrate the transmission delay of the first signal and the transmission delay of each data line based on the second reference voltage, the target reception delay of the first signal and the target reception delay of each data line.

[0099] In one possible implementation, the processing module 502 is specifically used for:

[0100] Based on multiple first reference voltages, multiple preset reception delays of the first signal, and the first reception delay of each data line, the memory is tested for data reading, and multiple data reading results corresponding to multiple preset reception delays of each first reference voltage are obtained.

[0101] Based on multiple data reading results corresponding to multiple preset receiving delays for each first reference voltage, a second reference voltage is determined among multiple first reference voltages;

[0102] The target reception delay of the first signal is determined based on the second reference voltage.

[0103] In one possible implementation, the processing module 502 is specifically used for:

[0104] For any given first reference voltage, determine the multiple preset receiving delays for which the data reading result is correct, and determine the difference between the maximum and minimum values ​​among the multiple preset receiving delays for which the data reading result is correct;

[0105] Among multiple differences, the largest difference is determined, and the first reference voltage corresponding to the largest difference is determined as the second reference voltage.

[0106] In one possible implementation, the processing module 502 is specifically used for:

[0107] Based on multiple preset reception delays where the data reading result corresponding to the second reference voltage is correct, the first interval is determined;

[0108] The preset reception delay corresponding to the midpoint of the first interval is determined as the target reception delay of the first signal.

[0109] In one possible implementation, the processing module 502 is specifically used for:

[0110] Determine the multiple third receive delays corresponding to the data lines;

[0111] Based on the second reference voltage, the target reception delay of the first signal, and multiple third reception delays, a data read test is performed on the memory to obtain the data read results for each third reception delay.

[0112] Based on the third reception delay, which indicates that the data reading result is correct, the target reception delay of the data line is determined.

[0113] In one possible implementation, the processing module 502 is specifically used for:

[0114] Based on the correct data reading result and the third reception delay, the second interval is determined;

[0115] The third receiving delay corresponding to the midpoint of the second interval is determined as the target receiving delay of the data line.

[0116] In one possible implementation, the calibration module 503 is specifically used for:

[0117] The first transmission delay of each data line is determined, and the first transmission delay is determined based on the second transmission delay of the first signal;

[0118] The second reference voltage is expanded to obtain multiple third reference voltages;

[0119] Based on multiple third reference voltages, multiple preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, the fourth reference voltage for data writing to the memory and the target transmission delay of the first signal are determined.

[0120] Based on the fourth reference voltage and the target transmission delay of the first signal, the first transmission delay of each data line is calibrated to obtain the target transmission delay of each data line.

[0121] In one possible implementation, the calibration module 503 is specifically used for:

[0122] Based on multiple third reference voltages, multiple preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, a data write test is performed on the memory to obtain multiple data write results corresponding to multiple preset transmission delays of each third reference voltage.

[0123] Based on the multiple data writing results corresponding to multiple preset transmission delays for each third reference voltage, a fourth reference voltage is determined among the multiple third reference voltages;

[0124] Based on multiple preset transmission delays where the data writing result corresponding to the fourth reference voltage is correct, the target transmission delay of the first signal is determined.

[0125] In one possible implementation, the calibration module 503 is further configured to:

[0126] Store the fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line;

[0127] When the memory is powered on, the stored fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line are read to configure the memory.

[0128] For a description of the features in the embodiment corresponding to the calibration device for the memory, please refer to the relevant description in the embodiment corresponding to the calibration method for the memory, which will not be repeated here.

[0129] Figure 6 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. Figure 6 As shown, the storage device 60 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the storage device 60 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0130] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the above-described memory calibration method embodiment.

[0131] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0132] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0133] The memory may include high-speed memory (Random Access Memory, RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0134] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0135] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described XX method embodiments when it is run.

[0136] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0137] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described memory calibration method embodiments.

[0138] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory calibration method embodiments.

[0139] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of this application.

[0140] The above provides a detailed description of a memory calibration method and a memory device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for calibrating a memory, characterized in that, include: An initial reference voltage and a first receive delay for each data line in the memory are determined, the first receive delay being determined based on a second receive delay of a first signal used for synchronizing data transmission; The initial reference voltage is extended to obtain multiple first reference voltages. Based on the multiple first reference voltages, multiple preset reception delays of the first signal, and the first reception delay of each data line, the second reference voltage for data reading from the memory and the target reception delay of the first signal are determined. Based on the second reference voltage and the target reception delay of the first signal, the first reception delay of each data line is calibrated to obtain the target reception delay of each data line. Based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, the transmission delay of the first signal and the transmission delay of each data line are calibrated.

2. The method according to claim 1, characterized in that, Based on the plurality of first reference voltages, the plurality of preset reception delays of the first signal, and the first reception delay of each data line, determining the second reference voltage for data reading from the memory and the target reception delay of the first signal includes: Based on the plurality of first reference voltages, the plurality of preset reception delays of the first signal, and the first reception delay of each data line, a data read test is performed on the memory to obtain a plurality of data read results corresponding to the plurality of preset reception delays of each first reference voltage; Based on multiple data reading results corresponding to multiple preset receiving delays for each of the first reference voltages, the second reference voltage is determined from the multiple first reference voltages; The target reception delay of the first signal is determined based on the second reference voltage.

3. The method according to claim 2, characterized in that, Based on multiple data reading results corresponding to multiple preset receiving delays for each of the first reference voltages, the second reference voltage is determined from the multiple first reference voltages, including: For any given first reference voltage, determine multiple preset receiving delays for which the data reading result is correct, and determine the difference between the maximum and minimum values ​​among the multiple preset receiving delays for which the data reading result is correct; Among multiple differences, the largest difference is determined, and the first reference voltage corresponding to the largest difference is determined as the second reference voltage.

4. The method according to claim 3, characterized in that, Determining the target reception delay of the first signal based on the second reference voltage includes: Based on multiple preset reception delays where the data reading result corresponding to the second reference voltage is correct, a first interval is determined; The preset reception delay corresponding to the midpoint of the first interval is determined as the target reception delay of the first signal.

5. The method according to any one of claims 1-4, characterized in that, For any data line; based on the second reference voltage and the target reception delay of the first signal, the first reception delay of each data line is calibrated to obtain the target reception delay of each data line, including: Determine multiple third receive delays corresponding to the data lines; Based on the second reference voltage, the target reception delay of the first signal, and the plurality of third reception delays, a data read test is performed on the memory to obtain the data read results for each third reception delay. Based on the third reception delay, which indicates that the data reading result is correct, the target reception delay of the data line is determined.

6. The method according to claim 5, characterized in that, Based on the third reception delay, which indicates that the data reading result is correct, the target reception delay of the data line is determined, including: Based on the correct data reading result and the third reception delay, the second interval is determined; The third receiving delay corresponding to the midpoint of the second interval is determined as the target receiving delay of the data line.

7. The method according to any one of claims 1-4, characterized in that, Based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, the transmission delay of the first signal and the transmission delay of each data line are calibrated, including: A first transmission delay is determined for each data line, the first transmission delay being determined based on a second transmission delay of the first signal; The second reference voltage is expanded to obtain multiple third reference voltages; Based on the plurality of third reference voltages, the plurality of preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, a fourth reference voltage for writing data to the memory and a target transmission delay of the first signal are determined. Based on the fourth reference voltage and the target transmission delay of the first signal, the first transmission delay of each data line is calibrated to obtain the target transmission delay of each data line.

8. The method according to claim 7, characterized in that, Based on the plurality of third reference voltages, the plurality of preset transmission delays of the first signal, the first transmission delay of each data line, the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line, a fourth reference voltage for writing data to the memory and the target transmission delay of the first signal are determined, including: Based on the plurality of third reference voltages, the plurality of preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, a data write test is performed on the memory to obtain a plurality of data write results corresponding to the plurality of preset transmission delays of each third reference voltage. Based on the multiple data writing results of multiple preset transmission delays corresponding to each of the third reference voltages, the fourth reference voltage is determined among the multiple third reference voltages; Based on multiple preset transmission delays where the data writing result corresponding to the fourth reference voltage is correct, the target transmission delay of the first signal is determined.

9. The method according to claim 8, characterized in that, The method further includes: The fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line are stored. When the memory is powered on, the stored fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line are read to configure the memory.

10. A storage device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the memory calibration method as described in any one of claims 1 to 9 when executing the computer program.

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