Light detection device and electronic apparatus

Abstract

The invention further improves the reliability of the light detection device and the electronic apparatus. The light detection device includes: a semiconductor layer having a first surface and a second surface opposite to each other in a thickness direction; a multilayer wiring layer provided on the first surface side of the semiconductor layer; a warpage suppression film provided on the side of the multilayer wiring layer facing the semiconductor layer side; and a recess that overlaps the warpage suppression film in plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer. The warpage suppression film then has an opening in an overlapping region that overlaps with the groove in a plan view.

Description

Technical Field

[0001] This technology (the technology disclosed herein) relates to photodetectors and electronic devices, and more specifically to technologies that are effective when applied to photodetectors and electronic devices including warp suppression layers. Background Technology

[0002] In optical detection devices such as solid-state imaging devices or ranging devices, a stacking type is known in which semiconductor layers on which elements are formed are stacked in multiple levels. Optical detection devices of this stacking type can transmit signals at high speeds. Patent Document 1 discloses a solid-state imaging device having a two-level stacked structure with two semiconductor layers. Furthermore, Patent Document 1 also discloses a technique for providing a warpage suppression film (warpage correction layer) to suppress warpage of a semiconductor substrate containing semiconductor layers and multiple wiring layers. Citation List Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-204810 Summary of the Invention The problem to be solved by the present invention

[0004] Meanwhile, in the stacked photodetector, a multilayer wiring layer is disposed on one surface side of the semiconductor layer, and a warpage suppression film is further disposed on the side of the multilayer wiring layer opposite to the semiconductor layer side. Then, the multilayer wiring layer disposed on one side surface of the semiconductor layer and the external electrode pad disposed on the side of the semiconductor layer opposite to that side surface are electrically connected through a groove disposed in the semiconductor layer.

[0005] In this configuration, stress tends to concentrate locally around the grooves, and in a top view, the portion of the multilayer wiring layer overlapping the grooves of the semiconductor layer may deform. This deformation of the multilayer wiring layer can cause warping or peeling of the wiring and internal electrode pads, leading to decreased reliability, thus leaving room for improvement.

[0006] The purpose of this technology is to provide a technique that can further improve the reliability of optical detection devices and electronic devices. Solution to the problem

[0007] (1) A light detection device according to one aspect of the present technology includes: A semiconductor layer having a first surface and a second surface that are opposite to each other in the thickness direction; A multilayer wiring layer is disposed on the first surface side of the semiconductor layer; A warpage suppression film is disposed on the side of the multilayer wiring layer opposite to the semiconductor layer side; and The groove overlaps with the warpage suppression film in a plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer. Then, the warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in the plan view.

[0008] (2) The optical detection device according to another aspect of the present technology includes: A first semiconductor layer has a first surface and a second surface opposite to each other, and is provided with a photoelectric conversion unit that performs photoelectric conversion on light incident from the second surface side; A first multilayer wiring layer is disposed on the first surface side of the first semiconductor layer; The second semiconductor layer has a third surface and a fourth surface opposite to each other, and transistors are disposed thereon; A second multilayer wiring layer is disposed on the third surface side of the second semiconductor layer and overlaps with the first multilayer wiring layer; A warpage suppression film disposed between the first multilayer wiring layer and the second multilayer wiring layer; and The groove overlaps with the warpage suppression film in a plan view and extends from the fourth surface side of the second semiconductor layer to the second multilayer wiring layer. Then, the warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in the plan view.

[0009] (3) An electronic device according to another aspect of the present technology includes: The optical detection device; An optical lens that forms an image of the light from the subject onto the imaging surface of the detection device; and A signal processing circuit that processes the signal output from the optical detection device. Attached Figure Description

[0010] Figure 1 This is a chip layout diagram illustrating a construction example of a solid-state imaging device according to a first embodiment of the present technology. Figure 2 A block diagram illustrating a construction example of a solid-state imaging apparatus according to a first embodiment of the present technology. Figure 3 This is an equivalent circuit diagram illustrating a construction example of a pixel and pixel circuit according to a first embodiment of the present technology. Figure 4 It is a schematic representation of the path along Figure 1 The longitudinal section diagram of the longitudinal section structure cut by line a1-a1. Figure 5 yes Figure 4 The unfolded diagram. Figure 6 yes Figure 5 A magnified view of a portion of it. Figure 7 It is a planar diagram schematically showing the planar pattern in the overlapping region of the warp suppression membrane. Figure 8 This is a schematic longitudinal cross-sectional view showing the deformation in the overlapping area where the interface between the first and second layers overlaps with the groove in a conventional solid-state imaging device. Figure 9 This is a schematic longitudinal cross-sectional view showing the deformation in the overlapping region where the interface between the first and second stacks of the solid-state imaging apparatus according to the first embodiment overlaps with the groove. Figure 10 This is a schematic plan view illustrating a variation 1-1 of the first embodiment of the present technology. Figure 11 This is a schematic plan view illustrating variations 1-2 of the first embodiment of the present technology. Figure 12 The diagram schematically shows longitudinal cross-sectional views of variations 1-3 of the first embodiment of the present technology. Figure 13 The diagram schematically shows longitudinal cross-sectional views of variations 1-4 of the first embodiment of the present technology. Figure 14 This is a chip layout diagram illustrating a construction example of a solid-state imaging device according to a second embodiment of the present technology. Figure 15 It is a schematic representation of the path along Figure 14 The longitudinal section diagram of the longitudinal section structure cut by line a14-a14. Figure 16 This is a diagram illustrating a construction example of an electronic device according to a third embodiment of the present technology. Detailed Implementation

[0011] The embodiments of this technology will be described in detail below with reference to the accompanying drawings. Note that in the illustrations referenced in the following description, identical or similar parts are indicated by the same or similar reference numerals. It should be noted that the illustrations are schematic, and the relationships between thickness and planar dimensions, the thickness ratios between layers, etc., may differ from actual measurements. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0012] Furthermore, it goes without saying that there are some differences in the dimensional relationships and proportions between the various figures. Moreover, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0013] Furthermore, the following embodiments merely illustrate the apparatus and methods for implementing the technical concept of this technology, and are not intended to limit the technical concept of this technology to the following constructions. That is, various modifications can be made to the technical concept of this technology within the scope of the claims.

[0014] Furthermore, the definitions of up and down directions in the following description are for illustrative purposes only and are not intended to limit the technical concept of this technology. For example, when an object is rotated 90° for observation, the up and down directions will be converted into the left and right directions; while when an object is rotated 180° for observation, the up and down directions will be reversed.

[0015] Furthermore, in the following embodiments, among the three mutually orthogonal directions in space, the first and second mutually orthogonal directions within the same plane are defined as the X direction and the Y direction, respectively, and the third direction orthogonal to the first and second directions is defined as the Z direction. Furthermore, in the following embodiments, the thickness direction of the semiconductor layers 30 and 70, described later, is referred to as the Z direction.

[0016] [First Embodiment] In the first embodiment, an example of applying this technology to a solid-state imaging device (back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor) as a light detection device will be described. In addition, in the first embodiment, a warpage suppression film (warpage adjustment film) disposed between the first stack (first semiconductor substrate) and the second stack (second semiconductor substrate) will be described.

[0017] <<Overall Structure of Solid State Imaging Devices>> First, the overall structure of the solid-state imaging device 1A will be explained. like Figure 1 As shown, the solid-state imaging device 1A according to the first embodiment of the present technology mainly includes a semiconductor chip 2 having a rectangular two-dimensional planar shape in a planar view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. Figure 16 As shown, the solid-state imaging device 1A (101) receives image light (incident light 106) from the subject through an optical lens 102, converts the incident light 106, which forms an image on the imaging plane, into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal.

[0018] like Figure 1As shown, in a two-dimensional plane containing mutually orthogonal X and Y directions, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes: a rectangular sensor pixel array unit 2A disposed at the central portion of the semiconductor chip; and a peripheral portion 2B disposed outside and surrounding the sensor pixel array unit 2A. The semiconductor chip 2 is formed during the manufacturing process by cutting a semiconductor wafer including a first semiconductor layer 30 and a second semiconductor layer 70 (described later) into small pieces for each chip forming region. Therefore, the structure of the solid-state imaging device 1A described below is substantially similar to the structure before the semiconductor wafer is cut into small pieces. That is, this technology is applicable to semiconductor chips and semiconductor wafers.

[0019] Sensor pixel array unit 2A, for example, receives signals from... Figure 16 The optical lens (optical system) 102 shown is a light-receiving surface that focuses the light. Then, multiple sensor pixels (pixels) 3 are arranged in a matrix in the sensor pixel array unit 2A in a two-dimensional plane including the X and Y directions. In other words, the sensor pixels 3 are repeatedly arranged in the two-dimensional plane along mutually orthogonal X and Y directions.

[0020] like Figure 1 As shown, multiple external electrode pads 94 are disposed in the peripheral portion 2B. Figure 4 As shown, the plurality of external electrode pads 94 are disposed on the side of the semiconductor chip 2 opposite to the sensor pixel array unit 2A. Figure 1 As shown, each of the plurality of external electrode pads 94 is arranged, for example, along the four sides of a two-dimensional plane of the semiconductor chip 2. Each of the plurality of external electrode pads 94 serves as an input / output terminal for electrically connecting the semiconductor chip 2 to an external device.

[0021] <Logic Circuits> Semiconductor chip 2 includes Figure 2 The logic circuit 13 shown is as follows. Figure 2 As shown, logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8, etc. Logic circuit 13 may include, for example, a complementary MOS (CMOS) circuit, which includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a p-channel MOSFET as field-effect transistors.

[0022] Figure 2The vertical driving circuit 4 shown includes, for example, a shift register. The vertical driving circuit 4 sequentially selects the desired pixel driving line 10, provides pulses to the selected pixel driving line 10 for driving the sensor pixel 3, and drives each sensor pixel 3 row by row. That is, the vertical driving circuit 4 selectively scans each sensor pixel 3 in the sensor pixel array unit 2A row by row along the vertical direction, and provides the pixel signal from each sensor pixel 3, based on the signal charge generated by the photoelectric conversion unit (photoelectric conversion element) of the sensor pixel 3 according to the amount of received light, to the column signal processing circuit 5 via the vertical signal line 11.

[0023] Figure 2 The column signal processing circuit 5 shown is arranged for each column of sensor pixels 3, and performs signal processing such as noise cancellation on the signal output from a row of sensor pixels 3 for each column of pixels. For example, each column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) for eliminating pixel-specific fixed-pattern noise and analog-to-digital (AD) conversion.

[0024] Figure 2 The horizontal drive circuit 6 shown includes, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scan pulses to the column signal processing circuits 5 to sequentially select each column signal processing circuit 5 and cause each column signal processing circuit 5 to output the processed pixel signal to the horizontal signal line 12.

[0025] Figure 2 The output circuit 7 shown processes the pixel signals sequentially provided from each column signal processing circuit 5 via the horizontal signal line 12 and outputs the processed signal. Signal processing can employ, for example, buffering, black level adjustment, column change correction, and various digital signal processing techniques.

[0026] Figure 2 The control circuit 8 shown generates clock and control signals based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, serving as the operating reference for the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6. Then, the control circuit 8 outputs the generated clock and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6.

[0027] <Circuit Structure of Sensor Pixels> like Figure 3 As shown, each of the plurality of sensor pixels 3 includes a photoelectric conversion region 32 and a pixel circuit (readout circuit) 15. The photoelectric conversion region 32 includes a photoelectric conversion unit 34, a transfer transistor TR which serves as a pixel transistor, and a floating diffusion region FD which serves as a charge holding part. The pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 32.

[0028] The first embodiment has, but is not limited to, the following circuit configuration: for example, one sensor pixel 3 is assigned a pixel circuit 15. For example, the following circuit configuration can be used: multiple sensor pixels 3 share one pixel circuit 15. Specifically, the following circuit configuration can be used: a sensor pixel group (photoelectric conversion group) shares one pixel circuit 15, in which four sensor pixels 3 arranged in a 2×2 layout are set as a unit, that is, two sensor pixels 3 are arranged in the X direction and two sensor pixels 3 are arranged in the Y direction. Furthermore, the following circuit configuration can be used: a sensor pixel group (photoelectric conversion group) shares one pixel circuit 15, in which two sensor pixels 3 are set as a unit. Furthermore, the following circuit configuration can be used: a sensor pixel group (photoelectric conversion group) shares one pixel circuit 15, in which four or more sensor pixels 3 are set as a unit.

[0029] Figure 3 The photoelectric conversion unit 34 shown includes, for example, a pn junction photodiode (PD) and generates signal charge according to the amount of light received. The cathode side of the photoelectric conversion unit 34 is electrically connected to the source region of the transmission transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground).

[0030] Figure 3 The transmission transistor TR shown transmits the signal charge generated by photoelectric conversion in photoelectric conversion unit 34 to the floating diffusion region FD. The source region of the transmission transistor TR is electrically connected to the cathode side of photoelectric conversion unit 34, and the drain region of the transmission transistor TR is electrically connected to the floating diffusion region FD. Furthermore, the gate electrode of the transmission transistor TR is... Figure 2 One of the transmission transistor drive lines in the pixel drive line 10 shown is electrically connected.

[0031] Figure 3 The floating diffusion region FD shown temporarily holds (accumulates) the signal charge transmitted from the photoelectric conversion unit 24 via the transmission transistor TR.

[0032] For each sensor pixel 3, the photoelectric conversion region 32, including the photoelectric conversion unit 34, the transmission transistor TR, and the floating diffusion region FD, is installed... Figure 4 and Figure 5 On the first semiconductor layer 30 shown.

[0033] Figure 3The pixel circuit 15 shown reads the signal charge held in the floating diffusion region FD and outputs a pixel signal based on the read signal charge. The pixel circuit 15 includes, for example, an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST as pixel transistor Q, but is not limited thereto. These pixel transistors (AMP, SEL, RST) and the aforementioned transmission transistor TR all include MOSFETs as field-effect transistors, which have, for example, a gate electrode insulating film formed of a silicon oxide (SiO2) film, a gate electrode, and a pair of main electrode regions serving as source and drain regions. Furthermore, these transistors can also be metal-insulator-semiconductor field-effect transistors (MISFETs) having a silicon nitride (Si3N4) film as a gate electrode insulating film or a multilayer film such as a silicon nitride film and a silicon oxide film.

[0034] Figure 3 The source region of the amplifying transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. Then, the gate electrode of the amplifying transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.

[0035] Figure 3 The source of the selected transistor SEL is electrically connected to the vertical signal line 11 (VSL), and its drain region is electrically connected to the source region of the amplifying transistor AMP. Then, the gate electrode of the selected transistor SEL is... Figure 2 The select transistor drive line in the pixel drive line 10 shown is electrically connected.

[0036] Figure 3 The source region of the reset transistor RST is electrically connected to the floating diffusion region FD and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. Then, the gate electrode of the reset transistor RST is... Figure 2 The reset transistor drive line in the pixel drive line 10 shown is electrically connected.

[0037] when Figure 3 When the transmission transistor TRG shown is turned on, the transmission transistor TR transmits the signal charge generated by the photoelectric conversion unit 24 to the floating diffusion region FD.

[0038] when Figure 3 When the reset transistor RST is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the pixel signal output timing of the pixel circuit 15.

[0039] Figure 3 The amplifying transistor AMP shown generates a voltage signal corresponding to the level of the signal charge held in the floating diffusion region FD as a pixel signal. The amplifying transistor AMP acts as a source follower amplifier and outputs a pixel signal representing the voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 24. When the select transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs the voltage corresponding to that potential to the column signal processing circuit 5 through the vertical signal line 11 (VSL).

[0040] Here, for reference Figure 3 During operation of the solid-state imaging apparatus 1A according to the first embodiment, the signal charge generated by the photoelectric conversion unit 34 of the sensor pixel 3 is held (accumulated) in the floating diffusion region FD by the transfer transistor TR of the sensor pixel 3. Then, the pixel circuit 15 reads the signal charge held in the floating diffusion region FD and applies it to the gate electrode of the amplification transistor AMP of the pixel circuit 15. A horizontal selection control signal is provided from the vertical shift register to the gate electrode of the selection transistor SEL of the pixel circuit 15. Then, by setting the selection control signal to a high (H) level, the selection transistor SEL is turned on, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST is turned on, and the signal charge accumulated in the floating diffusion region FD is reset.

[0041] <Other pixel circuits> Alternatively, the selection transistor SEL can be omitted if necessary. Furthermore, when the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

[0042] In addition, a switching transistor can be placed between the reset transistor RST, the floating diffusion region FD, and the gate electrode of the amplification transistor AMP. This switching transistor controls the charge retention of the floating diffusion region FD and adjusts the voltage amplification factor according to the potential amplified by the amplification transistor AMP.

[0043] Furthermore, a switching transistor is used to switch the conversion efficiency. Typically, when capturing images in low light, the pixel signal is small. Since Q=CV, if the FD capacitance C (floating diffusion capacitance C) of the charge holding section (floating diffusion region FD) is large during charge-to-voltage conversion, the conversion voltage V during voltage conversion via the amplifying transistor AMP will be low. On the other hand, since the pixel signal is large in bright light, unless the FD capacitance C of the charge holding section is large, the charge holding section cannot fully receive the charge from the photoelectric conversion unit 24 (photodiode PD). Furthermore, the FD capacitance C of the charge holding section needs to be large so that the voltage V obtained by the amplifying transistor AMP through voltage conversion is not too high (in other words, it becomes too low). Therefore, when the switching transistor is turned on, the capacitance of the gate electrode corresponding to the switching transistor increases, resulting in an increase in the overall FD capacitance C. On the other hand, when the switching transistor is turned off, the overall FD capacitance C decreases. In this way, by turning the switching transistor on / off, the FD capacitance C can be changed, thereby switching the conversion efficiency.

[0044] <<Detailed Structure of Solid-State Imaging Devices>> Next, we will refer to Figures 4 to 7 To illustrate the specific structure of the solid-state imaging device 1A. like Figure 4 and Figure 5 As shown, the solid-state imaging device 1A (semiconductor chip 2) includes a first stack (first semiconductor substrate) 20 and a second stack (second semiconductor substrate) 60. The first stack 20 and the second stack 60 are then bonded together with their bonding surfaces 20a and 60a facing each other. Sensor pixel array unit 2A, control circuit 8, and pixel circuit 15 are mounted on the first stack 20. Logic circuit 13, including a vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, and output circuit 7, is mounted on the second stack 60.

[0045] <First Stack> like Figure 4 and Figure 5 As shown, the first stack 20 includes: a first semiconductor layer 30 having a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction); a first multilayer wiring layer 40 disposed on the first surface S1 side of the first semiconductor layer 30; and a light-concentrating layer 50 disposed on the second surface S2 side of the first semiconductor layer 30. Furthermore, on the side of the first multilayer wiring layer 40 opposite to the side of the first semiconductor layer 30, the first stack 20 includes a warpage suppression film 46 and a bonding layer 47 stacked sequentially from the side of the first multilayer wiring layer 40. Here, the first surface S1 of the first semiconductor layer 30 may also be referred to as the main surface or the element formation surface, and the second surface S2 may also be referred to as the back surface. Then, as will be explained in detail later, the solid-state imaging apparatus 1A according to the first embodiment performs photoelectric conversion on the incident light incident from the second surface S2 side of the first semiconductor layer 30 by means of a photoelectric conversion unit 34 (photodiode PD) disposed in the photoelectric conversion region 32 of the first semiconductor layer 30. Therefore, in the first embodiment, the second surface S2 of the first semiconductor layer 30 may also be referred to as the light incident surface.

[0046] <Second stack> The second stack 60 includes: a second semiconductor layer 70 having a third surface S3 and a fourth surface S4 located on opposite sides in the thickness direction (Z direction); and a second multilayer wiring layer 80 disposed on the third surface S3 side of the second semiconductor layer 70. In addition, the second stack 60 includes a groove 91 extending from the third surface S3 side of the second semiconductor layer 70 to the second multilayer wiring layer 80, an isolation insulating film 92 disposed along the inner wall of the groove 91, and a contact electrode 93 disposed along the inner wall of the groove 91 through the isolation insulating film 92 and electrically connected to the second multilayer wiring layer 80. In addition, the second stack 60 includes an external electrode pad 94 disposed on the fourth surface S4 side of the second semiconductor layer 70 and electrically connected to the contact electrode 93, and a solder resist film 95 disposed in the groove 91 across the contact electrode 93. Furthermore, on the side of the second multilayer wiring layer 80 opposite to the side of the second semiconductor layer 70, the second stack 60 includes a warpage suppression film 86 and a bonding layer 87 sequentially stacked from the side of the second multilayer wiring layer 80. Here, the third surface S3 of the second semiconductor layer 70 can also be referred to as the main surface or the device forming surface, and the fourth surface S4 can also be referred to as the back surface.

[0047] <Light Concentrating Layer> like Figure 4 and Figure 5 As shown, a light-concentrating layer 50 is disposed on the second surface S2 side of the first semiconductor layer 30. The light-concentrating layer 50 has a stacked structure in which, for example, a planarization film 51, an optical filter 53, and an on-chip lens 54 are stacked sequentially from the second surface S2 side of the first semiconductor layer 30, but is not limited thereto.

[0048] A planarization film 51 is disposed on the second surface S2 side of the semiconductor layer 30 and covers the second surface S2 of the semiconductor layer 30, and planarizes the second surface S2 side of the semiconductor layer 30.

[0049] Optical filter 53 and microlens 54 are provided for each sensor pixel 3. Optical filter 53 performs color separation on incident light incident from the light incident surface side (second surface S2 side) of semiconductor chip 2. Microlens 54 converges the illumination light and makes the converged light effectively enter the sensor pixel 3 (photoelectric conversion region 32).

[0050] <First Semiconductor Layer> like Figure 4 and Figure 5 As shown, a first semiconductor layer 30 is disposed on the third surface S3 side of the second semiconductor layer 70, separated by a first multilayer wiring layer 40 and a second multilayer wiring layer 80. The first semiconductor layer 30 includes, for example, a p-type single-crystal silicon substrate. A photoelectric conversion region 32 is disposed in each sensor pixel 3 within the region of the first semiconductor layer 30 that overlaps with the sensor pixel array unit 2A in the plan view. Although not shown in the figure, the photoelectric conversion region 32 is separated by isolation regions disposed in the first semiconductor layer 30. Note that the number of sensor pixels 3 is not limited to... Figure 4 and Figure 5 The quantity in.

[0051] Although not shown in the figure, the photoelectric conversion region 32 includes, for example, a p-type well region and an n-type semiconductor region (photoelectric conversion unit) embedded in the well region. Figure 3 The photoelectric conversion element PD shown is constructed in the photoelectric conversion region 32 of the first semiconductor layer 30, which includes a well region and a photoelectric conversion unit. Furthermore, the photoelectric conversion region 32 may include, for example, a floating diffusion region (charge holding portion) FD including an n-type semiconductor region and a transfer transistor TR, but is not limited thereto.

[0052] like Figure 4 and Figure 5 As shown, a plurality of transistors Q1 are disposed on the first surface S1 of the first semiconductor layer 30. The transistors Q1 are disposed in the semiconductor layer 30 in the plan view and are located directly below the peripheral portion 2B. For example, the transistors Q1 are configured as follows: Figure 2 The transistor in the control circuit 8 shown. Transistor Q1 can be, for example, a metal-oxide-semiconductor field-effect transistor (MOS transistor). Figure 4 and Figure 5 Four transistors Q1 are shown as representatives of multiple transistors.

[0053] <First Multilayer Wiring> like Figure 4 and Figure 5 As shown, a first multilayer wiring layer 40 is stacked on the first surface S1 side of the first semiconductor layer 30. The first multilayer wiring layer 40 has a multilayer wiring structure in which multiple levels of wiring layers 42 are stacked with interlayer insulating films 41 separating them. Figure 4and Figure 5 While not limited to this, a three-layer wiring structure with wiring layers 42 stacked in three levels is shown for example.

[0054] The interlayer insulating film 41 is, for example, a silicon oxide film. The wiring layer 42 is formed, for example, a copper (Cu) film or a Cu alloy film with Cu as the main component, or a copper (Al) film or an Al alloy film with Al as the main component.

[0055] <Second Semiconductor Layer> like Figure 4 and Figure 5 As shown, the second semiconductor layer 70 is disposed on the first surface S1 side of the first semiconductor layer 30, separated from the second multilayer wiring layer 80 and the first multilayer wiring layer 40. The second semiconductor layer 70 includes, for example, a p-type single-crystal silicon substrate.

[0056] like Figure 4 and Figure 5 As shown, a plurality of transistors Q2 are disposed on the third surface S3 of the semiconductor layer 70. The transistors Q2 are, for example, constituting... Figure 3 The pixel transistors in the pixel circuit (readout circuit) 15 shown, or those constituting... Figure 2 The transistor in the logic circuit 13 shown. Transistor Q2 can be, for example, a MOS transistor. Figure 4 and Figure 5 Seven transistors Q2 are shown as a representation of multiple transistors.

[0057] <Second Multilayer Wiring> like Figure 4 and Figure 5 As shown, the second multilayer wiring layer 80 is stacked on the third surface S3 side of the second semiconductor layer 70. The second multilayer wiring layer 80 has a multilayer wiring structure in which multiple wiring layers 82 are stacked with interlayer insulating films 81 between them. Figure 4 and Figure 5 While not limited to this, a three-layer wiring structure with wiring layers 82 stacked in three levels is shown for example.

[0058] like Figure 4 and Figure 5 As shown, the second multilayer wiring layer 80 includes an internal electrode pad 83. The internal electrode pad 83 is disposed on the wiring layer 82 of the first layer counting from the second semiconductor layer 70 side of the second multilayer wiring layer 80.

[0059] The interlayer insulating film 81 is, for example, a silicon oxide film. The wiring layer 82 is formed, for example, a copper (Cu) film or a Cu alloy film with Cu as the main component, or a copper (Al) film or an Al alloy film with Al as the main component.

[0060] <groove, insulating film> like Figure 4 and Figure 5 As shown, the groove 91 is disposed at a position overlapping with the internal electrode pad 83 of the second multilayer wiring layer 80 in the plan view. The groove 91 then extends from the third surface S3 side of the second semiconductor layer 70 to the second multilayer wiring layer 80 and reaches the internal electrode pad 83. The groove 91 can be formed by selectively etching the second semiconductor layer 70 and the second multilayer wiring layer 80 using well-known photolithography techniques and anisotropic dry etching techniques. like Figure 1 As shown, but not limited to, for example, multiple grooves 91 are provided in the peripheral portion 2B.

[0061] like Figure 4 and Figure 5 As shown, the insulating film 92 is disposed along the inner wall side of the groove 91 and on the fourth surface S4 side of the second semiconductor layer 70. That is, the insulating film 92 is disposed on the inner wall side of the groove 91 and on the fourth surface S4 of the second semiconductor layer 70. The insulating film 92 is, for example, a silicon oxide film.

[0062] <Contact electrode, external electrode pad> like Figure 4 and Figure 5 As shown, the contact electrode 93 is disposed along the inner wall of the groove 91 through the insulating film 92, and is disposed along the inner electrode pad 83 located at the bottom of the groove 91. The contact electrode 93 is then electrically and mechanically connected to the inner electrode pad 83. The contact electrode 93 is then electrically insulated from and separated from the second semiconductor layer 70 via the insulating film 92.

[0063] like Figure 4 and Figure 5 As shown, an external electrode pad 94 is disposed on the fourth surface S4 side of the second semiconductor layer 70 via an insulating film 92. The external electrode pad 94 is integrally formed with the contact electrode 93 and is electrically connected to the contact electrode 93. That is, the external electrode pad 94 is electrically connected to the internal electrode pad 83 of the second multilayer wiring layer 80 through a groove 91. The groove 91 is a through-hole for electrically connecting the internal electrode pad 83 on the third surface S3 side of the second semiconductor layer 70 and the external electrode pad 94 on the fourth surface S4 side of the second semiconductor layer 70, and penetrates the second semiconductor layer 70 along the thickness direction (Z direction). The external electrode pad 94 is electrically insulated from and separated from the second semiconductor layer 70 via the insulating film 92.

[0064] The contact electrode 93 and the external electrode pad 94 can be formed, for example, by forming a conductive film of a certain thickness on the fourth surface S4 side of the second semiconductor layer 70 and along the inner wall of the groove 91, and then patterning the conductive film using known photolithography and anisotropic dry etching techniques. The conductive film can be, for example, a stacked film of titanium (Ti) film as a barrier film and copper (Cu) film as a seed film.

[0065] like Figure 1 As shown, but not limited to, for example, a plurality of external electrode pads 94 are provided in the peripheral portion 2B of the semiconductor chip 2.

[0066] Solder resist like Figure 4 and Figure 5 As shown, the solder resist 95 is disposed within the groove 91 and covers the contact electrode 93, and is configured to cover the fourth surface S4 of the second semiconductor layer 70. That is, the solder resist 95 is disposed within the groove 91 and on the fourth surface S4 of the second semiconductor layer 70.

[0067] The main purpose of providing the solder mask 95 is to protect the contact electrodes 93 and wiring (not shown) located on the fourth surface S4 side of the second semiconductor layer 70. Then, the solder mask 95 is provided with an opening 95a to expose the external electrode pads 94.

[0068] Connecting components such as solder bumps or bonding traces are connected to external electrode pads 94 through openings 95a in the solder mask 95.

[0069] <Bonding Layer> like Figure 5 As shown, the bonding layer 47 on the first stack 20 side is disposed on the bonding surface side of the first multilayer wiring layer 40, which is located on the side opposite to the first semiconductor layer 30 side, to cover the warpage suppression film 46. The bonding layer 46 is disposed on the sensor pixel array unit 2A and the peripheral portion 2B of the semiconductor chip 2, and is disposed over a wide area to cover the entire area of ​​the first multilayer wiring layer 40 in the plan view.

[0070] like Figure 5 As shown, the bonding layer 87 on the second stack 20 side is disposed on the bonding surface side of the second multilayer wiring layer 80, which is located on the side opposite to the second semiconductor layer 70 side, to cover the warpage suppression film 86. The bonding layer 87 is disposed on the sensor pixel array unit 2A and the peripheral portion 2B of the semiconductor chip 2, and is disposed over a wide area to cover the entire area of ​​the second multilayer wiring layer 80 in the plan view.

[0071] The surface of bonding layer 47 serves as the bonding surface 20a of the first stack 20. On the other hand, bonding layer 87 serves as the bonding surface 60a of the second stack 60. Then, bonding layer 47 of the first stack 20 and bonding layer 87 of the second stack 60 are bonded together. Then, by bonding bonding layer 47 of the first stack 20 and bonding layer 87 of the second stack 60 together, the first stack 20 and the second stack 60 are bonded side by side in their respective thickness directions (Z direction).

[0072] <Plasma Bonding Methods> The bonding of the bonding layer 47 of the first stack 20 and the bonding layer 87 of the second stack 60 can be performed, for example, by plasma bonding.

[0073] In the plasma bonding method, silanol groups are formed by plasma irradiation of a silicon oxide layer, which serves as the bonding layer. Then, the surfaces with the silanol groups are placed face to face and the stack is pressed together to achieve bonding via van der Waals forces. Subsequently, to further enhance the bonding strength at the bonding interface, a heat treatment at 400°C for 60 minutes is performed to induce a dehydration condensation reaction in the silanol groups. By controlling the bonding layers of the stack at this molecular level, the stacks can be bonded together. The bonding between the bonding layer 47 of the first stack 20 and the bonding layer 87 of the second stack 60 is performed in a wafer state.

[0074] <Warpage Inhibition Membrane> like Figure 5 As shown, the warpage suppression film 46 is disposed on the side of the first multilayer wiring layer 40 opposite to the side of the first semiconductor layer 30 and is covered by the bonding layer 47. The warpage suppression film 46 is disposed on the sensor pixel array unit 2A and the peripheral portion 2B of the semiconductor chip 2, and is disposed over a wide area so as to cover the entire area of ​​the first multilayer wiring layer 40 in a plan view.

[0075] The warpage suppression film 46 suppresses warpage of a first stack 20 composed of a first semiconductor layer 30 and a first multilayer wiring layer 40 having different coefficients of thermal expansion, and the warpage suppression film 46 includes a layer having internal stresses opposite to the warpage stresses of the first stack 20. The warpage suppression film 46 can be, for example, a material that can be formed by plasma CVD (e.g., SiN, SiO2, SiOC, SiC, SiCN, FSG, or FTEOS), or a material that can be formed by coating (e.g., an inductive material or SOG). In particular, in films formed by plasma CVD, the internal stresses can be controlled by changing conditions such as the pressure and RF power within the CVD equipment chamber. Therefore, it is preferable to use a material film formed by plasma CVD as the warpage suppression film 46. In a first embodiment, for example, a silicon nitride (SiN) film is used as the warpage suppression film 46. like Figure 5 As shown, a warpage suppression film 86 is disposed on the side of the second multilayer wiring layer 80 opposite to the side of the second semiconductor layer 70, and is covered by a bonding layer 87. The warpage suppression film 86 is disposed on the pixel array unit 2A and the peripheral portion 2B of the semiconductor chip 2, and is disposed over a wide area so as to cover the entire area of ​​the second multilayer wiring layer 80 in a plan view.

[0076] The warpage suppression film 86 suppresses warpage of the second stack 60, which is formed by stacking a second semiconductor layer 70 and a second multilayer wiring layer 80 with different coefficients of thermal expansion. The warpage suppression film 86 includes a layer having internal stresses opposite to the warpage stress of the second stack 60. The warpage suppression film 46 may have a similar structure to the warpage suppression film 46 described above for suppressing warpage of the first stack 20. In a first embodiment, for example, a silicon nitride (SiN) film is used as the warpage suppression film 86.

[0077] like Figure 5 As shown, each of the warpage suppression films 86 and 46 is disposed between the second multilayer wiring layer 80 and the first multilayer wiring layer 40. That is, the solid-state imaging device 1A according to the first embodiment includes a second semiconductor layer 70, a second multilayer wiring layer 80 disposed on the third surface S3 side of the second semiconductor layer 70, a warpage suppression film 86 disposed on the side of the second multilayer wiring layer 80 opposite to the second semiconductor layer 70 side, and a groove 91 that overlaps with the warpage suppression film 86 in the plan view and extends from the fourth surface S4 side of the second semiconductor layer 70 to the second multilayer wiring layer.

[0078] <Overlapping region of the warp suppression membrane> like Figure 6 and Figure 7As shown, the warpage suppression film 86 has an opening 86a1 in the overlapping region 86a that overlaps with the groove 91 in the plan view. The opening 86a1 may be provided, for example, scattered, but is not limited thereto. In this case, the overlapping region 86a of the warpage suppression film 86 is a lattice-like planar pattern including the opening 86a1. like Figure 6 As shown, the opening 86a1, for example, penetrates the warpage suppression membrane 86. Then, as... Figure 7 As shown, the planar shape of the opening 46a1 is, for example, a rectangular shape.

[0079] like Figure 6 As shown, similar to the warpage suppression film 86 described above, the warpage suppression film 46 also has openings 46a1 in the overlapping region 46a that overlaps with the groove 91 in the plan view. Similar to the openings 86a1 of the warpage suppression film 86, the openings 46a1 are also, for example, scattered. Furthermore, the overlapping region 46a of the warpage suppression film 46 is also a grid-like planar pattern including the openings 46a1. Furthermore, similar to the openings 86a1 described above, the openings 46a1 of the warpage suppression film 46 also, for example, penetrate the warpage suppression film 46, and the planar shape of the openings 46a1 is, for example, rectangular.

[0080] <<Main Effects of the First Embodiment>> Next, we will refer to Figure 8 and Figure 9 The main effects of the first embodiment are explained.

[0081] Figure 8 This is a schematic longitudinal cross-sectional view showing the deformation in the overlapping area where the interface R1 between the first stack 20 and the second stack 60 overlaps with the groove 91 in a conventional solid-state imaging device.

[0082] Figure 9 This is a schematic longitudinal cross-sectional view showing the deformation in the overlapping region where the interface between the first stack 20 and the second stack 60 overlaps with the groove 91 in the solid-state imaging apparatus 1A according to the first embodiment.

[0083] like Figure 8 As shown, in a conventional solid-state imaging device, in a planar view, the overlapping regions 86a and 46a of the warp suppression films 86 and 46 that overlap with the groove 91 of the second semiconductor layer 70 are in a solid film state. That is, in a planar view, the entire groove 91 is covered by the warp suppression films 86 and 46. Therefore, the stress caused by the warp suppression films 86 and 46 may be locally concentrated around the groove 91, and the portion of the second multilayer wiring layer 80 that overlaps with the groove 91 of the second semiconductor layer 70 may deform in the planar view (warp amount A). Deformation of the second multilayer wiring layer 80 can cause the wiring and internal electrode pads 83 of the second multilayer wiring layer 80 to warp or peel off, resulting in decreased reliability.

[0084] On the other hand, such as Figure 9 As shown, in the solid-state imaging apparatus 1A of the first embodiment, the warpage suppression films 86 and 46 have openings 86a1 and 46a1 in the overlapping regions 86a and 46a that overlap with the groove 91 of the second semiconductor layer 70 in a plan view. Therefore, the phenomenon of localized stress concentration around the groove 91 caused by the warpage suppression films 86 and 46 can be alleviated, and the deformation (warpage amount A) of the portion of the second multilayer wiring layer 80 that overlaps with the groove 91 of the second semiconductor layer 70 in a plan view can be suppressed.

[0085] Therefore, it is possible to suppress the warping or peeling of the wiring of the multilayer wiring layer 80 and the internal electrode pads 83 caused by local deformation of the second multilayer wiring layer 80.

[0086] Therefore, the reliability of the solid-state imaging device 1A according to the first embodiment can be further improved.

[0087] <<Modifications of the First Embodiment>> <Variation Example 1-1> In the first embodiment described above, as Figure 7 As shown, the planar shape of the openings 86a1 and 46a1 of the warpage suppression membranes 86 and 46 is rectangular, but this technology is not limited to rectangular shapes. For example, such as Figure 10 As shown, the openings 86a1 and 46a1 of the warpage suppression films 86 and 46 can also be formed into a circular planar shape. In this case, the same effect as the first embodiment described above can be obtained.

[0088] <Variations 1-2> Furthermore, in the first embodiment described above, as Figure 7 The diagram illustrates the case where openings 86a1 and 46a1 are distributed in the overlapping regions 86a and 46a of the warp suppression membranes 86 and 46. However, this technology is not limited to the configuration where openings 86a1 and 46a1 are distributed in the overlapping regions 86a and 46a of the warp suppression membranes 86 and 46. For example, such as Figure 11 As shown, an opening 86a1, 46a1 can also be provided in the overlapping regions 86a, 46a of the warp suppression films 86, 46. In this case, the same effect as the first embodiment described above can be obtained.

[0089] <Variations 1-3> In the first embodiment described above, as Figure 4As shown, a groove 91 is provided in the second semiconductor layer 70 that overlaps with the peripheral portion 2B of the semiconductor chip 2 in the plan view, and openings 86a1 and 46a1 are provided in the overlapping regions 86a and 46a of the warp suppression films 86 and 46 that overlap with the groove 91. However, the present technology is not limited to the groove 91 of the first embodiment described above.

[0090] For example, such as Figure 12 As shown, a groove 91 can be provided in the second semiconductor layer 70 that overlaps with the sensor pixel array unit 2A of the semiconductor chip 2 in the planar view, and openings 86a1 and 46a1 can be provided in the overlapping regions 86a and 46a of the warp suppression films 86 and 46 that overlap with the groove 91. In this case, similar effects to the first embodiment described above can also be obtained.

[0091] Furthermore, since the deformation (warpage A) of the portion of the second multilayer wiring layer 80 that overlaps with the groove 91 directly below the sensor pixel array unit 2A in the planar view can be suppressed, the warpage of the internal electrode pad 83 can be suppressed. Therefore, the phenomenon that the light reflected from the internal electrode pad 83 due to the warpage of the internal electrode pad 83 is concentrated and presented as a projected image can be suppressed, and the image quality can be further improved.

[0092] <Variations 1-4> Furthermore, in the first embodiment described above, as Figure 6 The illustration shows a case where warpage suppression films 86 and 46 are provided on both the first stack 20 and the second stack 60. However, this technology can also be applied to cases where a warpage suppression film is provided on at least one of the first stack 20 and the second stack 60. Figure 13 The diagram shows a case where a warpage suppression film 86 is provided on the second stack 60, which is one of the first stack 20 and the second stack 60. An opening 86a is then provided in the overlapping region 86a of the warpage suppression film 86 on the second stack 60 side.

[0093] [Second Embodiment] like Figure 14 and Figure 15 As shown, the solid-state imaging device 1B according to the second embodiment of the present technology is basically similar to the solid-state imaging device 1A according to the first embodiment described above, except that the structure of the external electrode pads and grooves is different.

[0094] In other words, such as Figure 5 As shown, in the first embodiment described above, the groove 91 is disposed in the second stack 60 and overlaps with the internal electrode pad 83 of the second multilayer wiring layer 80 in the plan view, and the openings 86a1 and 46a1 are disposed in the overlapping regions 86a and 46a of the warp suppression films 86 and 46 and overlap with the groove 91.

[0095] On the other hand, such as Figure 15 As shown, in the second embodiment, the groove 56 is disposed in the first stack 20 and overlaps with the internal electrode pad 44 of the first multilayer wiring layer 40 in the plan view, and the openings 46b1 and 86b1 are disposed in the overlapping regions 46b and 86b of the warp suppression films 46 and 86 and overlap with the groove 56.

[0096] like Figure 15 As shown, internal electrode pads 44 are disposed in wiring layer 42, for example, the third layer counting from the first semiconductor layer 30 side of the first multilayer wiring layer 40. Internal electrode pads 44 serve as input / output terminals for electrically connecting the semiconductor chip 2 to an external device. Connecting components such as solder bumps or bonding wires are then connected to the internal electrode pads 44.

[0097] The groove 56 extends from the second surface S2 side of the first semiconductor layer 30 toward the first multilayer wiring layer 40 and reaches the internal electrode pad 44 of the first multilayer wiring layer 40. That is, the groove 56 penetrates the first semiconductor layer 30 on the first surface S1 and the second surface S2 and reaches the internal electrode pad 44 of the first multilayer wiring layer 40.

[0098] Similar to the overlapping regions 46a and 86b of the first embodiment described above, the overlapping regions 46b and 86b of the warpage suppression films 46 and 86 are, for example, a lattice-like planar pattern including openings 46b1 and 86b1.

[0099] The solid-state imaging device 1B according to the second embodiment can also produce effects similar to those produced by the solid-state imaging device 1A according to the first embodiment described above.

[0100] [Third Embodiment] <<Examples of Electronic Device Applications>> This technology (the technology disclosed herein) can be applied to various electronic devices, such as imaging devices like digital still cameras or digital video cameras, mobile phones with imaging capabilities, or other devices with imaging capabilities.

[0101] Figure 16 This is a diagram illustrating a schematic construction of an electronic device (e.g., a camera) according to a third embodiment of the present technology.

[0102] like Figure 16 As shown, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is an embodiment in which the solid-state imaging device 1A according to the first embodiment of the present technology is used as an electronic device (e.g., a camera) as the solid-state imaging device 101.

[0103] Optical lens 102 images the image light (incident light 106) from the subject onto the imaging surface of solid-state imaging device 101. Therefore, charge accumulates in solid-state imaging device 101 for a specific period of time. Shutter device 103 controls the illumination and blocking times of solid-state imaging device 101. Drive circuit 104 provides drive signals to control the transmission operation of solid-state imaging device 101 and the shutter operation of shutter device 103. Based on the drive signals (timing signals) provided by drive circuit 104, solid-state imaging device 101 performs charge transfer. Signal processing circuit 105 performs various signal processing on the signals (pixel signals) output by solid-state imaging device 101. The signal-processed video signal is stored in a storage medium such as a memory or output to a monitor.

[0104] This configuration can further improve the reliability of the solid-state imaging device 101, and thus also further improve the reliability of the electronic device 100 according to the third embodiment.

[0105] Note that the electronic device 100 applicable to the solid-state imaging device according to the above embodiments is not limited to a camera, and the solid-state imaging device can also be applied to other electronic devices. For example, the solid-state imaging device can be applied to imaging devices such as camera modules of mobile devices (e.g., mobile phones or tablet terminals).

[0106] Furthermore, this technology can be applied to any light detection device, including not only the solid-state imaging devices described above as image sensors, but also range sensors (also known as time-of-flight (ToF) sensors) used for measuring distance. A range sensor is a sensor that emits illumination light towards an object, detects the reflected light from the object's surface, and calculates the distance to the object based on the time of flight from the emission of the illumination light to the receipt of the reflected light. This range sensor can also employ the aforementioned pixel transistors.

[0107] Note that this technology can have the following configuration. (1) A light detection device, comprising: A semiconductor layer having a first surface and a second surface that are opposite to each other in the thickness direction; A multilayer wiring layer is disposed on the first surface side of the semiconductor layer; A warpage suppression film is disposed on the side of the multilayer wiring layer opposite to the semiconductor layer side; and A groove, which overlaps with the warpage suppression film in a plan view, and extends from the second surface side of the semiconductor layer to the multilayer wiring layer, wherein... The warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in a plan view. (2) The optical detection device according to (1), wherein the openings are distributed. (3) The photodetector according to (1) or (2), wherein the overlapping region of the warpage suppression film is a lattice-like planar pattern including the opening. (4) The light detection device according to any one of (1) to (3), further comprising: A contact electrode, disposed in the groove and connected to the wiring layer of the multilayer wiring layer; and An external electrode pad is disposed on the second surface side of the semiconductor layer and connected to the contact electrode. (5) The optical detection device according to (4), wherein, The multilayer wiring layer includes internal electrode pads located between the warp suppression film and the groove, and The contact electrode is connected to the internal electrode pad. (6) The optical detection device according to (4), wherein, The contact electrode is disposed along the inner wall of the groove, and A solder resist film covering the contact electrode is provided in the groove. (7) The photodetector according to any one of (1) to (6), wherein the warpage suppression film suppresses the warpage of the semiconductor layer and the wiring layer. (8) A light detection device, comprising: A first semiconductor layer has a first surface and a second surface opposite to each other, and is provided with a photoelectric conversion unit that performs photoelectric conversion on light incident from the second surface side; A first multilayer wiring layer is disposed on the first surface side of the first semiconductor layer; The second semiconductor layer has a third surface and a fourth surface opposite to each other, and transistors are disposed thereon; A second multilayer wiring layer is disposed on the third surface side of the second semiconductor layer and overlaps with the first multilayer wiring layer; A warpage suppression film disposed between the first multilayer wiring layer and the second multilayer wiring layer; and A groove, which overlaps with the warpage suppression film in a plan view, and extends from the fourth surface side of the second semiconductor layer to the second multilayer wiring layer, wherein, The warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in a plan view. (9) The light detection device according to (8), wherein the openings are distributed. (10) The photodetector according to (8) or (9), wherein the overlapping region of the warpage suppression film is a lattice-like planar pattern including the opening. (11) The optical detection device according to (8) further includes: A contact electrode, disposed in the groove and connected to the wiring layer of the multilayer wiring layer; and An external electrode pad is disposed on the second surface side of the semiconductor layer and connected to the contact electrode. (12) The optical detection device according to (11), wherein, The second multilayer wiring layer includes internal electrode pads located between the warp suppression film and the groove, and The contact electrode is connected to the internal electrode pad. (13) The optical detection device according to (11), wherein, The contact electrode is disposed along the inner wall of the groove, and A solder resist film covering the contact electrode is provided in the groove. (14) The optical detection device according to any one of (8) to (12), wherein the warpage suppression film suppresses the warpage of the semiconductor layer and the wiring layer. (15) An electronic device comprising: Optical detection device; An optical lens that forms an image of the light from the subject onto the imaging surface of the light detection device; and The signal processing circuit processes the signal output from the photodetector, wherein... The optical detection device includes: A semiconductor layer having a first surface and a second surface that are opposite to each other in the thickness direction; A multilayer wiring layer is disposed on the first surface side of the semiconductor layer; A warpage suppression film is disposed on the side of the multilayer wiring layer opposite to the semiconductor layer side; and A groove, which overlaps with the warpage suppression film in a plan view, and extends from the second surface side of the semiconductor layer to the multilayer wiring layer, wherein... The warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in a plan view.

[0108] The scope of this technology is not limited to the exemplary embodiments shown in the accompanying drawings and described above, but also includes all embodiments that produce effects equivalent to those intended by this technology. Furthermore, the scope of this technology is not limited to the combination of inventive features as defined in the claims, but can be defined by any combination of specific features from all disclosed features. List of reference numerals

[0109] 1A Solid-State Imaging Device 2 Semiconductor chips 2A sensor pixel array unit 2B Peripheral Department 3 sensor pixels 4 Vertical drive circuit 5-column signal processing circuits 6. Horizontal drive circuit 7 Output Circuit 8. Control Circuit 10-pixel drive line 11 Vertical signal line 12 Horizontal Signal Lines 13 Logic Circuits 15-pixel circuit 20 First stack 30 First semiconductor layer 32 Photoelectric conversion region 34 Photoelectric conversion units 40 First Multilayer Wiring Layer 41 interlayer insulating film 42 Wiring Layer 44 Internal electrode pads 46 Warpage Inhibition Membrane Overlapping areas of 46a and 46b 46a1, 46b1 opening 47 Bonding Layer 50 Concentrating Layers 51 Planarization film 53 Optical Filters 54 on-chip lenses 56 Grooves 60 Second stack 70 Second semiconductor layer 80 Second Multilayer Wiring Layer 81 interlayer insulating film 82 Wiring Layer 83 Internal electrode pads 86 Warpage Inhibition Membrane Overlapping areas of 86a and 86b 86a1, 86b1 opening 87 Bonding Layer 91 Groove 92 Insulating film 93 Contact Electrode 94 External electrode pads 95 Solder mask 100 Electronic devices 101 Solid-State Imaging Device 102 Optical System (Optical Lens) 103 Shutter mechanism 104 drive circuit 105 Signal Processing Circuit S1 First Surface S2 Second Surface S3 Third Surface S4 Fourth Surface Q1 and Q2 transistors

Claims

1. A light detection device, comprising: A semiconductor layer having a first surface and a second surface that are opposite to each other in the thickness direction; A multilayer wiring layer is disposed on the first surface side of the semiconductor layer; A warpage suppression film is disposed on the side of the multilayer wiring layer opposite to the semiconductor layer side; as well as A groove, which overlaps with the warpage suppression film in a plan view, and extends from the second surface side of the semiconductor layer to the multilayer wiring layer, wherein... The warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in a plan view.

2. The optical detection device according to claim 1, wherein, The openings are scattered.

3. The optical detection device according to claim 1, wherein, The overlapping area of ​​the warpage suppression film is a lattice-like planar pattern including the opening.

4. The optical detection device according to claim 1, further comprising: A contact electrode is disposed in the groove and connected to the wiring layer of the multilayer wiring layer; as well as An external electrode pad is disposed on the second surface side of the semiconductor layer and connected to the contact electrode.

5. The optical detection device according to claim 4, wherein, The multilayer wiring layer includes internal electrode pads located between the warp suppression film and the groove, and The contact electrode is connected to the internal electrode pad.

6. The optical detection device according to claim 4, wherein, The contact electrode is disposed along the inner wall of the groove, and A solder resist film covering the contact electrode is provided in the groove.

7. The optical detection device according to claim 1, wherein, The warpage suppression film suppresses the warpage of the semiconductor layer and the wiring layer.

8. A light detection device, comprising: A first semiconductor layer has a first surface and a second surface opposite to each other, and is provided with a photoelectric conversion unit that performs photoelectric conversion on light incident from the second surface side; A first multilayer wiring layer is disposed on the first surface side of the first semiconductor layer; The second semiconductor layer has a third surface and a fourth surface opposite to each other, and transistors are disposed thereon; A second multilayer wiring layer is disposed on the third surface side of the second semiconductor layer and overlaps with the first multilayer wiring layer; A warpage suppression film is disposed between the first multilayer wiring layer and the second multilayer wiring layer; as well as A groove, which overlaps with the warpage suppression film in a plan view, and extends from the fourth surface side of the second semiconductor layer to the second multilayer wiring layer, wherein, The warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in a plan view.

9. The optical detection device according to claim 8, wherein, The openings are scattered.

10. The optical detection device according to claim 8, wherein, The overlapping area of ​​the warpage suppression film is a lattice-like planar pattern including the opening.

11. The optical detection device according to claim 8, further comprising: A contact electrode is disposed in the groove and connected to the wiring layer of the multilayer wiring layer; as well as An external electrode pad is disposed on the second surface side of the semiconductor layer and connected to the contact electrode.

12. The optical detection device according to claim 11, wherein, The second multilayer wiring layer includes internal electrode pads located between the warp suppression film and the groove, and The contact electrode is connected to the internal electrode pad.

13. The optical detection device according to claim 11, wherein, The contact electrode is disposed along the inner wall of the groove, and A solder resist film covering the contact electrode is provided in the groove.

14. The optical detection device according to claim 8, wherein, The warpage suppression film suppresses the warpage of the semiconductor layer and the wiring layer.

15. An electronic device comprising: Optical detection device; An optical lens that forms an image of the light from the subject onto the imaging surface of the light detection device; as well as The signal processing circuit processes the signal output from the photodetector, wherein... The optical detection device includes: A semiconductor layer having a first surface and a second surface that are opposite to each other in the thickness direction; A multilayer wiring layer is disposed on the first surface side of the semiconductor layer; A warpage suppression film is disposed on the side of the multilayer wiring layer opposite to the semiconductor layer side; and A groove, which overlaps with the warpage suppression film in a plan view, and extends from the second surface side of the semiconductor layer to the multilayer wiring layer, wherein... The warpage suppression membrane has an opening in the overlapping region that overlaps with the groove in a plan view.

Images