Formation method of semiconductor structure
By employing a two-step reduction process, the problem of increased resistance caused by stress migration in metal interconnect processes was solved, thereby improving the quality and reliability of the conductive layer and reducing defects such as voids.
Patent Information
- Application Number
- CN202511107937.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-11-07
AI Technical Summary
In existing technologies, stress migration failure in metal interconnect processes is related to the mismatch of thermal expansion coefficients of metal/dielectric materials, metal grain size, and defect density, leading to problems such as increased resistance or open circuits.
A two-step reduction process is adopted, with different process parameters for the first and second reduction processes. The first reduction process partially reduces the initial oxide layer, while the second reduction process completely reduces the remaining oxide layer. This avoids the introduction of reaction byproducts, improves the quality of the conductive layer, and reduces defects such as voids caused by stress migration.
It effectively reduces defects on the surface of the conductive layer, lowers the resistance caused by stress migration, and improves the quality and reliability of the conductive layer.
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Figure CN120914100A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a forming method of semiconductor structure. BACKGROUND
[0002] As a back-end-of-line process of integrated circuit manufacturing, the reliability of metal interconnection technology is always the focus of research. Stress migration (SM) is a failure mechanism driven by thermal mechanical stress, mainly characterized by the migration of metal atoms under the action of stress gradient and the formation of voids, which eventually leads to resistance increase or further circuit open.
[0003] In the metal interconnection process, the failure of stress migration is related to the coefficient of thermal expansion mismatch (CTE mismatch) of metal / dielectric materials, the grain size of metal, and the defect density (such as grain boundary vacancies), so reducing the defect density of metal can effectively reduce the failure rate of stress migration. SUMMARY
[0004] The technical problem solved by the present application is to provide a forming method of semiconductor structure to reduce the defect density of metal and reduce the failure rate of stress migration.
[0005] To solve the above technical problems, the technical scheme of the present application provides a forming method of semiconductor structure, comprising: providing a substrate; forming a first dielectric layer and an initial conductive layer in the first dielectric layer on the substrate, the first dielectric layer exposing the surface of the initial conductive layer, the surface of the initial conductive layer having an initial oxide layer; performing a first reduction treatment on the initial oxide layer to form an oxide layer; performing a second reduction treatment on the oxide layer to form a conductive layer, the process of the first reduction treatment being different from the process of the second reduction treatment.
[0006] Optionally, the process parameters of the first reduction treatment include a first gas, a first time length, and a first temperature; the process parameters of the second reduction treatment include a second gas, a second time length, and a second temperature; the type of the first gas is different from the type of the second gas, the first time length is less than the second time length, and the first temperature is the same as the second temperature.
[0007] Optionally, the first gas includes ammonia; the first time length ranges from 3 seconds to 7 seconds; and the first temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
[0008] Optionally, the second gas includes hydrogen; the second time length ranges from 5 seconds to 15 seconds; and the second temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
[0009] Optionally, forming the first dielectric layer and the initial conductive layer in the first dielectric layer on the substrate comprises: forming the first dielectric layer and a groove in the first dielectric layer on the substrate; forming a conductive material layer in the groove and on the first dielectric layer; and planarizing the conductive material layer until the surface of the first dielectric layer is exposed, thereby forming the initial conductive layer in the groove.
[0010] Optionally, the initial oxide layer is an oxide of the material of the initial conductive layer, and the material of the initial conductive layer comprises a metal, and the metal comprises one or more of a combination of copper, aluminum, tungsten, cobalt, nickel and tantalum.
[0011] Optionally, the thickness of the conductive layer is greater than the thickness of the initial conductive layer.
[0012] Optionally, the method further comprises: forming a second dielectric layer on the surface of the conductive layer and the surface of the first dielectric layer, and the material of the second dielectric layer comprises a non-oxygen-containing material, and the material of the second dielectric layer is different from the material of the first dielectric layer.
[0013] Optionally, the material of the second dielectric layer comprises silicon nitride, silicon carbide or silicon carbonitride.
[0014] Optionally, the substrate comprises a base and a device layer on the base, the device layer comprises an isolation structure and a device structure in the isolation structure, and the device structure comprises a gate structure, a diode, a triode, a capacitor, an inductor or a metal interconnection layer; the first dielectric layer is on the device layer, and the initial conductive layer is electrically connected to the device structure.
[0015] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:
[0016] The forming method of the present application, through two-step reduction treatment processes of the first reduction treatment and the second reduction treatment, the process of the first reduction treatment is different from the process of the second reduction treatment, the initial oxide layer on the surface of the initial conductive layer is completely reduced, and the first reduction treatment is not completely reduced, even if the reaction time of the second reduction treatment is longer, no additional reaction by-products will be introduced, thereby the process window of the first reduction treatment and the second reduction treatment is larger, easy to control, which is beneficial to improve the quality of the formed conductive layer, reduce the defects such as holes on the surface of the conductive layer caused by stress migration, and reduce the resistance during subsequent conduction. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 and Figure 2 is a structural schematic diagram of a semiconductor structure forming process;
[0018] Figures 3 to 6is a structural schematic diagram of a semiconductor structure forming process in the embodiment of the present application. DETAILED DESCRIPTION
[0019] As described in the background, reducing the defect density of the metal can effectively reduce the failure ratio of stress migration. Now, specific embodiments are analyzed and described.
[0020] Figure 1 and Figure 2 is a structural schematic diagram of a semiconductor structure forming process.
[0021] Please refer to Figure 1 , a substrate 100 is provided; a first dielectric layer (not shown) and a conductive layer 101 in the first dielectric layer are formed on the substrate 100, the first dielectric layer exposes the surface of the conductive layer 101, and the surface of the conductive layer 101 has an oxide layer 102; the oxide layer 102 is subjected to a reduction treatment.
[0022] The forming process of the conductive layer 101 is as follows: a first dielectric layer is formed on the substrate 100; a groove is formed in the first dielectric layer, which exposes the surface of the substrate 100; a metal material layer is formed in the groove and on the first dielectric layer; the metal material layer is planarized until the surface of the first dielectric layer is exposed, and the conductive layer 101 is formed in the groove, and the surface of the conductive layer 101 is easy to be oxidized to form the oxide layer 102.
[0023] The conductive layer 101 is used as subsequent metal interconnection, and therefore the oxide layer 102 on the surface of the conductive layer 101 needs to be removed to avoid affecting the conductive performance.
[0024] The material of the conductive layer 101 is usually copper, which has better conductive performance and lower cost. The process of the reduction treatment of the oxide layer 102 is usually a plasma treatment process containing ammonia gas. However, when the copper oxide is subjected to the reduction treatment, it is difficult to control the treatment time. If the treatment time is too short, the oxide layer 102 is not easy to be completely reduced, and if the treatment time is too long, the ammonia gas is easy to react with copper to generate copper nitride CuN x on the surface of the conductive layer 101. x The crystal grains are small and do not match the crystal lattice of copper. After the conductive layer 101 is loaded with voltage, the migration degree of metal ions is different due to the different grain sizes of the materials on the surface of the conductive layer 101 and the conductive layer 101, so that defects are easy to be generated on the surface of the conductive layer 101, stress migration occurs, and finally the resistance is increased or the circuit is further opened.
[0025] To solve the above problems, the technical scheme of the present application provides a forming method of semiconductor structure, which comprises two-step reduction treatment processes of first reduction treatment and second reduction treatment, the process of the first reduction treatment is different from the process of the second reduction treatment, so that the initial oxide layer on the surface of the initial conductive layer is completely reduced, and the first reduction treatment is not completely reduced, even if the reaction time of the second reduction treatment is longer, no additional reaction by-products will be introduced, so that the process window of the first reduction treatment and the second reduction treatment is larger, which is easy to control, and is beneficial to improve the quality of the formed conductive layer, reduce the defects such as holes on the surface of the conductive layer caused by stress migration, and reduce the resistance during subsequent conduction.
[0026] In order to make the above-mentioned objects, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.
[0027] Figures 3 to 6 is a structure schematic diagram of the semiconductor structure forming process in the embodiment of the present application.
[0028] Please refer to Figure 3 , a substrate 200 is provided; a first dielectric layer and an initial conductive layer 201 located in the first dielectric layer are formed on the substrate 200, the first dielectric layer exposes the surface of the initial conductive layer 201, and the surface of the initial conductive layer 201 has an initial oxide layer 202.
[0029] The substrate 200 comprises a base and a device layer located on the base, the device layer comprises an isolation structure and a device structure located in the isolation structure, and the device structure comprises a gate structure, a diode, a triode, a capacitor, an inductor, a metal interconnection layer, etc.; the first dielectric layer is located on the device layer, and the initial conductive layer 201 is electrically connected with the device structure.
[0030] The method for forming the first dielectric layer and the initial conductive layer 201 on the substrate 200 comprises: forming the first dielectric layer on the substrate 200; forming a groove in the first dielectric layer, the groove exposes the surface of the device structure; forming a conductive material layer in the groove and on the first dielectric layer; and planarizing the conductive material layer until the surface of the first dielectric layer is exposed, thereby forming the initial conductive layer 201 in the first dielectric layer.
[0031] The material of the first dielectric layer comprises a dielectric material, and the dielectric material comprises a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbon nitride and silicon carbon oxynitride.
[0032] In the embodiment, the material of the first dielectric layer comprises silicon oxide. The process for forming the first dielectric layer comprises a chemical vapor deposition process.
[0033] The material of the initial conductive layer 201 includes metal, which includes one or more of a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum. The initial oxide layer 202 is an oxide of the material of the initial conductive layer 201.
[0034] In this embodiment, the material of the initial conductive layer 201 includes copper. The material of the initial oxide layer 202 is an oxide of copper.
[0035] In this embodiment, the process of forming the conductive material layer includes a physical vapor deposition process.
[0036] In this embodiment, the process of planarizing the conductive material layer includes a chemical mechanical polishing process. The polishing liquid of the chemical mechanical polishing process includes benzotriazole (BTA).
[0037] In the process of planarizing the conductive material layer to form the initial conductive layer 201, the initial conductive layer 201 is easily oxidized to form the initial oxide layer 202.
[0038] In an embodiment, the substrate is a planar substrate.
[0039] In another embodiment, the substrate is a fin substrate.
[0040] In this embodiment, the material of the substrate is silicon.
[0041] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0042] Please refer to Figure 4 A first reduction treatment is performed on the initial oxide layer 201 to form an oxide layer 203 and a first reduction layer 204.
[0043] The first reduction treatment only reduces part of the initial oxide layer 201 to form the first reduction layer 204, and part of the initial oxide layer 201 is not reduced to form the oxide layer 203.
[0044] The first reduction treatment, while reducing part of the initial oxide layer 201, also removes the polishing liquid (benzotriazole) remaining during the process of forming the initial conductive layer 201 by the chemical mechanical polishing process, so as to avoid the influence of the remaining polishing liquid on the subsequent reduction process.
[0045] The material of the first reduction layer 204 is the same as that of the initial conductive layer 201.
[0046] In the embodiment, the material of the first reduction layer 204 is copper.
[0047] The reaction process of the first reduction treatment is NH3+CuO→Cu+N2+H2O.
[0048] The process parameters of the first reduction treatment include a first gas, a first time length and a first temperature.
[0049] In the embodiment, the first gas includes ammonia; the first time length ranges from 3 seconds to 7 seconds; and the first temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
[0050] Please refer to Figure 5 The second reduction treatment is performed on the oxide layer 203 to form a conductive layer, and the process of the first reduction treatment is different from that of the second reduction treatment.
[0051] The second reduction treatment reduces all of the remaining oxide layer 203 to form a second reduction layer 205, and the conductive layer includes the initial conductive layer 201, the first reduction layer 204 and the second reduction layer 205.
[0052] In the embodiment, the thickness of the conductive layer is greater than that of the initial conductive layer 201. The initial oxide layer 201 is reduced by the first reduction treatment and the second reduction treatment, so that the thickness of the conductive layer actually participating in conduction is increased, the material is not wasted, and the conduction efficiency is increased.
[0053] The material of the second reduction layer 205 is the same as that of the initial conductive layer 201.
[0054] In the embodiment, the material of the second reduction layer 205 is copper.
[0055] The reaction process of the second reduction treatment is H2+CuO→Cu.
[0056] The process parameters of the second reduction treatment include a second gas, a second time length and a second temperature.
[0057] The process of the first reduction treatment is different from that of the second reduction treatment, including that the type of the first gas is different from that of the second gas, the first time length is less than the second time length, the first temperature is the same as the second temperature, and the range of the first temperature is the same as that of the second temperature.
[0058] The first temperature is the same as the second temperature, and the range of the first temperature is the same as that of the second temperature. Then, one set of temperature system can be applied in the two reduction treatments, and the process is simplified.
[0059] In the embodiment, the second gas includes hydrogen; the second time length ranges from 5 seconds to 15 seconds; and the second temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
[0060] The first reduction process and the second reduction process are different in process, and the initial oxide layer on the surface of the initial conductive layer is completely reduced. The first reduction process is not completely reduced, and even if the reaction time of the second reduction process is longer, no additional reaction byproducts are introduced, so that the process window of the first reduction process and the second reduction process is larger, easy to control, and beneficial to improve the quality of the formed conductive layer, reduce defects such as pores on the surface of the conductive layer caused by stress migration, and reduce the resistance during subsequent conduction.
[0061] Please refer to Figure 6 The second dielectric layer 206 is formed on the surface of the conductive layer and the surface of the first dielectric layer.
[0062] In the embodiment, the material of the second dielectric layer 206 includes a material without oxygen, and the material of the second dielectric layer 206 is different from the material of the first dielectric layer. Therefore, the process of forming the second dielectric layer 206 will not oxidize the conductive layer.
[0063] The material of the second dielectric layer 206 includes silicon nitride, silicon carbide, or silicon carbon nitride.
[0064] In the embodiment, the material of the second dielectric layer 206 includes silicon nitride.
[0065] The method of forming the second dielectric layer 206 includes: forming a dielectric material layer on the surface of the conductive layer and the surface of the first dielectric layer; and planarizing the dielectric material layer to form the second dielectric layer 206 on the surface of the conductive layer and the surface of the first dielectric layer.
[0066] The process of forming the dielectric material layer includes a chemical vapor deposition process, and the reaction gas of the chemical vapor deposition process includes ammonia and tetramethylsilane.
[0067] At this point, the formed conductive layer is dense in structure, has fewer defects caused by stress migration, can improve the quality of the conductive layer, and reduce the resistance during subsequent conduction.
[0068] Next, according to the actual process requirements, an opening can also be formed in the second dielectric layer 206, and other interconnection conductive layers can be formed in the opening and on the second dielectric layer 206. The process of forming the interconnection conductive layer can continue to refer to the process of Figures 3 to 6 .
[0069] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.
Claims
1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a first dielectric layer and an initial conductive layer in the first dielectric layer on the substrate, the first dielectric layer exposing a surface of the initial conductive layer, the surface of the initial conductive layer having an initial oxide layer; performing a first reduction treatment on the initial oxide layer to form an oxide layer; performing a second reduction treatment on the oxide layer to form a conductive layer, the first reduction treatment having a different process from the second reduction treatment.
2. The method of forming a semiconductor structure of claim 1, wherein, The process parameters of the first reduction treatment include a first gas, a first time length, and a first temperature; the process parameters of the second reduction treatment include a second gas, a second time length, and a second temperature; the first gas is different from the second gas in type, the first time length is less than the second time length, and the first temperature is the same as the second temperature.
3. The method of forming a semiconductor structure of claim 2, wherein, The first gas includes ammonia; the first time length ranges from 3 seconds to 7 seconds; and the first temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
4. The method of forming a semiconductor structure of claim 2, wherein, The second gas includes hydrogen; the second time length ranges from 5 seconds to 15 seconds; and the second temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
5. The method of forming a semiconductor structure of claim 1, wherein, The method of forming a first dielectric layer and an initial conductive layer in the first dielectric layer on a substrate comprises: forming a first dielectric layer and a groove in the first dielectric layer on the substrate; forming a conductive material layer in the groove and on the first dielectric layer; and planarizing the conductive material layer until the surface of the first dielectric layer is exposed, thereby forming the initial conductive layer in the groove.
6. The method of forming a semiconductor structure of claim 1, wherein, The initial oxide layer is an oxide of the material of the initial conductive layer, and the material of the initial conductive layer includes a metal, which includes one or more of a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.
7. The method of forming a semiconductor structure of claim 1, wherein, The thickness of the conductive layer is greater than the thickness of the initial conductive layer.
8. The method of forming a semiconductor structure of claim 1, wherein, The method further comprises: forming a second dielectric layer on the surface of the conductive layer and the surface of the first dielectric layer, the material of the second dielectric layer including an oxygen-free material, and the material of the second dielectric layer being different from the material of the first dielectric layer.
9. The method of forming a semiconductor structure of claim 8, wherein, The material of the second dielectric layer includes silicon nitride, silicon carbide, or silicon carbon nitride.
10. The method of forming a semiconductor structure of claim 1, wherein, The substrate includes a base and a device layer on the base, the device layer including an isolation structure and a device structure in the isolation structure, the device structure including a gate structure, a diode, a triode, a capacitor, an inductor, or a metal interconnection layer; the first dielectric layer is on the device layer, and the initial conductive layer is electrically connected to the device structure.