An interleaved qr flyback controller

Abstract

The application discloses a kind of staggered QR flyback controllers in the technical field of semiconductor, including control IC, control IC includes power supply pin, phase switch, resonant signal detection pin, first drive channel and second drive channel, the first end of 180 ° phase switch is connected to drive signal, the output end of first drive channel and second drive channel is short-circuited, resonant signal detection pin is used to make the power tube of first drive channel of quasi-resonant control open by zero-crossing detection, second drive channel includes second CS foot, and the same phase input end of second overcurrent protection comparator and second comparator is connected.The application can ensure that the converter works in QR control mode by setting phase switch, and staggered QR flyback controller can be formed by setting two working channels with 180 ° difference, effectively improve power, make up current technical blank.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to an interleaved QR flyback controller. BACKGROUND

[0002] An important development direction of modern switching power supply is high frequency, so that the volume and weight of the switching power supply can be greatly reduced, and the power density of the switching power supply is improved. Moreover, with the increase of switching frequency, the audio noise of the switching power supply can be reduced, and the dynamic response can be improved. However, with the high frequency of the switching power supply, the switching loss becomes more and more prominent, and the switching loss must be reduced. The soft switching technology is an important method to reduce the switching damage. Soft switching refers to zero voltage (Zero Voltage Switching, ZVS) or zero current (Zero Current Switching, ZCS) conduction, which uses the principle of quasi-resonance to make the drain voltage of the power tube in the switching power supply zero, so that the power tube is turned on, or the current is zero, so that the power tube is turned off, and the switching loss is reduced, so as to meet the high frequency application of the switching power supply.

[0003] Among them, since the flyback converter has the advantages of input and output electrical isolation, simple circuit structure, low cost and the like, it is widely used in various portable electronic products such as mobile phones, notebook computers and the like. Quasi-resonant technology is widely used in flyback converters due to its strong advantages in high frequency applications. It is usually a quasi-resonant (Quasi-Resonant, QR) flyback converter. The QR flyback converter triggers the power tube to conduct at the bottom of the power tube drain-source voltage, thereby reducing the switching loss of the power tube and improving the system efficiency. QR flyback converter is characterized by detecting the bottom of the power tube drain-source voltage to trigger the power tube to conduct, so that the converter works in variable frequency mode.

[0004] Figure 1It is a typical QR flyback converter application diagram, including control IC and peripheral components, the control IC includes a first drive circuit, the peripheral components include: a starting network composed of a first resistor R1 and a first capacitor C1, wherein the starting network supplies power to the power supply pin VCC of the IC; T is a transformer, Lp, Ls, La are the primary winding, secondary winding and auxiliary winding respectively; MOSFET is a power tube; R4 is a sampling resistor; D1 is a power diode; R2, R3 constitute an auxiliary winding sampling network; D2 is a freewheeling diode; Cout is an output capacitor; R5, R6 constitute an output sampling network; IsoAmp is an isolation operational amplifier; C2 is the COMP ground capacitor. The control IC includes a power supply pin VCC, which generates a low-voltage power supply REF through a Regulator module; the COMP pin is pulled up to the internal power supply REF through a 5K resistor, and one-third of the voltage after subtracting 1V is sent to the negative input terminal of the PWM comparator; The first drive circuit includes a first CS pin, which is sent to the positive input terminal of the PWM comparator and the positive input terminal of the overcurrent protection comparator (OCP) at the same time; The ZT detection pin samples the signal of the auxiliary winding, which is compared with 50mV through the zero-crossing comparator (ZCD Detect) for detecting the trough of resonance; The DT Timer module is a dead time control module, which determines the dead time, and the dead time is strongly related to the COMP voltage. This module and the zero-crossing comparator (ZCD Detect) jointly control the conduction of the power tube.

[0005] Figure 1The working principle is as follows: after the system is powered on and stabilized, the COMP pin is basically stable at a certain voltage value. At a certain moment, the power tube is turned on, the transformer T is in the excitation stage, and the voltage of the sampling resistor R4 is ramped up. When the voltage of R4 (the voltage of the first CS pin) rises to a certain value (converted from the COMP voltage), the PWM comparator output becomes high, and the control power tube is turned off. Obviously, the high and low of the COMP voltage determines the size of the power tube conduction time. At this time, the energy stored in the primary winding of the transformer is transmitted to the secondary winding, and the secondary winding starts to discharge and provides power for the output through the freewheeling diode D2. The voltage (proportional to the output voltage VOUT) coupled by the auxiliary winding supplies power for the VCC of the chip. When the secondary winding discharge current drops to zero, due to the influence of the transformer leakage inductance and the parasitic capacitance of the power tube MOSFET, the auxiliary winding voltage starts to resonate, and the chip detects the resonance signal through the resonance signal detection pin ZT. Once the ZCD Detect comparator output is high, the dead time is determined by the DT Timer, and once the dead time reaches the requirement of the module and the ZCD Detect comparator output is high, the power tube is turned on again. The cycle is repeated. It should be noted that the dead time controlled by the DT Timer module is determined by the COMP voltage, and the COMP voltage and the dead time have a one-to-one correspondence. The dead time can be as low as 0us, that is, the system enters the BCM working mode. From the perspective of loop feedback, the heavier the load, the lower the output voltage VOUT, the higher the COMP voltage, the longer the conduction time, and the smaller the dead time. Even in the BCM working mode, more energy is transmitted to the output, and the output voltage VOUT can be increased, so as to form a dynamic balance, and the output voltage VOUT can be stabilized at the set voltage.

[0006] Figure 2 The existing QR flyback converter waveform diagram is shown. Under heavy load, the conduction time is long, the dead time is short (even none), and the Drain voltage of the MOSFET is opened at the first resonance valley bottom to start the next cycle. Under light load, the conduction time is short, the dead time is long, and when the dead time meets the value determined by the COMP and starts the next cycle at the Drain voltage valley bottom. However, the existing QR flyback converter is limited by the topology structure, and the power cannot be greatly increased. SUMMARY

[0007] The purpose of the present application is to provide an interleaved QR flyback controller which can ensure that the converter works in the QR control mode, and the two working channels are 180° apart, so as to form an interleaved QR flyback controller and effectively improve the power.

[0008] To achieve the above purpose, the present application provides the following technical solutions:

[0009] The staggered QR flyback controller comprises a control IC and a peripheral circuit, the control IC comprises a power supply pin VCC, a 180-degree phase switch, a resonance signal detection pin ZT, a first drive channel and a second drive channel, a first end of the 180-degree phase switch is connected to a drive signal DRV, output ends of the first drive channel and the second drive channel are short-circuited, the resonance signal detection pin ZT is used for enabling a power tube of the first drive channel to be turned on by quasi-resonance control through zero-crossing detection, the second drive channel comprises a second CS pin CS2, the second CS pin is connected to a same-phase input end of a second over-current protection comparator OCP2 and a second comparator PWM2, output ends of the second over-current protection comparator OCP2 and the second comparator PWM2 are respectively connected to first and second input ends of an OR gate, an output end of the OR gate is connected to a reset end R of a second RS flip-flop, a set end S of the second RS flip-flop is connected to a second end of the 180-degree phase switch, an output end of the second RS flip-flop is connected to an input end of a first driver, an output end of the first driver serves as an output end OUT2 of the second drive channel, and the peripheral circuit comprises a start-up network, one end of the start-up network is connected to the power supply pin VCC.

[0010] As a further scheme of the present application, the first drive channel is a single-channel QR flyback controller.

[0011] As a further scheme of the present application, the start-up network comprises a first resistor R1 and a first capacitor C1, a first end of the first resistor R1 is connected to an input signal Vin, a primary winding of a first transformer T1 and a primary winding of a second transformer T2, a second end of the first resistor R1 is connected to a negative electrode of a first diode D1, a positive electrode of the first diode D1 is connected to an auxiliary winding La1 and a first end of a second resistor R2, a second end of the second resistor R2 is connected to a first end of a third resistor R3 and a resonance signal detection pin ZT of the control IC, and a second end of the third resistor R3 is grounded, wherein the primary winding of the first transformer T1 is a first primary winding Lp1, and the primary winding of the second transformer T2 is a second primary winding Lp2.

[0012] As a further scheme of the present application, the first transformer T1 comprises a first secondary winding Ls1, and the second transformer T2 comprises a second secondary winding Ls2, one end of the first secondary winding Ls1 and one end of the second secondary winding Ls2 are respectively connected to a first end of an output capacitor Cout after being connected in series with a diode, the first end of the output capacitor Cout is connected to an output voltage VOUT and a first end of a fifth resistor R5, a second end of the output capacitor Cout is grounded, a second end of the fifth resistor R5 is connected to a first end of an isolation operational amplifier IsoAmp and a sixth resistor R6, a second end of the isolation operational amplifier IsoAmp is connected to a first end of a second capacitor C2, and a second end of the second capacitor C2 and a second end of the sixth resistor R6 are grounded.

[0013] As a further scheme of the present application: the 180° phase switch comprises a monostable trigger, and an output end of the monostable trigger is connected to the delay circuit.

[0014] As a further scheme of the present application: the monostable trigger comprises a first inverter INV1, an input end of the first inverter INV1 is connected to a first input end of a NAND gate and a driving signal, an output end of the first inverter INV1 is connected to an input end of a second inverter INV2 and a first end of a third capacitor C3, a second end of the third capacitor C3 is grounded, an output end of the second inverter INV2 is connected to an input end of a third inverter INV3, an output end of the third inverter INV3 is connected to a second input end of the NAND gate, an output end of the NAND gate is connected to an input end of a fourth inverter INV4, and an output end of the fourth inverter INV4 is connected to an input end of the delay circuit.

[0015] As a further scheme of the present application: the delay circuit comprises a fifth inverter, an input end of the fifth inverter is connected to an output end of the fourth inverter INV4, and an output end of the fifth inverter is connected to a first end of a fourth capacitor C4 and an input end of a sixth inverter INV6, and a second end of the fourth capacitor C4 is grounded.

[0016] As a further scheme of the present application: the 180° phase switch further comprises a first MOS tube N1, a gate of the first MOS tube N1 is connected to an output end of a seventh inverter INV7, an input end of the seventh inverter INV7 is connected to an output end of the fourth inverter INV4, a drain of the first MOS tube N1 is connected to a first current source I1, a source of the first MOS tube N1 is connected to a first end of a fifth capacitor C1', a drain of a second MOS tube N2 and a source of a third MOS tube N3, a gate of the third MOS tube N3 is connected to an output end of the fourth inverter INV4, a drain of the third MOS tube N3 is connected to a first end of a sixth capacitor C2' and a second current source I2, a first end of the sixth capacitor C2' and a second end of the second current source I2 are grounded, the first end of the sixth capacitor C2' is connected to a third comparator CMP, a source of the second MOS tube N2 is grounded, a gate of the second MOS tube N2 is connected to an output end of the sixth inverter INV6, and a second end of the fifth capacitor C1' is grounded.

[0017] Compared with the prior art, the present application has the following beneficial effects:

[0018] The present application can ensure that the converter works in the QR control mode by setting the phase switch, and can form an interleaved QR flyback controller by setting two working channels with a difference of 180°, effectively improving the power and making up for the current technical blank. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is an application schematic diagram of the existing QR flyback converter.

[0020] Figure 2 for the existing QR flyback converter waveform schematic diagram;

[0021] Figure 3 for the staggered QR flyback controller of the present application and its application schematic diagram;

[0022] Figure 4 for the waveform schematic diagram of the present application;

[0023] Figure 5 for the phase switch circuit diagram of the present application;

[0024] Figure 6 for the waveform schematic diagram of the signal of the phase switch of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0026] Embodiment:

[0027] Please refer to Figures 1-3 In the embodiments of the present application, a staggered QR flyback controller includes a control IC and a peripheral circuit. The control IC includes a power supply pin VCC, a 180° phase switch, a resonant signal detection pin ZT, a first drive channel and a second drive channel. The first end of the 180° phase switch is connected to a drive signal DRV. The output ends of the first drive channel and the second drive channel are shorted. The resonant signal detection pin ZT is used to make the power tube of the first drive channel open through zero-crossing detection. The second drive channel includes a second CS pin CS2. The second CS pin is connected to the non-inverting input end of a second over-current protection comparator OCP2 and a second comparator PWM2. The output ends of the second over-current protection comparator OCP2 and the second comparator PWM2 are respectively connected to the first and second input ends of an OR gate. The output end of the OR gate is connected to the reset end R of a second RS flip-flop. The set end S of the second RS flip-flop is connected to the second end of the 180° phase switch. The output end of the second RS flip-flop is connected to the input end of a first driver. The output end of the first driver serves as the output end OUT2 of the second drive channel. The peripheral circuit includes a start-up network. One end of the start-up network is connected to the power supply pin VCC.

[0028] In the embodiment, the side of the control IC is provided with a power supply pin VCC, a compensation pin COMP, a CS pin, a resonance signal detection pin ZT, a ground pin GND, a calibrator and an output pin OUT, the first end of the calibrator is connected to the power supply pin VCC, the second end of the calibrator is connected to a low-voltage reference power supply (REF), one end of the compensation pin COMP is connected to a pull-up resistor, the pull-up resistor is used to pull up the voltage of the compensation pin COMP to the low-voltage reference power supply (REF) and subtract 1V to take one-third to the negative input end of the PWM comparator.

[0029] In the embodiment, the resistance value of the pull-up resistor is 5K.

[0030] Preferably, the first drive channel is a single-channel QR flyback controller.

[0031] Preferably, the start-up network comprises a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 is connected to the input signal Vin, the primary winding of the first transformer T1 and the primary winding of the second transformer T2, the second end of the first resistor R1 is connected to the negative electrode of the first diode D1, the positive electrode of the first diode D1 is connected to the auxiliary winding La1 and the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3 and the resonance signal detection pin ZT of the control IC, the second end of the third resistor R3 is grounded, wherein the primary winding of the first transformer T1 is the first primary winding Lp1, and the primary winding of the second transformer T2 is the second primary winding Lp2.

[0032] In the embodiment, the first diode is a freewheeling diode.

[0033] Preferably, the first transformer T1 comprises a first secondary winding Ls1, and the second transformer T2 comprises a second secondary winding Ls2, one end of the first secondary winding Ls1 and one end of the second secondary winding Ls2 are respectively connected to a diode in series and then connected to the first end of an output capacitor Cout, the first end of the output capacitor Cout is connected to an output voltage VOUT and the first end of a fifth resistor R5, the second end of the output capacitor Cout is grounded, the second end of the fifth resistor R5 is connected to the first end of an isolation operational amplifier IsoAmp and a sixth resistor R6, the second end of the isolation operational amplifier IsoAmp is connected to the first end of a second capacitor C2, and the second end of the second capacitor C2 and the second end of the sixth resistor R6 are grounded.

[0034] Preferably, the 180° phase switch comprises a monostable trigger, and the output end of the monostable trigger is connected to a delay circuit.

[0035] Preferably, the monostable trigger comprises a first inverter INV1, an input end of the first inverter INV1 is connected with a first input end of a NAND gate and a driving signal, an output end of the first inverter INV1 is connected with an input end of a second inverter INV2 and a first end of a third capacitor C3, a second end of the third capacitor C3 is grounded, an output end of the second inverter INV2 is connected with an input end of a third inverter INV3, an output end of the third inverter INV3 is connected with a second input end of the NAND gate, an output end of the NAND gate is connected with an input end of a fourth inverter INV4, an output end of the fourth inverter INV4 is connected with an input end of the delay circuit.

[0036] Preferably, the delay circuit comprises a fifth inverter, an input end of the fifth inverter is connected with an output end of the fourth inverter INV4, an output end of the fifth inverter is connected with a first end of a fourth capacitor C4 and an input end of a sixth inverter INV6, a second end of the fourth capacitor C4 is grounded.

[0037] Preferably, the 180° phase switch further comprises a first MOS transistor N1, a gate of the first MOS transistor N1 is connected with an output end of a seventh inverter INV7, an input end of the seventh inverter INV7 is connected with an output end of the fourth inverter INV4, a drain of the first MOS transistor N1 is connected with a first current source I1, a source of the first MOS transistor N1 is connected with a first end of a fifth capacitor C1', a drain of a second MOS transistor N2 and a source of a third MOS transistor N3, a gate of the third MOS transistor N3 is connected with an output end of the fourth inverter INV4, a drain of the third MOS transistor N3 is connected with a first end of a sixth capacitor C2' and a second current source I2, a first end of the sixth capacitor C2' and a second end of the second current source I2 are grounded, the first end of the sixth capacitor C2' is connected with the third comparator CMP, a source of the second MOS transistor N2 is grounded, a gate of the second MOS transistor N2 is connected with an output end of the sixth inverter INV6, a second end of the fifth capacitor C1' is grounded.

[0038] As shown in FIG. 1, the first driving channel and the second driving channel are connected with the load in parallel, and the first driving channel and the second driving channel are connected with the load in series. Figure 4 As shown in FIG. 2, in the embodiment, no matter how the load changes, and no matter how the working frequency changes, the opening moment of the second driving channel always remains at the middle moment of a working period of the first driving channel.

[0039] As shown in FIG. 3, in the embodiment, no matter how the load changes, and no matter how the working frequency changes, the opening moment of the second driving channel always remains at the middle moment of a working period of the first driving channel. Figure 5As shown, DRV1 is a first channel low voltage drive signal, INV1, INV2, INV3, NAND, INV4, C3 constitute an Oneshot (monostable trigger) circuit, INV5, C4, INV6 constitute a small delay, Ctrl1 and Ctrl3 are in-phase control signals, Ctrl3 is slightly delayed from Ctrl1 (a few ns), Ctrl2 is opposite to Ctrl1, Ctrl2 is slightly delayed from Ctrl1, Ctrl2 controls N1 to determine whether the current source I1 charges the capacitor C1, Ctrl1 controls N3 to determine whether the V1 voltage is transmitted to V2, Ctrl3 controls N2 to determine whether the capacitor C1 is discharged, V2 has a capacitor C2 and a pull-down current source I2 to ground, and V2 is also the negative input terminal of the comparator CMP. In design, the capacitances of C1 and C2 are equal, and the current of I2 is twice that of I.

[0040] As shown in the figure, Figure 6 At t1, Ctrl1 becomes high, N3 is turned on, the energy of capacitor C1 is transmitted to capacitor C2, that is, the V1 signal voltage is transmitted to V2 signal; after a few ns, Ctrl2 becomes low, N1 is turned off, and C1 capacitor no longer continues to charge; after a few ns, Ctrl3 becomes high, and capacitor C1 is immediately discharged to zero; because the pulse width of Ctrl1-3 is very small (a few tens of ns), then Ctrl2 immediately becomes high, Ctrl1 and Ctrl3 immediately become low, N1 is turned on, N2 and N3 are turned off, and current source I1 charges capacitor C1 again;

[0041] At t2, capacitor C2 is discharged to 0V by current source I2 (twice I1), and the discharge time is equal to half of the charging time of capacitor C1 in the previous period. The comparator CMP is inverted, and the output ON_Ctrl of the module becomes high, and the rising edge is used to control the opening of the second channel;

[0042] At t3, t1 is repeated again.

[0043] From the above, t2 is the midpoint of t1-t3, and by controlling the second drive channel to be turned on at t2, it can be ensured that the phase difference between the first channel and the second channel is 180°, and it is not limited to whether the frequency of DRV1 is fixed.

[0044] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can make equivalent replacement or change within the technical range disclosed by the present application according to the technical solution and the inventive concept of the present application, which should be covered within the protection scope of the present application.

Claims

1. An interleaved QR flyback controller, characterized by, The application relates to a control IC, which comprises a power supply pin VCC, a phase switch, a resonant signal detection pin ZT, a first driving channel and a second driving channel, a first end of the phase switch is connected to a driving signal DRV, the output ends of the first driving channel and the second driving channel are short-circuited, the resonant signal detection pin ZT is used for controlling the power tube of the first driving channel to be turned on through zero-crossing detection, the second driving channel comprises a second CS pin CS2, the second CS pin is connected to the same-phase input end of a second over-current protection comparator OCP2 and a second comparator PWM2, the output ends of the second over-current protection comparator OCP2 and the second comparator PWM2 are respectively connected to the first and second input ends of an OR gate, the output end of the OR gate is connected to the reset end R of a second RS flip-flop, the setting end S of the second RS flip-flop is connected to the second end of the phase switch, the output end of the second RS flip-flop is connected to the input end of a first driver, and the output end of the first driver serves as the output end OUT2 of the second driving channel. ​ The peripheral circuit comprises a starting network, one end of the starting network is connected with a power supply pin VCC, and the phase switch comprises a monostable trigger and a delay circuit, an output end of the monostable trigger is connected with the delay circuit, and the monostable trigger comprises: an input end of a first inverter INV1 is connected with a first input end of a NAND gate and a driving signal DRV, an output end of the first inverter INV1 is connected with an input end of a second inverter INV2 and a first end of a third capacitor C3, a second end of the third capacitor C3 is grounded, an output end of the second inverter INV2 is connected with an input end of a third inverter INV3, an output end of the third inverter INV3 is connected with a second input end of the NAND gate, an output end of the NAND gate is connected with an input end of a fourth inverter INV4, and an output end of the fourth inverter INV4 is connected with an input end of the delay circuit; the delay circuit comprises a fifth inverter, a fourth capacitor C4 and a sixth inverter INV6, an input end of the fifth inverter is connected with an output end of the fourth inverter INV4, an output end of the fifth inverter is connected with a first end of the fourth capacitor C4 and an input end of the sixth inverter INV6, and a second end of the fourth capacitor C4 is grounded; the phase switch further comprises: a gate of a first MOS transistor N1 is connected with an output end of a seventh inverter INV7, an input end of the seventh inverter INV7 is connected with an output end of the fourth inverter INV4, a drain of the first MOS transistor N1 is connected with a first current source I1, a source of the first MOS transistor N1 is connected with a first end of a fifth capacitor C1', a drain of a second MOS transistor N2 and a source of a third MOS transistor N3, a gate of the third MOS transistor N3 is connected with an output end of the fourth inverter INV4, a drain of the third MOS transistor N3 is connected with a first end of a sixth capacitor C2' and a first end of a second current source I2, a second end of the sixth capacitor C2' and a second end of the second current source I2 are grounded, a first end of the sixth capacitor C2' is connected with a third comparator CMP, a source of the second MOS transistor N2 is grounded, a gate of the second MOS transistor N2 is connected with an output end of the sixth inverter INV6, a second end of the fifth capacitor C1' is grounded, and an output end of the third comparator CMP is connected with a set end S of a second RS flip-flop.

2. The interleaved QR flyback controller according to claim 1, characterized in that: The first driving channel is a single-channel QR flyback controller.

3. The interleaved QR flyback controller according to claim 2, characterized in that: The starting network comprises a first resistor R1 and a first capacitor C1, a first end of the first resistor R1 is connected with an input signal Vin, a primary winding of a first transformer T1 and a primary winding of a second transformer T2, a second end of the first resistor R1 is connected with a negative electrode of a first diode D1, a positive electrode of the first diode D1 is connected with an auxiliary winding La1 and a first end of a second resistor R2, a second end of the second resistor R2 is connected with a first end of a third resistor R3 and a resonance signal detection pin ZT of a control IC, and a second end of the third resistor R3 is grounded, wherein the primary winding of the first transformer T1 is a first primary winding Lp1, and the primary winding of the second transformer T2 is a second primary winding Lp2.

4. The interleaved QR flyback controller according to claim 3, characterized in that: The first transformer T1 includes a first secondary winding Ls1, the second transformer T2 includes a second secondary winding Ls2, one end of the first secondary winding Ls1 and the second secondary winding Ls2 are connected to the first end of the output capacitor Cout in series after connecting a diode, the first end of the output capacitor Cout is connected to the output voltage VOUT and the first end of the fifth resistor R5, the second end of the output capacitor Cout is grounded, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the isolation operational amplifier IsoAmp, the second end of the isolation operational amplifier IsoAmp is connected to the first end of the second capacitor C2, the second end of the second capacitor C2 and the second end of the sixth resistor R6 are grounded.

5. The interleaved QR flyback controller of claim 4, characterized by: The phase switch is a 180° phase switch.

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