Interstage sampling and holding amplifying circuit
By using an interstage sample-and-hold amplifier circuit with a two-stage amplifier and interpolation resistor array structure, the problems of insufficient swing and linearity of the folded circuit are solved, the dynamic performance and signal delay of the analog-to-digital converter are improved, and efficient signal amplification and holding are achieved.
Patent Information
- Application Number
- CN202511011616.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-11-07
AI Technical Summary
The existing folding circuits have insufficient swing and linearity, which affects the accuracy of analog-to-digital converters. Furthermore, the cascaded folding method results in long signal delays, which affects dynamic performance.
An interstage sample-and-hold amplifier circuit is adopted, including an amplifier unit and a transmission gate unit. Through a two-stage amplifier structure and an interpolation resistor array, the signal amplification and holding are controlled by a clock signal with opposite phase. A common-gate stage and a sleeve-type common-source common-gate amplifier structure are used to improve the gain, and a virtual transistor is used to suppress channel charge injection.
It improves the gain and linearity of the output signal of the folded circuit, simplifies the circuit structure, reduces the area, and improves the response speed, making it suitable for large-scale array applications.
Smart Images
Figure CN120915296A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of analog integrated circuit technology, and in particular to an inter-stage sample-and-hold amplification circuit. BACKGROUND
[0002] The greater the folding factor of the folding interpolation analog-to-digital converter, the more parasitic capacitance is coupled at the input end. In order to improve the bandwidth of the folding circuit, a cascaded folding manner is usually adopted in the related art, which, however, causes the swing and linearity of the output signal of the folding circuit to decrease, thereby affecting the precision of the analog-to-digital conversion. In addition, the more the number of cascaded stages, the longer the signal delay, which affects the dynamic performance of the analog-to-digital converter to some extent. SUMMARY
[0003] The present application provides an inter-stage sample-and-hold amplification circuit to solve the technical problem of insufficient swing and linearity of the current folding circuit, which affects the precision of the analog-to-digital converter, and further improves the dynamic performance of the folding interpolation analog-to-digital converter.
[0004] The present application provides an inter-stage sample-and-hold amplification circuit, which comprises an amplifier unit comprising a first positive input end, a first negative input end, a first positive output end, a first negative output end, a first clock control end and a second clock control end; the first positive input end and the first negative input end are connected to the positive output end and the negative output end of a first-stage folding circuit, respectively; the first positive output end and the first negative output end are connected to two parallel interpolation resistance arrays, respectively; the first clock control end and the second clock control end are connected as input ends of clock signals with opposite phases; each interpolation resistance array comprises a plurality of interpolation resistances connected in series, and the interpolation resistances in the two interpolation resistance arrays are arranged in pairs; the two interpolation resistance arrays are connected to the positive input end and the negative input end of a second-stage folding circuit, respectively; and a plurality of transmission gate units are arranged between a pair of interpolation resistances in the two interpolation resistance arrays.
[0005] In an embodiment of the present application, the amplifier unit comprises a first-stage amplifier and a second-stage amplifier; the positive and negative input ends of the first-stage amplifier are connected to the positive output end and the negative output end of the first-stage folding circuit as the first positive input end and the first negative input end, respectively; the output end of the first-stage amplifier is connected to the input end of the second-stage amplifier, and the positive and negative output ends of the second-stage amplifier are connected as the first positive output end and the first negative output end, respectively.
[0006] In an embodiment of the present application, the first-stage amplifier adopts a common-gate amplification structure.
[0007] In an embodiment of the present application, the second-stage amplifier adopts a sleeve-type common-source common-gate amplification structure.
[0008] In an embodiment of the present application, the first-stage amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor; a source of the first transistor is connected to a source of the second transistor and a power voltage is applied thereto; a gate of the first transistor is connected to a gate of the second transistor and a first bias voltage is applied thereto; a drain of the first transistor is connected to a source of the third transistor and serves as the first positive input terminal; a drain of the second transistor is connected to a drain of the fourth transistor and serves as the first negative input terminal; a gate of the third transistor is connected to a gate of the fourth transistor and a second bias voltage is applied thereto; a drain of the third transistor is connected to a drain of the fifth transistor and a drain of the fourth transistor is connected to a drain of the sixth transistor; a source of the fifth transistor is connected to a source of the sixth transistor and a ground voltage is applied thereto; a drain of the seventh transistor is connected to the drain of the third transistor, a gate of the seventh transistor is connected to the power voltage, a source of the seventh transistor is connected to a gate of the fifth transistor; a drain of the eighth transistor is connected to the drain of the fourth transistor, a gate of the eighth transistor is connected to the power voltage, and a source of the eighth transistor is connected to a gate of the sixth transistor; a gate of the ninth transistor, a gate of the eleventh transistor, a gate of the thirteenth transistor, a gate of the fourteenth transistor, a gate of the sixteenth transistor and a gate of the eighteenth transistor are connected to a first clock; a gate of the tenth transistor, a gate of the twelfth transistor, a gate of the fifteenth transistor and a gate of the seventeenth transistor are connected to a second clock, wherein the first clock and the second clock are opposite in phase; a source of the ninth transistor is connected to the drain of the fourth transistor after being short-circuited with a drain of the ninth transistor; a source of the tenth transistor is connected to the drain of the fourth transistor, and a drain of the tenth transistor is connected to a drain of the twelfth transistor and serves as a first output terminal of the first-stage amplifier; a source of the eleventh transistor is connected to the drain of the tenth transistor after being short-circuited with a drain of the eleventh transistor; a source of the thirteenth transistor is connected to the gate of the sixth transistor and a source of the twelfth transistor after being short-circuited with a drain of the thirteenth transistor; a source of the fourteenth transistor is connected to a source of the fifteenth transistor and a source of the seventeenth transistor after being short-circuited with a drain of the fourteenth transistor and serves as a second output terminal of the first-stage amplifier; a drain of the fifteenth transistor is connected to the drain of the third transistor; a source of the sixteenth transistor is connected to the drain of the third transistor after being short-circuited with a drain of the sixteenth transistor; a drain of the seventeenth transistor is connected to the gate of the fifth transistor, and a source of the eighteenth transistor is connected to the gate of the fifth transistor after being short-circuited with a gate of the eighteenth transistor.
[0009] In an embodiment of the present application, the second-stage amplifier comprises a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor and a twenty-eighth transistor; the gate and the drain of the nineteenth transistor are short-circuited and connected to the gate of the twentieth transistor; the source of the nineteenth transistor, the source of the twentieth transistor, the source of the twenty-first transistor and the source of the twenty-second transistor are connected to the power supply voltage respectively; the drain of the nineteenth transistor is connected to the drain of the twenty-first transistor and the drain of the twenty-third transistor as the first negative output terminal, and the drain of the twentieth transistor is connected to the drain of the twenty-second transistor, the gate of the twenty-second transistor, the gate of the twenty-first transistor and the drain of the twenty-fourth transistor as the first positive output terminal; the gate of the twenty-third transistor is connected to a third bias voltage, and the source of the twenty-third transistor is connected to the drain of the twenty-fifth transistor; the gate of the twenty-fourth transistor is connected to the third bias voltage, and the source of the twenty-fourth transistor is connected to the drain of the twenty-sixth transistor; the source of the twenty-sixth transistor is connected to the source of the twenty-fifth transistor; the gate of the twenty-fifth transistor is connected to the second output terminal, and the gate of the twenty-sixth transistor is connected to the first output terminal; the gate and the drain of the twenty-seventh transistor are connected and connected to the source of the twenty-eighth transistor and the drain of the nineteenth transistor respectively; the gate and the drain of the twenty-eighth transistor are connected and connected to the source of the twenty-seventh transistor and the drain of the twenty-second transistor respectively.
[0010] In an embodiment of the present application, the ninth transistor, the eleventh transistor, the thirteenth transistor, the fourteenth transistor, the sixteenth transistor and the eighteenth transistor are dummy transistors; the tenth transistor, the twelfth transistor, the fifteenth transistor and the seventeenth transistor are switch transistors, the gate length of the dummy transistor is the same as the gate length of the switch transistor; the width of the eleventh transistor is equal to half of the sum of the width of the tenth transistor and the width of the twelfth transistor; the width of the ninth transistor is equal to half of the width of the tenth transistor; the width of the thirteenth transistor is equal to half of the width of the twelfth transistor; the width of the fourteenth transistor is equal to half of the sum of the width of the fifteenth transistor and the width of the seventeenth transistor; the width of the sixteenth transistor is equal to half of the width of the fifteenth transistor; and the width of the eighteenth transistor is equal to half of the width of the seventeenth transistor.
[0011] In an embodiment of the present application, the transmission gate unit comprises a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor is connected with the drain of the first NMOS transistor as the input terminal of the transmission gate unit; the drain of the first PMOS transistor is connected with the source of the first NMOS transistor as the output terminal of the transmission gate unit; the gate of the first PMOS transistor is connected with the first clock, and the gate of the first NMOS transistor is connected with the second clock.
[0012] The present application has the following advantages: the inter-stage sampling holding amplification circuit provided by the present application is used between stages of a cascade folded circuit, can improve the gain of the output signal of the folded circuit, and improve the linearity; the circuit structure is simple, the area is small, the response speed is fast, and the circuit is suitable for large-scale array application. BRIEF DESCRIPTION OF DRAWINGS
[0013] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application. It is apparent that the accompanying drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0014] In the drawings:
[0015] Figure 1 It is a schematic diagram of a traditional cascade folded circuit structure;
[0016] Figure 2 It is a schematic diagram of the circuit architecture of the inter-stage sampling holding amplification circuit provided by an embodiment of the present application;
[0017] Figure 3 It is a circuit schematic diagram of the amplifier unit in an embodiment of the present application;
[0018] Figure 4 It is a schematic diagram of the CMOS transmission gate unit in an embodiment of the present application; Figure 2
[0019] Figure 5 It is an AC simulation gain bandwidth diagram of the amplifier in an embodiment of the present application;
[0020] Figure 6 It is a time domain waveform diagram of the inter-stage sampling holding amplification circuit in an embodiment of the present application;
[0021] Figure 7 It is a frequency domain dynamic performance parameter diagram obtained according to the inter-stage sampling holding amplification circuit in an embodiment of the present application. Figure 6
[0022] The reference signs are as follows:
[0023] Ml - first transistor; M2 - second transistor; M3 - third transistor; M4 - fourth transistor; M5 - fifth transistor; M6 - sixth transistor; M7 - seventh transistor; M8 - eighth transistor; M9 - ninth transistor; Ml 0 - tenth transistor; Ml 1 - eleventh transistor; Ml 2 - twelfth transistor; Ml 3 - thirteenth transistor; Ml 4 - fourteenth transistor; Ml 5 - fifteenth transistor; Ml 6 - sixteenth transistor; Ml 7 - seventeenth transistor; Ml 8 - eighteenth transistor; Ml 9 - nineteenth transistor; M20 - twentieth transistor; M21 - twenty-first transistor; M22 - twenty-second transistor; M23 - twenty-third transistor; M24 - twenty-fourth transistor; M25 - twenty-fifth transistor; M26 - twenty-sixth transistor; M27 - twenty-seventh transistor; M28 - twenty-eighth transistor; VDD - power supply voltage; Vbl - first bias voltage; Vb2 - second bias voltage; Vb3 - third bias voltage; Vinp - first positive input terminal; Vinn - first negative input terminal; Von - first negative output terminal; Vop - first positive output terminal. DETAILED DESCRIPTION
[0024] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure or can be learned by practice of the application. The application can be realized and achieved by means of the structures and combinations of structures described and claimed in this specification and can be realized and achieved by means of structures and combinations of structures that are equivalent to those described and claimed in this specification. Various embodiments of the present application are described herein with reference to the accompanying drawings, in which:
[0025] It is also noted that the graphical illustrations provided in the following embodiments merely illustrate the basic concept of the present application, and the drawings in the accompanying drawings only show the components related to the present application, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component may
[0026] In the following description, numerous specific details are discussed in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one of ordinary skill in the art that the embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the embodiments of the present application.
[0027] The inventors have found that:
[0028] The greater the folding factor of the folding circuit in the folding interpolation analog-digital converter, the more the parasitic capacitance coupled at the input end, which leads to difficulty in improving the bandwidth of the folding circuit, so in the design of the ultra-high-speed folding interpolation analog-digital converter, cascaded folding is usually adopted to realize a high folding factor, that is, a higher folding factor is divided into the product of two smaller folding factors, and the output of the upper-stage folding circuit is taken as the input of the lower-stage folding circuit. Figure 1 It is a schematic diagram of a traditional cascaded folding circuit structure.
[0029] In this cascaded folding circuit structure, firstly, the swing and linearity of the output signal of the folding circuit are reduced, which is not conducive to the folding and interpolation of the circuit in the later stage and affects the output accuracy of the ADC; secondly, there are a preamplifier array and cascaded folding interpolation circuits between the output signal of the front-end sample-and-hold circuit and the comparator, and the more the number of cascaded circuit stages, the longer the signal delay is; for an ultra-high sampling rate, the clock period is close to or reaches the ps level, so it is difficult for the output signal of the front-end sample-and-hold circuit to reach the output end of the ADC within half a clock period, thereby affecting the dynamic performance of the ADC.
[0030] Based on the problems in the above related technologies, the present application provides an inter-stage sample-and-hold amplification circuit, and the technical solutions of the present application are described in detail below in combination with specific embodiments.
[0031] Please refer to Figure 2 , Figure 2 It is a schematic diagram of the circuit architecture of the inter-stage sample-and-hold amplification circuit provided by an embodiment of the present application. As shown in Figure 2 , the inter-stage sample-and-hold amplification circuit is applied between two-stage folding circuits, and the inter-stage sample-and-hold amplification circuit comprises an amplifier unit, a first positive input end, a first negative input end, a first positive output end, a first negative output end, a first clock control end and a second clock control end; the first positive input end and the first negative input end are connected to the positive output end and the negative output end of the first-stage folding circuit respectively; the first positive output end and the first negative output end are connected to two parallel interpolation resistance arrays respectively, and the first clock control end and the second clock control end are taken as the input ends of the clock with opposite phases respectively; wherein each interpolation resistance array comprises a plurality of interpolation resistances connected in series, and the interpolation resistances in the two interpolation resistance arrays are arranged in pairs; the two interpolation resistance arrays are connected to the positive input end and the negative input end of the second-stage folding circuit respectively; a plurality of transmission gate units are arranged between a pair of interpolation resistances in the two interpolation resistance arrays.
[0032] The resistor interpolation circuit with an interpolation coefficient of 3 is taken as an example, the input and output signals are differential signals, the clock-controlled amplifier unit is controlled by two phase-opposed clock signals CLKP and CLKN, the positive and negative input terminals of the clock-controlled amplifier unit are connected to the output of the previous-stage folding circuit, and the positive and negative output terminals of the clock-controlled amplifier unit are connected to the interpolation circuit composed of two parallel interpolation resistor arrays. The transmission gate unit is controlled by the same clock signals CLKP and CLKN, and the input and output of the transmission gate unit are connected to the two parallel interpolation resistors, and each pair of parallel interpolation resistors has a transmission gate unit. Specifically, the first-stage folding circuit can include two groups of outputs, each group of outputs includes positive and negative outputs, and the two groups of outputs are connected to two ends of the two interpolation resistor arrays through one amplifier unit. For example, the positive terminal of the first group of outputs is connected to the first positive input terminal of the first amplifier unit, the negative terminal of the first group of outputs is connected to the first negative input terminal of the first amplifier unit, the first positive output terminal of the first amplifier unit is connected to one end of the first interpolation resistor array, and the first negative output terminal of the first amplifier unit is connected to one end of the second interpolation resistor array; the positive terminal of the second group of outputs is connected to the first positive input terminal of the second amplifier unit, the negative terminal of the second group of outputs is connected to the first negative input terminal of the second amplifier unit, the first positive output terminal of the second amplifier unit is connected to the other end of the first interpolation resistor array, and the first negative output terminal of the second amplifier unit is connected to the other end of the second interpolation resistor array. The second-stage folding circuit includes two groups of inputs, each group of inputs also includes positive and negative input terminals. The positive input terminal of the first group of inputs of the second-stage folding circuit is connected between two resistors of the first interpolation resistor array, and the negative input terminal is connected between two corresponding resistors of the second interpolation resistor array; the positive input terminal of the second group of inputs is connected between the other two resistors of the first interpolation resistor array, and the negative input terminal is connected between the two corresponding resistors of the second interpolation resistor array. The two groups of inputs can be separated by a pair of resistors or multiple pairs of resistors, and the specific number of resistors can be set and adjusted according to actual application requirements, which is not limited here.
[0033] Please refer to Figure 3 , Figure 3 It is a circuit schematic diagram of the amplifier unit in an embodiment of the present application. In an embodiment, the amplifier unit includes a first-stage amplifier and a second-stage amplifier; the positive and negative input terminals of the first-stage amplifier are connected to the positive and negative output terminals of the first-stage folding circuit as the first positive input terminal and the first negative input terminal, respectively; the output terminal of the first-stage amplifier is connected to the input terminal of the second-stage amplifier, and the positive and negative output terminals of the second-stage amplifier are used as the first positive output terminal and the first negative output terminal, respectively.
[0034] In an embodiment, the first-stage amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor; a source of the first transistor is connected to a source of the second transistor and a power voltage is applied thereto; a gate of the first transistor is connected to a gate of the second transistor and a first bias voltage is applied thereto; a drain of the first transistor is connected to a source of the third transistor and serves as a first positive input terminal; a drain of the second transistor is connected to a drain of the fourth transistor and serves as a first negative input terminal; a gate of the third transistor is connected to a gate of the fourth transistor and a second bias voltage is applied thereto; a drain of the third transistor is connected to a drain of the fifth transistor and a drain of the fourth transistor is connected to a drain of the sixth transistor; a source of the fifth transistor is connected to a source of the sixth transistor and a ground voltage is applied thereto; a drain of the seventh transistor is connected to the drain of the third transistor, a gate of the seventh transistor is connected to the power voltage, a source of the seventh transistor is connected to a gate of the fifth transistor; a drain of the eighth transistor is connected to the drain of the fourth transistor, a gate of the eighth transistor is connected to the power voltage, and a source of the eighth transistor is connected to a gate of the sixth transistor; a gate of the ninth transistor, a gate of the eleventh transistor, a gate of the thirteenth transistor, a gate of the fourteenth transistor, a gate of the sixteenth transistor and a gate of the eighteenth transistor are connected to a first clock; a gate of the tenth transistor, a gate of the twelfth transistor, a gate of the fifteenth transistor and a gate of the seventeenth transistor are connected to a second clock, wherein the first clock and the second clock are opposite in phase; a source of the ninth transistor is connected to the drain of the fourth transistor after being short-circuited with a drain of the ninth transistor; a source of the tenth transistor is connected to the drain of the fourth transistor, and a drain of the tenth transistor is connected to a drain of the twelfth transistor and serves as a first output terminal of the first-stage amplifier; a source of the eleventh transistor is connected to the drain of the tenth transistor after being short-circuited with a drain of the eleventh transistor; a source of the thirteenth transistor is connected to the gate of the sixth transistor and a source of the twelfth transistor after being short-circuited with a drain of the thirteenth transistor; a source of the fourteenth transistor is connected to a source of the fifteenth transistor and a source of the seventeenth transistor after being short-circuited with a drain of the fourteenth transistor and serves as a second output terminal of the first-stage amplifier; a drain of the fifteenth transistor is connected to the drain of the third transistor; a source of the sixteenth transistor is connected to the drain of the third transistor after being short-circuited with a drain of the sixteenth transistor; a drain of the seventeenth transistor is connected to the gate of the fifth transistor, and a source of the eighteenth transistor is connected to the gate of the fifth transistor after being short-circuited with a gate of the eighteenth transistor. Specifically, the first transistor to the eighth transistor constitute a subject part of the first-stage amplifier, and the ninth transistor to the eighteenth transistor constitute a switch part of the first-stage amplifier.
[0035] In an embodiment, the second-stage amplifier comprises a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, and a twenty-eighth transistor.
[0036] The gate and the drain of the nineteenth transistor are shorted and connected to the gate of the twentieth transistor; the source of the nineteenth transistor, the source of the twentieth transistor, the source of the twenty-first transistor, and the source of the twenty-second transistor are respectively connected to the power supply voltage; the drain of the nineteenth transistor is respectively connected to the drain of the twenty-first transistor and the drain of the twenty-third transistor as the first negative output end, and the drain of the twentieth transistor is respectively connected to the drain of the twenty-second transistor, the gate of the twenty-second transistor, the gate of the twenty-first transistor, and the drain of the twenty-fourth transistor as the first positive output end; the gate of the twenty-third transistor is connected to a third bias voltage, and the source of the twenty-third transistor is connected to the drain of the twenty-fifth transistor, the gate of the twenty-fourth transistor is connected to the third bias voltage, and the source of the twenty-fourth transistor is connected to the drain of the twenty-sixth transistor; the source of the twenty-sixth transistor is connected to the source of the twenty-fifth transistor; the gate of the twenty-fifth transistor is connected to the second output end, and the gate of the twenty-sixth transistor is connected to the first output end; the gate and the drain of the twenty-seventh transistor are connected and respectively connected to the source of the twenty-eighth transistor and the drain of the nineteenth transistor; the gate and the drain of the twenty-eighth transistor are connected and respectively connected to the source of the twenty-seventh transistor and the drain of the twenty-second transistor. M1-M4, M19-M22 are PMOS tubes, and the rest of the transistors are NMOS tubes.
[0037] In an embodiment, the transmission gate unit comprises a first PMOS tube and a first NMOS tube, the source of the first PMOS tube is connected to the drain of the first NMOS tube as the input end of the transmission gate unit; the drain of the first PMOS tube is connected to the source of the first NMOS tube as the output end of the transmission gate unit; the gate of the first PMOS tube is connected to the first clock, and the gate of the first NMOS tube is connected to the second clock. Specifically, the transmission gate unit can be a transmission gate made of CMOS process, the input is the source end of the first PMOS tube, and the output is the source end of the first NMOS tube. The drain and the source of the first PMOS tube are respectively connected to the source and the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the clock signal CLKN, and the gate of M2 is connected to the clock signal CLKP. The substrate end of all the PMOS tubes is connected to the power supply VDD, and the substrate end of all the NMOS tubes is connected to the ground.
[0038] The amplifier unit of the present application is controlled by phase-opposed clock, and can realize signal amplification, and improve the swing and linearity of input signal of the subsequent circuit. In order to achieve certain gain, two-stage amplification mode is adopted. The first-stage amplifier adopts common-gate amplification mode, the common-gate tubes M3 and M4 isolate the drain end of the input tube from the output end, and are used for improving the bandwidth of the circuit; M7 and M8 are connected to the voltage VDD at the gate, and they are always on, so that M5 and M6 are connected in diode mode. The single-ended gain of the first-stage amplifier can be approximately expressed as:
[0039]
[0040] wherein g m3 , g are the transconductances of M3 and M5 respectively, and the diode-connected device as the load can make the gain not subject to the change of output voltage, so that the input and output are relatively linear.
[0041] The second-stage amplifier adopts sleeve-type common-source common-gate amplification structure, and can effectively improve the gain. M19-M22 are cross-coupled PMOS active loads, and the current cancellation technology is adopted to obtain large gain, so that any resistance value from 1 / gm to infinity can be realized, and the influence of power supply voltage on common-mode output voltage can also be eliminated. The single-ended gain of the second-stage amplifier can be approximately expressed as:
[0042]
[0043] g m19 , g m20 , g m25 are the transconductances of M19, M20 and M25 respectively. The output positive and negative ends are connected by a group of forward and negative diode-connected MOS tubes, i.e. M27 and M28, which can provide stable current output under forward voltage, and supply the subsequent interpolation resistance circuit.
[0044] The following describes the circuit part for sampling and holding. Since the inter-stage sampling and holding circuit receives the quasi-DC signal output by the front-end sampling and holding circuit, the switch adopts simple NMOS switch and CMOS switch. The whole circuit is composed of two-stage sampling switches, and adopts the method of hierarchical sampling. The first-stage sampling switch is the switch unit part in the amplifier, i.e. M9-M18 in Figure 3 , and the second-stage sampling switch is the CMOS transmission gate unit in Figure 2 . No additional sampling capacitor is added in the circuit, the sampling capacitor of the first-stage switch is the parasitic capacitor of the output end of the first-stage amplifier, and the sampling capacitor of the second-stage switch is the parasitic capacitor of the output end of the second-stage amplifier and the interpolation resistance array.
[0045] When CLKP is high, the NMOS switches M10, M12, M15, M17 of the first stage are opened, so the output signal of the first stage switch is in tracking state; the CMOS pass gate of the second stage switch is turned on, which is equivalent to shorting the positive and negative terminals of the amplifier output and the interpolation circuit, so the output signal of the second stage switch is equivalent to being reset and zeroed, in holding state. When CLKP is low, the first stage switch is cut off, and the output signal is in holding state; the CMOS pass gate of the second stage switch is cut off, and the output positive and negative terminals are no longer shorted and can normally output the signal, so the output signal of the second stage switch is equivalent to the tracking state. In summary, when CLKP is low, the second stage switch outputs the quasi-DC signal held by the first stage switch for the folding circuit in the subsequent stage; when CLKP is high, the output positive and negative terminals are shorted, so the output signal at this time is equivalent to being reset.
[0046] In order to suppress the influence of channel charge injection on the first stage sampling switch, virtual tubes, i.e. M9, M11, M13, M14, M16, M18, are added. Taking one of the NMOS switches M10 as an example, when it is turned on, a certain amount of charge will accumulate at the inversion layer channel, represented as:
[0047] Q ch = W M10 L M10 C OX (V DD -V in -V TH ) (3)
[0048] W M10 , L M10 are the gate width and length of M10 respectively, COX is the gate oxide layer capacitance, VDD is the power voltage, Vin is the input voltage, and VTH is the threshold voltage. When M10 is cut off, the channel charge will leak to the source and drain terminals. Assuming that the charge leaked to the source terminal is half of Qch, the error voltage of the source terminal caused by the channel charge is:
[0049]
[0050] Cs is the parasitic capacitance of the source terminal.
[0051] Virtual tubes M9, M11, M13 are added to the source and drain terminals of the NMOS switches M10, M12, and the clock signal connected to the virtual tubes is CLKN, which is opposite to the clock signal of the switch tube. When the switch tube is turned off, M9, M11, M13 are turned on to absorb the channel charge leaked by the switch tube. The length of the gate of the switch tube is the same as that of the virtual tube, and the width is W M11 = 0.5W M10 + 0.5W M12 , WM9 = 0.5W M10 , W M13 = 0.5W M12 The purpose of the design is to effectively absorb the charge when the channel charge leaks to the average source and drain. The switch tube M15, M17 and the virtual tube M14, M16, M18 also follow the design rules.
[0052] The power supply voltage VDD connected to the gate of M7, M8 is in the always-on state, which can effectively suppress the influence of clock feedthrough.
[0053] The inter-stage sampling and holding amplifier circuit is constructed and simulated in cadence simulation environment using 0.18 μm CMOS process and 1.9 V power supply voltage. The input common mode level of the amplifier is set to 1.4 V, and the switch unit in the amplifier is set to the tracking state, and the AC simulation analysis of the amplifier is carried out. The simulation results are shown in Figure 5 , the gain is 18.4 dB, and the -3 dB bandwidth is 1.58 GHz. The sampling clock frequency is set to 800 MHz, the input signal frequency is set to 46.875 MHz, and the input signal amplitude is 50 mV, and the transient simulation is carried out. The simulation results are shown in Figure 6 , from top to bottom in the figure are CLKP clock signal, input signal, and sampling and holding output signal. It can be seen that the output signal is in the reset phase in the first half cycle of the clock, and in the holding phase in the second half cycle, which can realize the function of sampling and holding; the amplitude of the output signal in the holding phase is greatly increased compared with the input signal, which is the embodiment of the amplification function of the circuit. The FFT frequency domain analysis of the sampling and holding output signal in Figure 6 is shown in Figure 7 , ENOB = 11.5 bit, SNR = 90.2 dB, and SFDR = 71.3 dB, which shows that the dynamic performance is sufficient to meet the requirements of the subsequent circuit.
[0054] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.
Claims
1. An inter-stage sample-and-hold amplification circuit characterized by comprising: The circuit comprises: An amplifier unit comprising a first positive input end, a first negative input end, a first positive output end, a first negative output end, a first clock control end and a second clock control end; the first positive input end and the first negative input end are connected to the positive output end and the negative output end of the first-stage folding circuit respectively; the first positive output end and the first negative output end are connected to two parallel interpolation resistance arrays respectively, and the first clock control end and the second clock control end are connected to the input ends of clock signals with opposite phases respectively; each of the interpolation resistance arrays comprises a plurality of interpolation resistances connected in series, and the interpolation resistances in the two interpolation resistance arrays are arranged in pairs; the positive input end and the negative input end of the second-stage folding circuit are connected to the two interpolation resistance arrays respectively. A plurality of transmission gate units, each of which is arranged between a pair of interpolation resistances in the two interpolation resistance arrays.
2. The inter-stage sample-and-hold amplification circuit according to claim 1, wherein, The amplifier unit comprises a first-stage amplifier and a second-stage amplifier; the positive input end and the negative input end of the first-stage amplifier are connected to the positive output end and the negative output end of the first-stage folding circuit as the first positive input end and the first negative input end respectively; the output end of the first-stage amplifier is connected to the input end of the second-stage amplifier, and the positive output end and the negative output end of the second-stage amplifier are connected as the first positive output end and the first negative output end respectively.
3. The inter-stage sample-and-hold amplification circuit of claim 2, wherein, The first-stage amplifier adopts a common-gate stage amplification structure.
4. The inter-stage sample-and-hold amplification circuit of claim 2, wherein, The second-stage amplifier adopts a sleeve type common-source common-gate amplification structure.
5. The inter-stage sample-and-hold amplification circuit of claim 2, wherein, The first-stage amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor. The source of the first transistor is connected with the source of the second transistor, the gate of the first transistor is connected with the gate of the second transistor and is connected with a first bias voltage, the drain of the first transistor is connected with the source of the third transistor as the first positive input terminal, the drain of the second transistor is connected with the drain of the fourth transistor as the first negative input terminal, the gate of the third transistor is connected with the gate of the fourth transistor and is connected with a second bias voltage, the drain of the third transistor is connected with the drain of the fifth transistor, the drain of the fourth transistor is connected with the drain of the sixth transistor, the source of the fifth transistor is connected with the source of the sixth transistor, the drain of the seventh transistor is connected with the drain of the third transistor, the gate is connected with the power supply voltage, the source is connected with the gate of the fifth transistor, the drain of the eighth transistor is connected with the drain of the fourth transistor, the gate is connected with the power supply voltage, the source is connected with the gate of the sixth transistor, the gate of the ninth transistor, the gate of the eleventh transistor, the gate of the thirteenth transistor, the gate of the fourteenth transistor, the gate of the sixteenth transistor and the gate of the eighteenth transistor are connected with a first clock, the gate of the tenth transistor, the gate of the twelfth transistor, the gate of the fifteenth transistor and the gate of the seventeenth transistor are connected with a second clock, wherein the first clock and the second clock are opposite in phase, the source and the drain of the ninth transistor are connected with the drain of the fourth transistor after being short-circuited, the source of the tenth transistor is connected with the drain of the fourth transistor, the drain is connected with the drain of the twelfth transistor as the first output terminal of the first-stage amplifier, the source and the drain of the eleventh transistor are connected with the drain of the tenth transistor after being short-circuited, the source and the drain of the thirteenth transistor are connected with the gate of the sixth transistor and the source of the twelfth transistor respectively after being short-circuited, the source and the drain of the fourteenth transistor are connected with the source of the fifteenth transistor and the source of the seventeenth transistor respectively as the second output terminal of the first-stage amplifier, the drain of the fifteenth transistor is connected with the drain of the third transistor, the source and the drain of the sixteenth transistor are connected with the drain of the third transistor after being short-circuited, the drain of the seventeenth transistor is connected with the gate of the fifth transistor, and the source and the gate of the eighteenth transistor are connected with the gate of the fifth transistor after being short-circuited.
6. The inter-stage sample-and-hold amplification circuit of claim 5, wherein, The second-stage amplifier comprises a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor and a twenty-eighth transistor. The gate and the drain of the nineteenth transistor are short-circuited, and the gate of the twentieth transistor is connected; the source of the nineteenth transistor, the source of the twentieth transistor, the source of the twenty-first transistor, and the source of the twenty-second transistor are respectively connected to the power supply voltage; the drain of the nineteenth transistor is respectively connected to the drain of the twenty-first transistor and the drain of the twenty-third transistor as the first negative output end, and the drain of the twentieth transistor is respectively connected to the drain of the twenty-second transistor, the gate of the twenty-second transistor, the gate of the twenty-first transistor, and the drain of the twenty-fourth transistor as the first positive output end; the gate of the twenty-third transistor is connected to the third bias voltage, and the source is connected to the drain of the twenty-fifth transistor, the gate of the twenty-fourth transistor is connected to the third bias voltage, and the source is connected to the drain of the twenty-sixth transistor; the source of the twenty-sixth transistor is connected to the source of the twenty-fifth transistor; the gate of the twenty-fifth transistor is connected to the second output end, and the gate of the twenty-sixth transistor is connected to the first output end; the gate and the drain of the twenty-seventh transistor are connected, and are respectively connected to the source of the twenty-eighth transistor and the drain of the nineteenth transistor; the gate and the drain of the twenty-eighth transistor are connected, and are respectively connected to the source of the twenty-seventh transistor and the drain of the twenty-second transistor.
7. The inter-stage sample-and-hold amplification circuit of claim 5, wherein, The ninth transistor, the eleventh transistor, the thirteenth transistor, the fourteenth transistor, the sixteenth transistor, and the eighteenth transistor are dummy tubes; the tenth transistor, the twelfth transistor, the fifteenth transistor, and the seventeenth transistor are switch tubes, the gate length of the dummy tube is the same as the gate length of the switch tube; the width of the eleventh transistor is equal to half of the sum of the width of the tenth transistor and the width of the twelfth transistor; the width of the ninth transistor is equal to half of the width of the tenth transistor; the width of the thirteenth transistor is equal to half of the width of the twelfth transistor; the width of the fourteenth transistor is equal to half of the sum of the width of the fifteenth transistor and the width of the seventeenth transistor; The width of the sixteenth transistor is equal to half of the width of the fifteenth transistor; the width of the eighteenth transistor is equal to half of the width of the seventeenth transistor.
8. The inter-stage sample-and-hold amplification circuit of claim 5, wherein, The transmission gate unit includes a first PMOS tube and a first NMOS tube, the source of the first PMOS tube is connected to the drain of the first NMOS tube as the input end of the transmission gate unit; the drain of the first PMOS tube is connected to the source of the first NMOS tube as the output end of the transmission gate unit; the gate of the first PMOS tube is connected to the first clock, and the gate of the first NMOS tube is connected to the second clock.