Gallium nitride transistor and preparation method thereof

Abstract

The invention discloses a gallium nitride transistor and a preparation method thereof. The gallium nitride transistor comprises a composite substrate layer, a gallium nitride auxiliary layer and a functional layer, wherein the gallium nitride auxiliary layer and the functional layer are laminated on the composite substrate layer; the composite substrate layer comprises a base substrate and an epitaxial layer, the base substrate and the epitaxial layer are single crystal silicon carbide layers, and the resistivity of the epitaxial layer is higher than that of the base substrate. According to the invention, through the composite silicon carbide substrate composed of the low-cost low-resistivity silicon carbide substrate and the epitaxial growth high-resistivity silicon carbide layer, the device not only combines the properties of high resistivity, high thermal conductivity and high mechanical strength of silicon carbide, but also greatly reduces the material cost. The gallium nitride transistor with the composite silicon carbide substrate structure provided by the invention is more cost-effective than a uniform semi-insulating silicon carbide substrate, and retains all ideal material characteristics of silicon carbide suitable for high-frequency and high-power application.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a gallium nitride transistor and a preparation method thereof. BACKGROUND

[0002] Gallium nitride high electron mobility transistor (GaN-HEMT) devices are widely used in many power electronic applications. The GaN-HEMT structure can be epitaxially grown on different substrate materials, such as AlN, GaN, Si, SiC and sapphire, by MOCVD. Among them, the performance of the device is heavily dependent on the substrate material, for example, the dynamic on-resistance performance is better on the sapphire substrate, and the heat dissipation performance is better on the SiC substrate. In practice, the selection of the device substrate material depends on many factors, including cost, size (2 to 12 inches), inherent material performance (mechanical strength against warping, resistivity and thermal conductivity of thicker GaN epitaxial layers) and electrical performance and thermal management of the final device.

[0003] At present, the SiC substrate with a size of 4 to 8 inches suitable for large-scale production, that is, the GaN HEMT device in the RF front-end and PA application can be manufactured thereon to achieve the best heat dissipation management through the SiC substrate.

[0004] However, due to the limitation of the material itself (the cost is 2 to 20 times that of Si), the cost of the entire device is very high when using the SiC substrate. SUMMARY

[0005] The purpose of the present application is to provide a gallium nitride transistor and a preparation method thereof, which can reduce the cost while ensuring the performance of the transistor.

[0006] To achieve the above purpose, the present application provides the following solutions: In a first aspect, the present application provides a gallium nitride transistor, comprising: a composite substrate layer, and an auxiliary layer and a functional layer arranged on the composite substrate layer in a stack; The composite substrate layer comprises a base substrate and an epitaxial layer, and the base substrate and the epitaxial layer are single crystal silicon carbide layers, and the resistivity of the epitaxial layer is higher than that of the base substrate.

[0007] Optionally, in some embodiments, the single crystal silicon carbide in the composite substrate layer has a 3C, 4H or 6H lattice structure.

[0008] Optionally, in some embodiments, the thickness of the base substrate in the composite substrate layer is greater than the thickness of the epitaxial layer.

[0009] Optionally, in some embodiments, the gallium nitride transistor, the epitaxial layer comprises a single layer or more than one layer of silicon carbide layer, and the resistivity of each layer of silicon carbide in the multi-layer silicon carbide layer increases from the base substrate to the auxiliary layer.

[0010] Optionally, in some embodiments, the gallium nitride transistor, the thickness of each silicon carbide layer in the epitaxial layer is 5-50 μm.

[0011] Optionally, in some embodiments, the gallium nitride transistor, the thickness of the base substrate is 300-1000 μm, and the total thickness of the epitaxial layer is 5-300 μm.

[0012] Optionally, in some embodiments, the gallium nitride transistor, the auxiliary layer is a buffer layer, the functional layer comprises a channel layer and a barrier layer which are stacked on the buffer layer, and a source electrode, a gate electrode and a drain electrode which are patterned on the barrier layer.

[0013] In another aspect, the application provides a method for preparing a gallium nitride transistor, the method is used for preparing the gallium nitride transistor as described in the first aspect, and the method comprises: forming an epitaxial layer of single-crystal silicon carbide on a base substrate of single-crystal silicon carbide, the base substrate has a resistivity less than that of the epitaxial layer; stacking an auxiliary layer and a functional layer on the epitaxial layer in sequence.

[0014] According to the specific embodiments provided by the application, the following technical effects are disclosed: The application provides a gallium nitride transistor and a preparation method, the substrate of the transistor is set as a composite substrate layer comprising a base substrate with low resistivity and an epitaxial layer with high resistivity, wherein the presence of the low-resistivity silicon carbide layer in the base substrate greatly reduces the material cost of the substrate part; and the high-resistivity epitaxial layer formed on the low-resistivity base substrate ensures the electrical performance and thermal management performance of the device substrate. That is, the structure provided by the application uses a composite SiC substrate composed of a low-resistivity SiC substrate with low cost and an epitaxially grown high-resistivity SiC layer, so that the device combines the high-resistivity, high-thermal-conductivity and high-mechanical-strength performance of silicon carbide and greatly reduces the material cost. That is, the gallium nitride transistor with the composite SiC substrate structure provided by the application is more cost-effective than a homogeneous semi-insulating SiC substrate, and retains all the ideal material properties of SiC suitable for high-frequency and high-power applications. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 Fig. 1 is a structural schematic diagram of a gallium nitride transistor in the related art; Figure 2 Fig. 2 is a structural schematic diagram of a gallium nitride transistor according to some embodiments of the application; Figure 3 This is a schematic diagram of the structure of a gallium nitride transistor according to some embodiments of this application; Figure 4 This is a schematic flowchart illustrating a gallium nitride transistor fabrication method according to some embodiments of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] As can be understood, the device structure of a gallium nitride transistor (GaN HEMT) mainly includes a substrate, a buffer layer, a channel layer, and a barrier layer. Common types include depletion-mode and enhancement-mode transistors.

[0019] In depletion-mode gallium nitride (GaN) transistors, a Si substrate is typically used as the substrate, with a high-resistivity GaN crystal layer grown on the Si substrate as the channel layer. An aluminum nitride (AlGaN) insulating layer is usually added between the GaN layer and the Si substrate as a buffer layer to isolate the device from the substrate. The AlGaN layer is located between the GaN layer and the gate, source, and drain electrodes. A two-dimensional electron gas (2DEG) with high electron mobility and low resistance is generated between the AlGaN and GaN layers. At zero gate voltage, the device is in the on-state due to the strong polarization effect of the nitride.

[0020] Enhancement-mode GaN HEMTs are P-type gate structures, meaning a positively charged P-type GaN gate is grown on an AlGaN barrier layer. The P-type GaN layer can pull up the energy band of the AlGaN barrier layer, effectively depleting the 2DEG to achieve normally-off characteristics. When a sufficient positive gate-source voltage (VGS) is applied, the internal electric field of the P-GaN layer is weakened, the 2DEG concentration increases, forming a conduction channel, and the device turns on; when VGS decreases and falls below the threshold voltage, the channel turns off.

[0021] like Figure 1 As shown, regardless of whether it is depletion-mode or enhancement-mode, the GaN HEMT device structure in the related technology is fabricated on a uniform substrate material (Si, SiC, AlN, GaN or sapphire) with a uniform resistivity distribution.

[0022] Therefore, when cost is the main consideration, in order to reduce the cost of the device, a low-cost silicon or sapphire substrate will be selected, which eventually results in a higher vertical leakage, poor dynamic on-resistance performance (device with silicon substrate structure), or poor heat dissipation (device with sapphire substrate).

[0023] In this application, on the basis of ensuring the performance of the device, the cost of the device is reduced, and the cost of the substrate is avoided to bind the performance of the device. The transistor device of the composite substrate of single crystal silicon carbide (the composite SiC substrate composed of a low-cost low-resistivity SiC substrate and an epitaxially grown high-resistivity SiC layer) provided in this application combines all the required material properties of the device, such as high resistivity (semi-insulating SiC > 10 6 Ω·m), high thermal conductivity (SiC > Si > sapphire), and high mechanical strength (SiC > sapphire > Si), which eventually enables the growth of GaN HEMT device structures on a low-cost substrate.

[0024] Figure 2 The structure of the GaN HEMT of some embodiments of the present application is shown.

[0025] As Figure 2 shown, the structure can include: A composite substrate layer and an auxiliary layer and a functional layer disposed on the composite substrate layer. The composite substrate layer includes a base substrate and an epitaxial layer, and the base substrate and the epitaxial layer are single crystal silicon carbide layers, and the resistivity of the epitaxial layer is higher than that of the base substrate.

[0026] Specifically, in order to reduce the cost of the gallium nitride transistor device and ensure the performance of the substrate, such as electrical performance and thermal management performance, a composite structure of the substrate structure is provided, i.e. the structure of the transistor can include a composite substrate layer, an auxiliary layer disposed on the composite substrate layer, and a functional layer on the auxiliary layer.

[0027] The composite substrate layer can include a base substrate and an epitaxial layer, and both are set as single crystal silicon carbide layers to ensure the stability of the structure between the layers.

[0028] In addition, the resistivity of the silicon carbide forming the base substrate is lower than the resistivity of the silicon carbide forming the epitaxial layer.

[0029] For example, the resistivity of the base substrate can be 400 Ω·m, and the resistivity of the epitaxial layer can be 10 6 Ω·m or more. The above resistivity of the base substrate and the epitaxial layer is only an example, and in actual application, it can be flexibly adjusted according to the actual application scene of the device.

[0030] That is, the base substrate in the structure can use a cheap commercial SiC substrate with any background resistivity instead of a high-cost semi-insulating SiC substrate (such as resistivity > 10 5 Ω·m) as a starting base substrate. Further, a semi-insulating single-crystal SiC epitaxial layer (such as thickness > 5 μm, resistivity > 10 6 Ω·m) is grown on the starting SiC substrate with any resistivity.

[0031] It can be understood that, in the gallium nitride transistor of the embodiment of the present application, the substrate of the device is provided as a composite substrate layer including a base substrate with low resistivity and an epitaxial layer with high resistivity, so that the presence of the low-resistivity silicon carbide layer in the base substrate greatly reduces the material cost of the substrate part; and the high-resistivity epitaxial layer formed on the low-resistivity base substrate ensures the electrical performance and thermal management performance of the device substrate. That is, the structure provided by the present application uses a composite SiC substrate composed of a low-cost low-resistivity SiC substrate and an epitaxially grown high-resistivity SiC layer, so that the device combines the high-resistivity, high-thermal-conductivity and high-mechanical-strength performance of silicon carbide and greatly reduces the material cost.

[0032] That is, the gallium nitride transistor provided by the composite SiC substrate structure of the embodiment of the present application is more cost-effective than a uniform semi-insulating SiC substrate and retains all the ideal material properties of SiC suitable for high-frequency and high-power applications.

[0033] Optionally, in some embodiments of the present application, the single-crystal silicon carbide in the composite substrate layer is a 3C, 4H or 6H lattice structure, so that good lattice matching can be achieved between the base substrate and the epitaxial layer, and between the epitaxial layer and the auxiliary layer, ensuring the structural stability of the transistor.

[0034] That is, it can be understood that, in the basic structural unit of single-crystal silicon carbide, the C atoms and Si atoms form Si-C tetrahedrons, and the coordination number of each Si atom and C atom is 4, that is, each C atom is surrounded by 4 Si atoms, and each Si atom is surrounded by 4 C atoms.

[0035] Correspondingly, the Si-C double-atom layers in the SiC crystal are stacked along the

[0001] direction, and due to the small difference in bond energy between layers, different connection modes between atom layers are easily generated, resulting in a large number of types of SiC crystal.

[0036] The silicon carbide crystal type of the base substrate and the epitaxial layer in the substrate of the embodiment of the present application can be selected as 4H-SiC, that is, a 4H crystal structure stacked in the order of “ABCB”, so that when the epitaxial layer is grown on the base substrate, the crystal types between the two can be kept in good matching to ensure the stability of the structure.

[0037] Alternatively, in some other embodiments, the single crystal silicon carbide in the composite substrate layer can select 3C or 6H lattice structure, and the same can ensure good matching between the crystal forms of the layers to ensure the stability of the structure.

[0038] In addition, for the auxiliary layer, i.e. the buffer layer in the gallium nitride transistor, when the aluminum nitride is formed on the epitaxial layer as the buffer layer, the same can realize good matching between the compound structures of the layers through the crystal structure of the single crystal silicon carbide.

[0039] Optionally, in some embodiments of the present application, in order to effectively reduce the cost, the thickness of the base substrate in the composite substrate layer is greater than the thickness of the epitaxial layer.

[0040] For example, the thickness of the base substrate in the composite substrate layer can be 350 μm, and the total thickness of the epitaxial layer can be 10 μm.

[0041] It can be understood that the thickness of the base substrate and the epitaxial layer in the composite substrate can be determined according to actual conditions, i.e. the thickness of the two can be flexibly adjusted according to the requirements for the performance of the device and the cost index.

[0042] Optionally, in some embodiments of the present application, in order to further reduce the cost of the device and ensure the performance of the device, the epitaxial layer can include single or multiple silicon carbide layers, and the resistivity of each layer of silicon carbide gradually increases from the base substrate to the auxiliary layer.

[0043] Specifically, in this embodiment, the epitaxial layer can be set as a multi-layer composite structure, i.e. a single or multi-layer silicon carbide stack structure, and the resistivity of each layer of silicon carbide gradually increases from the base substrate to the auxiliary layer, thereby realizing maximum cost saving and making the resistivity of the single crystal silicon carbide at the top layer of the substrate meet the performance requirements of the device.

[0044] For example, in some embodiments, the thickness of the silicon carbide layer in the stack can be set to 10 μm, and the resistivity gradually increases from the substrate to the functional layer.

[0045] In some embodiments, the resistivity of the silicon carbide layer adjacent to the auxiliary layer is the highest, which can be 10 6 Ω·m or more, and gradually decreases as it approaches the base substrate.

[0046] It can be understood that the gallium nitride transistor provided by the embodiments of the present application realizes maximum cost limitation by setting the epitaxial layer as a multi-layer composite structure with gradually increasing resistivity, i.e. the structure ensures that the place where the top GaN epitaxial layer grows has the highest possible resistivity, and makes the resistivity of the single crystal silicon carbide at the top layer of the substrate meet the performance requirements of the device.

[0047] Optionally, asFigure 2 and Figure 3 As shown in FIG. 1, in the gallium nitride transistor structure, the auxiliary layer is a buffer layer, and the functional layer can include a channel layer and a barrier layer which are stacked on the buffer layer, and a source, a gate and a drain which are patterned on the barrier layer.

[0048] For example, in some embodiments, the buffer layer can be a gallium nitride layer or an aluminum nitride layer, which is used as an auxiliary layer to separate the substrate and the functional layer of the device, so as to relieve the lattice mismatch and thermal stress between the substrate and the channel layer GaN, and reduce the dislocation density.

[0049] That is, the channel layer on the buffer layer can be a high-resistivity gallium nitride layer (for example, the resistivity can be 10 6 Ω·m).

[0050] The barrier layer AlGaN layer is located between the channel layer and the gate, the source and the drain, so that a two-dimensional electron gas with high electron mobility and low resistance characteristics can be generated between the barrier layer and the channel layer. That is, under zero gate voltage, the device is in an on state due to the strong polarization effect of gallium nitride.

[0051] On the other hand, some embodiments of the present application also provide a preparation method of a gallium nitride transistor, which is used to prepare the gallium nitride transistor of each of the above embodiments.

[0052] As shown in FIG. 2, the method can include the following steps: Figure 4 S1, forming an epitaxial layer of single crystal silicon carbide on a base substrate of single crystal silicon carbide, the resistivity of the base substrate being less than the resistivity of the epitaxial layer.

[0053] S2, sequentially stacking an auxiliary layer and a functional layer on the epitaxial layer.

[0054] Specifically, first, an epitaxial layer of single crystal silicon carbide can be formed on a base substrate of single crystal silicon carbide. The epitaxial layer can be formed on the base substrate by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0055] In some embodiments, a single crystal silicon carbide layer with gradually increasing resistivity can be formed on the base substrate to form a composite epitaxial layer structure.

[0056] Further, buffer layer growth can be performed on the epitaxial layer. For example, an AlN or low-temperature GaN buffer layer (the thickness can be hundreds of nanometers) can be grown first to relieve the lattice mismatch and thermal stress between the substrate and the channel layer GaN, and reduce the dislocation density.

[0057] ​Further, a channel layer (GaN) is grown on the buffer layer, such as an intrinsic GaN layer with high resistivity (1-3 μm thick) can be grown, as a channel for electron transport.

[0058] Further, a barrier layer (AlGaN) is grown on the channel layer, such as an AlGaN layer (10-30 nm thick, 20-30% Al composition) can be grown on the GaN channel layer to form a two-dimensional electron gas (2DEG) at the hetero-interface.

[0059] Finally, the electrode structures of the drain, source and gate can be formed in sequence by a photolithography process.

[0060] It can be understood that the GaN transistor provided by the composite SiC substrate structure of the embodiments of the present application is more cost-effective than the uniform semi-insulating SiC substrate, and retains all the ideal material properties of SiC suitable for high-frequency and high-power applications. The three-part (or more) composite SiC substrate can also have different resistivities in each layer, as long as the top has the highest possible resistivity at the location where the GaN epitaxial layer is grown.

[0061] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present disclosure.

[0062] The principles and implementation modes of the present application are described by using specific examples in the present disclosure, and the above descriptions of the embodiments are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation modes and application ranges can be changed according to the idea of the present application. In conclusion, the content of the present disclosure should not be understood as a limitation of the present application.

Claims

1. A gallium nitride transistor, characterized by, Comprise: a composite substrate layer and a gallium nitride auxiliary layer and a functional layer stacked on the composite substrate layer; the composite substrate layer comprises a base substrate and an epitaxial layer, the base substrate and the epitaxial layer are monocrystalline silicon carbide layers, and the resistivity of the epitaxial layer is higher than that of the base substrate.

2. The gallium nitride transistor of claim 1, wherein, The monocrystalline silicon carbide in the composite substrate layer is a 3C, 4H or 6H lattice structure.

3. The gallium nitride transistor of claim 2, wherein, The thickness of the base substrate in the composite substrate layer is greater than the thickness of the epitaxial layer.

4. The gallium nitride transistor of claim 3, wherein, The epitaxial layer comprises a single layer or more than one layer of silicon carbide layer, and the resistivity of each layer of silicon carbide in the multi-layer silicon carbide layer increases from the base substrate to the auxiliary layer.

5. The gallium nitride transistor of claim 4, wherein, The thickness of each silicon carbide layer in the epitaxial layer is 5-50 μm.

6. The gallium nitride transistor of any one of claims 1-5, wherein, The thickness of the base substrate is 300-1000 μm, and the total thickness of the epitaxial layer is 5-300 μm.

7. The gallium nitride transistor of claim 1, wherein, The auxiliary layer is a buffer layer, and the functional layer comprises a channel layer and a barrier layer stacked on the buffer layer, and a source electrode, a gate electrode and a drain electrode patterned on the barrier layer.

8. A method for preparing a gallium nitride transistor, the method being used for preparing the gallium nitride transistor according to any one of claims 1-7, and the method comprising: forming an epitaxial layer of monocrystalline silicon carbide on a base substrate of monocrystalline silicon carbide, the resistivity of the base substrate being less than that of the epitaxial layer; forming an auxiliary layer and a functional layer in sequence on the epitaxial layer.

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