Test circuit board and control method thereof
By combining dual power supply submodules and enhanced drive circuits, the challenge of turn-off failure testing of single-board power semiconductor devices is solved, enabling reliable control and periodic simulation at the single-board level, thus improving testing efficiency and reliability.
Patent Information
- Application Number
- CN202511307004.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2025-11-11
AI Technical Summary
Existing technologies cannot simulate the shutdown failure of power semiconductor devices at the single-board level, making shutdown failure testing difficult and hindering convenient and reliable control and periodic repeatable testing.
By employing a combination of dual power supply submodules and enhanced drive circuits, and through the coordinated operation of the signal receiving module and the switching module, the shutdown failure function of the single-board gate drive unit is simulated. The large current of thousands of amperes is generated for testing by utilizing the cooperation of the isolation drive chip and the switch array.
It realizes reliable control and periodic simulation of single-board gate drive unit, improves test efficiency, ensures fast switching and reliability of controllable switch array, and avoids overheating damage.
Smart Images
Figure CN120928150A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power semiconductor device testing technology, and in particular to a test circuit board and its control method. Background Technology
[0002] Power semiconductor devices, such as integrated gate commutated thyristors (IGCTs), emitter turn-off thyristors (ETOs), gate commutated thyristors (GCTs), and gate turn-off thyristors (GTOs), are used in power systems to achieve power conversion, control, and distribution. They typically consist of a semiconductor chip unit and a gate drive unit. When current-controlled power semiconductor devices are turned off, the gate drive unit commutates the current between the anode and cathode to the anode and gate. This turn-off current is often a large current in the thousands of amperes, and it lacks overcurrent turn-off capability. If the turn-off current exceeds the rated current, the power semiconductor device will fail to turn off. Therefore, to test the turn-off failure of power semiconductor devices, there is currently no way to simulate the turn-off failure of power semiconductor devices on a single board, thus hindering the testing of their turn-off performance. Summary of the Invention
[0003] A test circuit board and its control method are provided, which realizes single-board-level debugging and simulation of the gate drive unit's shutdown failure function.
[0004] In a first aspect, a test circuit board is provided, comprising:
[0005] Signal receiving module 10, the output terminal of signal receiving module 10 is connected to switch module 20;
[0006] Power module 30, the power supply terminal of power module 30 is connected to switch module 20;
[0007] The output terminal of the switch module 20 is connected to the interface module 40;
[0008] The power module 30 includes a first power submodule 301 and a second power submodule 302. The power supply terminal of the first power submodule 301 is connected to the signal receiving module 10 and the second power submodule 302, and the power supply terminal of the second power submodule 302 is connected to the switch module 20.
[0009] In some embodiments, the switch module 20 includes a drive circuit 201 and a switch array 202. The drive circuit 201 is connected to the control terminal of the switch array 202 to drive the switch array 202 to turn on or off.
[0010] In some embodiments, the driving circuit 201 includes an isolation driving sub-circuit 2011 and a driving enhancement sub-circuit 2012. The signal receiving end of the isolation driving sub-circuit 2011 is connected to the output end of the signal receiving module 10, and the output end of the isolation driving sub-circuit 2011 is connected to the input end of the driving enhancement sub-circuit 2012.
[0011] In some embodiments, the drive enhancement sub-circuit 2012 includes a first switch and a second switch. The control terminals of the first switch and the second switch are both connected to the output terminal of the isolation drive sub-circuit 2011. The first end of the first switch and the first end of the second switch are both connected to the control terminal of the switch array 202. The second end of the first switch is connected to one end of the interface module 40, and the second end of the second switch is connected to the power supply terminal of the second power supply sub-module 302.
[0012] In some embodiments, the switch array 202 includes a plurality of controllable switches connected in parallel.
[0013] In some embodiments, the controllable switch is an IGBT or a MOSFET.
[0014] In some embodiments, the multiple controllable switches in the switch array 202 are symmetrically distributed.
[0015] In some embodiments, the signal receiving module 10 includes a receiving device 101 and a processing circuit 102. The receiving device 101 is connected to the input terminal of the processing circuit 102, and the output terminal of the processing circuit 102 is connected to the switching module 20.
[0016] Secondly, this application provides a control method based on the above-described test circuit board, comprising the following steps:
[0017] The switch module 20 turns on or off in response to the control signal received by the signal receiving module 10;
[0018] The signal receiving module 10 is powered by the first power sub-module 301 in the power module 30;
[0019] When the switch module 20 is turned on, the second power sub-module 302 in the power module 30 supplies power to the switch module 20 so that the switch module 20 enters the working state.
[0020] When the switch module 20 is off, the second power submodule 302 in the power module 30 supplies power to the switch module 20 so that the switch module 20 exits the working state.
[0021] In some embodiments, when the switch module 20 is turned on, the second power submodule 302 in the power module 30 supplies power to the switch module 20 so that the switch module 20 enters the working state, including pulling up the voltage of the switch module 20 to a second voltage value.
[0022] In some embodiments, when the switch module 20 is off, the second power submodule 302 in the power module 30 supplies power to the switch module 20 to cause the switch module 20 to exit the working state, including pulling down the voltage of the switch module 20 to the low potential side voltage value of the semiconductor device under test.
[0023] The above technical solution, by employing two interconnected power supply sub-modules and working in conjunction with an enhanced drive circuit, solves the problem that the shutdown failure function of existing gate drive units cannot be debugged at the board level. It achieves reliable control and periodic simulation of the shutdown failure condition of the board-level gate drive unit, thereby improving testing efficiency. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0025] Figure 1 A connection diagram of a test circuit board used in the implementation of this application;
[0026] Figure 2 A connection diagram of another test circuit board used in the implementation of this application;
[0027] Figure 3 This is a schematic diagram of the switching module in the test circuit provided in the embodiments of this application;
[0028] Figure 4 This is a schematic diagram of the drive enhancement sub-circuit provided in the embodiments of this application;
[0029] Figure 5 This is a schematic diagram of the power module structure in an embodiment of this application;
[0030] Figure 6 This is a schematic diagram of the structure of the signal receiving module provided in the embodiments of this application;
[0031] Explanation of icon numbers:
[0032] 10-Signal receiving module; 101-Receiver device; 102-Processing circuit; 20-Switch module; 201-Driver circuit; 2011-Isolation driver sub-circuit; 2012-Drive enhancement sub-circuit; 202-Switch array; 30-Power supply module; 301-First power supply sub-module; 302-Second power supply sub-module; 40-Interface module. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0034] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.
[0035] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.
[0036] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.
[0037] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0038] Under current testing conditions, the shutdown failure function of the gate drive unit cannot be directly verified at the board level. It can only be verified by reverse engineering during module-level operational testing, where the power semiconductor device actually experiences a shutdown failure. This verification is achieved through methods such as waveform recording, waveform analysis, and identifying module damage points. Currently, board-level verification faces two main challenges: firstly, generating / simulating a large current of several thousand amperes flowing through the commutation circuit of the gate drive unit to simulate its normal shutdown failure condition; secondly, achieving convenient and reliable control and enabling periodic, repeatable testing and verification.
[0039] Therefore, embodiments of this application provide a test circuit board and its control method, realizing reliable control and periodic simulation of the turn-off failure condition of the single-board-level gate drive unit. The power semiconductor devices applicable to this application include IGCT, ETO, GCT, or GTO.
[0040] Figure 1 A connection diagram of a test circuit board used in the implementation of this application is provided, as shown below. Figure 1 As shown, the test circuit board provided in this embodiment includes:
[0041] Signal receiving module 10, the output terminal of signal receiving module 10 is connected to switch module 20; power supply module 30, the power supply terminal of power supply module 30 is connected to switch module 20; output terminal of switch module 20 is connected to interface module 40;
[0042] The power module 30 includes a first power submodule 301 and a second power submodule 302. The power supply terminal of the first power submodule 301 is connected to the signal receiving module 10 and the second power submodule 302, and the output terminal of the second power submodule 302 is connected to the switch module 20. The power module 30 outputs two voltages, wherein the first power submodule 301 outputs a first voltage V. cc First voltage V cc The second power supply submodule 302 is used to power the signal receiving module 10 and the switching module 20, and outputs a second voltage V. cc1 The second voltage V cc1 Used to supply power to the switching module 20. In this embodiment, the signal receiving module 10 receives control signals sent by the gate drive unit.
[0043] Figure 2 Another connection diagram for use of the test circuit board provided for the implementation of this application is shown below. Figure 2 As shown, in some embodiments, the signal receiving module 10 receives control signals sent by the host computer.
[0044] The first interface of interface module 40 is used to connect to the gate of the power semiconductor device, and the second interface of interface module 40 is used to connect to the cathode of the power semiconductor device. The first and second interfaces can be annular, rectangular, or square. The first and second interfaces can respectively cover the upper and lower layers of the test circuit board, and are symmetrical vertically. Holes for copper studs to pass through are provided in the areas covered by the first and second interfaces. The first and second interfaces can also be located on the same side of the test circuit board. The shape and position of the first and second interfaces must match the shape and position of the gate interface and cathode interface in the gate driver circuit board of the semiconductor device.
[0045] In some embodiments, both the first and second interfaces are made of copper sheets, and the power semiconductor devices are connected to the test circuit through direct contact during testing.
[0046] In some embodiments, the first interface and the second interface can respectively cover the upper and lower layers of the test circuit board. The first interface and the second interface are symmetrical, and the areas covered by the first interface and the second interface have holes for copper studs to pass through. During testing, the gate interface of the semiconductor device gate driver circuit board is attached to the first interface of the test circuit board, and the second interface is connected to the cathode interface of the semiconductor device gate driver circuit board by copper studs and nuts. A spring and a washer are also provided between the nut and the test circuit board or the semiconductor device gate driver circuit board, which enables a more reliable connection between the interface of the test circuit board and the interface of the power semiconductor device.
[0047] In some embodiments, the first interface and the second interface are located on the same side of the test circuit board. During testing, the gate interface of the semiconductor device gate driver circuit board is attached to the first interface of the test circuit board, and the cathode interface of the semiconductor device gate driver circuit board is attached to the second interface of the test circuit board. A clamping device is provided on both sides of the attachment point to press and fix the attachment surfaces. This enables a more reliable connection between the interface of the test circuit board and the interface of the power semiconductor device.
[0048] In some embodiments, Figure 3 This is a schematic diagram of the switching module in the test circuit provided in the embodiments of this application, such as... Figure 3 As shown, the switch module 20 includes a drive circuit 201 and a switch array 202. The drive circuit 201 is connected to the control terminal of the switch array 202 to drive the switch array 202 to turn on or off.
[0049] In some embodiments, such as Figure 3As shown, the driving circuit 201 includes an isolation driving sub-circuit 2011 and a driving enhancement sub-circuit 2012. The signal receiving end of the isolation driving sub-circuit 2011 is connected to the output end of the signal receiving module 10, and the output end of the isolation driving sub-circuit 2011 is connected to the input end of the driving enhancement sub-circuit 2012.
[0050] Specifically, the isolation driver sub-circuit 2011 includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, and an isolation driver chip U1. The first pin of the isolation driver chip U1 is connected to the output terminal of the first power supply sub-module 301. The second pin of the isolation driver chip U1 is connected to the output terminal of the signal receiving module and the first terminal of the first resistor R1. The second terminal of the first resistor R1 is grounded. The third and fourth pins of the isolation driver chip U1 are both grounded. The fifth pin of the isolation driver chip U1 is connected to the interface module 40. The sixth pin of the isolation driver chip U1 is connected to the first terminal of the second resistor R2. The seventh pin of the isolation driver chip U1 is connected to the first terminal of the third resistor R3. The second terminal of the second resistor R2 is connected to the second terminal of the third resistor R3, the anode of the first diode D1, and the cathode of the second diode D2. The cathode of the first diode D1 is connected to the output terminal of the second power supply sub-module 302. The anode of the second diode D2 is grounded. The eighth pin of the isolation driver chip U1 is connected to the output terminal of the second power supply sub-module 302. The second terminal of the second resistor R2 is the output terminal.
[0051] The isolation driver chip is a single-channel, isolated IGBT / MOSFET gate driver chip. The first pin of this chip is the input-side power supply, used to connect to the power supply on the microcontroller side. In this embodiment, the first pin is connected to the first voltage V in the power module 30. cc The first pin is connected to the output terminal; the second pin is the input terminal of the non-inverting driver, active high; the third pin is the input terminal of the inverting driver, active low; the fourth pin is the input-side ground reference point; the fifth pin is the output-side ground reference point; the sixth pin is the output pin; the seventh pin is the output pin; and the eighth pin is the output-side power supply reference point. When the input signal Ctr is low, the low level output by the isolation driver chip is the cathode potential K; when the input signal Ctr is high, the high level output by the isolation driver chip is the second voltage V. cc1 .
[0052] In some embodiments, Figure 4 This is a schematic diagram of the drive enhancement sub-circuit provided in the embodiments of this application, such as... Figure 4As shown, the drive enhancement sub-circuit 2012 includes a first switch Q1 and a second switch Q2. The control terminals of both the first switch Q1 and the second switch Q2 are connected to the output terminal of the isolation drive sub-circuit 2011. The first terminal of the first switch Q1 and the first terminal of the second switch Q2 are both connected to the control terminal of the switch array 202. The second terminal of the first switch Q1 is connected to one end of the interface module 40, and the second terminal of the second switch Q2 is connected to the output terminal of the second power supply sub-module 302. The second terminal of the first switch Q1 is connected to the second interface in the interface module 40, so that when the test circuit board is working, the second terminal of the first switch Q1 is equivalent to being connected to the cathode of the power semiconductor device.
[0053] When the control signal Drive output by the isolation driver sub-circuit 2011 is high, the first switch Q1 is turned on, the second switch Q2 is turned off, and the control terminal of the switch array 202 is pulled down to the cathode potential K of the power semiconductor device, thus turning off the switch array 202. When the control signal Drive output by the isolation driver sub-circuit 2011 is low, the first switch Q1 is turned off, the second switch Q2 is turned on, and the control terminal of the switch array 202 is pulled up to the second voltage V. cc1 Then the switch array 202 is turned on. The driving capability of the drive enhancement sub-circuit 2012 can be increased from the level of several amperes to the level of hundreds of amperes, ensuring the fast switching of the controllable switch array, avoiding damage to the controllable switch array due to overheating, and improving the reliability of the controllable element array; the first switch Q1 is an enhancement-type P-channel MOSFET, and the second switch Q2 is an enhancement-type N-channel MOSFET.
[0054] In some embodiments, the switch array 202 includes a plurality of controllable switches connected in parallel. The control terminal of the switch array 202 controls the control terminals of all controllable switches. When the switch array 202 starts working, all controllable switches are turned on. When the switch array 202 stops working, all controllable switches are turned off.
[0055] In some embodiments, the controllable switch is an IGBT or a MOSFET.
[0056] In some embodiments, the multiple controllable switches in the controllable switch array are symmetrically distributed. Specifically, the multiple controllable switches in the controllable switch array can be symmetrically distributed left and right, or symmetrically distributed on the top and bottom of the circuit board.
[0057] In some embodiments, Figure 5 This is a schematic diagram of the power module structure in an embodiment of this application, as shown below. Figure 5 As shown, the first power supply submodule 301 supplies power to the chip in the second power supply submodule 302, and the first power supply submodule 301 outputs a first voltage V. ccThe second power supply submodule 302 outputs the second voltage V. cc1 .
[0058] Among them, such as Figure 5 As shown, the second power supply submodule 302 includes a first inductor L1, a second inductor L2, a third diode D3, a fourth resistor R4, and a first isolation power supply U2. The first terminal of the first isolation power supply U2 is connected to the first terminal of the first inductor L1, the second terminal of the first inductor L1 is connected to the output terminal of the first power supply submodule 301, the second terminal of the first isolation power supply U2 is grounded, the third terminal of the first isolation power supply U2 is connected to the first terminal of the second inductor L2, the second terminal of the second inductor L2 is connected to the anode of the third diode D3, the cathode of the third diode D3 is connected to the first terminal of the fourth resistor R4, the second terminal of the fourth resistor R4 is connected to the cathode of the power semiconductor device, the fourth terminal of the first isolation power supply U2 is connected to the cathode of the power semiconductor device, and the cathode of the third diode D3 is the output terminal. The second power supply submodule 302 outputs a second voltage V. cc1 The second power supply submodule 302 is based on the cathode of a power semiconductor device as a reference potential and can provide a second voltage V. cc1 An isolated voltage source is required. Without the second power supply submodule 302, the switching module 20 cannot be controlled to turn on. Specifically, taking an IGCT device as an example, the potential difference between the test circuit board reference ground GND and the cathode K of the IGCT is approximately 20V.
[0059] In some embodiments, the first isolated power supply can be a DC / DC isolated power supply chip, such as F_XT-2WR2, or a power supply built using an isolation transformer, such as a flyback power supply. The first isolated power supply is used to connect with the first voltage V. cc Isolation, generating a second voltage V cc1 .
[0060] In some embodiments, Figure 6 This is a schematic diagram of the structure of the signal receiving module provided in the embodiments of this application, such as... Figure 6 As shown, the signal receiving module 10 includes a receiving device 101 and a processing circuit 102. The receiving device 101 is connected to the input terminal of the processing circuit 102, and the output terminal of the processing circuit 102 is connected to the switching module 20.
[0061] In some embodiments, the receiving device 101 is an optical device, wherein the output pin of the optical device is connected to the input terminal of the processing circuit 102. The receiving device 101 may also be a combination of a specific port and a cable for implementing electrical connection, such as a combination of a coaxial connector and a coaxial cable.
[0062] like Figure 6As shown, the processing circuit 102 includes a fifth resistor R5, a sixth resistor R6, a fourth diode D4, a fifth diode D5, and a first gate circuit U3. The output terminal of the receiving device 101 is connected to the first terminal of the fifth resistor R5, the first terminal of the sixth resistor R6, the anode of the fourth diode D4, and the cathode of the fifth diode D5, respectively. The second terminal of the fifth resistor R5 and the cathode of the fourth diode D4 are both connected to the output terminal of the first power supply submodule 301. The anode of the fifth diode D5 is grounded. The second terminal of the sixth resistor R6 is connected to the input terminal of the first gate circuit U3. The output terminal of the first gate circuit U3 is connected to the input terminal of the switching module. The processing circuit 102 is used to modulate the command signal received by the receiving device 101, such as inverting and level conversion. The first gate circuit U3 is a NOT gate circuit. The fourth diode D4 and the fifth diode D5 are used to protect the port of the first gate circuit U3, limiting the input signal of the first gate circuit U3 to -0.7V to V. cc Between +0.7V.
[0063] This application provides a control method for a test circuit board, including the following steps:
[0064] Step 1: The signal receiving module 10 receives the control signal from the gate drive unit of the power semiconductor device to turn on the switch module 20. During operation, the first power supply submodule 301 in the power supply module 30 supplies power to the signal receiving module 10;
[0065] Step 2: In response to the control signal received by the signal receiving module 10, the drive enhancement sub-circuit 2012 in the switch module 20 pulls up the voltage at the control terminal of the switch array 202 to the second voltage VCC1, thus turning on the switch array 202 and enabling it to operate. The switch module 20 then enters the working state. At this time, the test circuit board can generate a large current of several thousand amperes flowing through the gate drive unit, thus performing a gate drive unit turn-off failure test.
[0066] Step 3: The signal receiving module 10 receives the control signal from the gate drive unit of the power semiconductor device to turn off the switch module 20.
[0067] Step 4: In response to the control signal received by the signal receiving module 10, the drive enhancement sub-circuit 2012 in the switch module 20 pulls down the voltage at the control terminal of the switch array 202 to the cathode potential of the power semiconductor device. The switch array 202 then turns off, ceases operation, and the switch module 20 exits its operating state. At this time, the main drive capability test of the gate drive unit is performed.
[0068] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.
Claims
1. A test circuit board, characterized in that, include: A signal receiving module (10) is provided, the output of which is connected to a switch module (20). A power supply module (30), the power supply terminal of which is connected to the switch module (20); Interface module (40), the output terminal of the switch module (20) is connected to the interface module (40); The power module (30) includes a first power submodule (301) and a second power submodule (302). The power supply terminal of the first power submodule (301) is connected to the signal receiving module (10) and the second power submodule (302), and the power supply terminal of the second power submodule (302) is connected to the switch module (20).
2. The test circuit board according to claim 1, characterized in that, The switching module (20) includes a driving circuit (201) and a switch array (202). The driving circuit (201) is connected to the control terminal of the switch array (202) to drive the switch array (202) to turn on or off.
3. The test circuit board according to claim 2, characterized in that, The driving circuit (201) includes an isolation driving sub-circuit (2011) and a driving enhancement sub-circuit (2012). The signal receiving end of the isolation driving sub-circuit (2011) is connected to the output end of the signal receiving module (10), and the output end of the isolation driving sub-circuit (2011) is connected to the input end of the driving enhancement sub-circuit (2012).
4. The test circuit board according to claim 3, characterized in that, The drive enhancement sub-circuit (2012) includes a first switch and a second switch. The control terminals of the first switch and the second switch are both connected to the output terminal of the isolation drive sub-circuit (2011). The first end of the first switch and the first end of the second switch are both connected to the control terminal of the switch array (202). The second end of the first switch is connected to one end of the interface module (40), and the second end of the second switch is connected to the power supply terminal of the second power supply sub-module (302).
5. The test circuit board according to claim 2, characterized in that, The switch array (202) includes multiple controllable switches connected in parallel.
6. The test circuit board according to claim 5, characterized in that, The controllable switch is an IGBT or a MOSFET.
7. The test circuit board according to claim 5, characterized in that, The multiple controllable switches in the switch array (202) column are symmetrically distributed.
8. The test circuit board according to claim 1, characterized in that, The signal receiving module (10) includes a receiving device (101) and a processing circuit (102). The receiving device (101) is connected to the input terminal of the processing circuit (102), and the output terminal of the processing circuit (102) is connected to the switching module (20).
9. The control method for the test circuit board according to claim 1, characterized in that, Includes the following steps: The switch module (20) turns on or off in response to a control signal received by the signal receiving module (10); The signal receiving module (10) is powered by the first power sub-module (301) in the power module (30); When the switch module (20) is turned on, the second power submodule (302) in the power module (30) supplies power to the switch module (20) so that the switch module (20) enters the working state; When the switch module (20) is off, the second power submodule (302) in the power module (30) supplies power to the switch module (20) so that the switch module (20) exits the working state.
10. The control method according to claim 9, characterized in that, When the switch module (20) is turned on, the second power submodule (302) in the power module (30) supplies power to the switch module (20) so that the switch module (20) enters the working state, including pulling up the voltage of the switch module (20) to a second voltage value.
11. The control method according to claim 9, characterized in that, When the switch module (20) is off, the second power submodule (302) in the power module (30) supplies power to the switch module (20) to make the switch module (20) exit the working state, including pulling down the voltage of the switch module (20) to the low potential side voltage value of the semiconductor device under test.