Driving substrate, preparation method thereof and display panel

Abstract

The invention provides a driving substrate, a preparation method thereof and a display panel, and relates to the technical field of display, the driving substrate comprises a binding area, and the binding area comprises a substrate, a conductive pattern, a first flat layer, a second flat layer and a conductive wire; the conductive pattern is located in the substrate partial region; the first flat layer covers the edge area of the conductive pattern; the second flat layer covers the conductive pattern and the first flat layer; the conductive wire is located on the side, away from the substrate, of the second flat layer, at least part of the conductive wire is located in a first area, and the first area is an area where orthographic projections of the conductive pattern, the first flat layer and the conductive wire on the substrate are overlapped; in the normal direction perpendicular to the substrate, the distance between the part, located in the first area, of the surface, away from the substrate, of the first flat layer and the substrate is larger than the minimum distance between the surface, away from the substrate, of the conductive pattern and the substrate, and the surface, away from the substrate, of the second flat layer is a plane; the driving substrate is used for preparing high-quality display products.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving substrate and its preparation method, and a display panel. Background Technology

[0002] With the continuous development of display technology, people's requirements for display panel performance are becoming increasingly stringent. In the composition of display panel architecture, the driving substrate plays a crucial role. Currently, in the touch-integrated technology system, due to the large step difference between different functional film layers under the conductive traces in certain areas, protrusions are formed on the surface of the film layers in these areas. When forming conductive traces in these areas, due to the high fluidity of the photoresist, the photoresist applied to the protruding parts will be thinner. During the etching process, it is easy to etch through the photoresist in the protruding parts, resulting in over-etching of the conductive traces and defects such as short circuits or open circuits. This, in turn, affects the stability of signal transmission and ultimately reduces the performance and production yield of the driving substrate.

[0003] This application aims to provide a novel driving substrate structure to solve the aforementioned problems existing in the related technologies. Summary of the Invention

[0004] This application provides a driving substrate and its fabrication method, as well as a display panel, which aims to improve the performance and yield of the driving substrate through a unique structural design.

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a driving substrate, the driving substrate including a bonding region, the bonding region comprising:

[0007] Base;

[0008] A conductive pattern is located in a portion of the substrate;

[0009] A first planar layer covers the edge region of the conductive pattern;

[0010] A second planarization layer covers the conductive pattern and the first planarization layer;

[0011] The conductive trace is located on the side of the second planarization layer away from the substrate, and at least a portion of the conductive trace is located in a first region, which is the area where the orthographic projections of the conductive pattern, the first planarization layer, and the conductive trace on the substrate overlap.

[0012] Wherein, along the direction perpendicular to the normal of the substrate, the distance between the portion of the surface of the first flat layer away from the substrate located in the first region and the substrate is greater than the minimum distance between the surface of the conductive pattern away from the substrate and the substrate, and the surface of the second flat layer away from the substrate is planar.

[0013] In some driving substrates provided in this application, the conductive pattern includes a first conductive pattern and a second conductive pattern;

[0014] The second conductive pattern is located on the side of the first conductive pattern away from the substrate, and at least a portion of the two are in direct contact.

[0015] In some driving substrates provided in this application, the orthographic projection of the second conductive pattern on the substrate is located within the orthographic projection of the first conductive pattern on the substrate.

[0016] In some driving substrates provided in this application, in the first region, the second conductive pattern and the orthographic projection of the first conductive pattern on the substrate do not overlap.

[0017] In some driving substrates provided in this application, the first region includes a flat region and an arc region, wherein the flat region is located on the side of the arc region away from the second conductive pattern;

[0018] In the flat region, the surface of the second flat layer near the substrate is planar;

[0019] In some driving substrates provided in this application, the second conductive pattern covers the first conductive pattern, and the second conductive pattern extends to cover the portion of the first planarization layer located in the first region.

[0020] In some driving substrates provided in this application, the first region includes a first edge region, a second edge region, and a central region, wherein the central region is located between the first edge region and the second edge region;

[0021] The thickness of the portion of the second flattening layer located in the central region is less than the thickness of the portion of the second flattening layer located in the first edge region, and the thickness of the portion of the second flattening layer located in the central region is less than the thickness of the portion of the second flattening layer located in the second edge region.

[0022] In some driving substrates provided in this application, the conductive pattern can be used to form at least one of the following structures: display signal lines, power signal lines, and clock signal lines; the conductive traces can be used to form at least one of the following structures: multiple connection lines for connecting the driving chip and the flexible circuit board.

[0023] Secondly, embodiments of this application provide a display panel including a driving substrate as described in any one of the first aspects.

[0024] Thirdly, embodiments of this application provide a method for fabricating a driving substrate, applicable to fabricating a driving substrate as described in any one of the first aspects, the method comprising:

[0025] Provide a base;

[0026] Forming the first conductive pattern;

[0027] A first planarization layer is formed, which covers the edge region of the first conductive pattern;

[0028] A second conductive pattern is formed, the second conductive pattern being located on the side of the first conductive pattern away from the substrate, and at least a portion of the two are in direct contact;

[0029] A second planarization layer is formed, covering the first conductive pattern, the second conductive pattern, and the first planarization layer;

[0030] A conductive trace is formed, at least a portion of which is located in a first region, the first region being an area where the conductive pattern, the first planarization layer and the orthographic projection of the conductive trace on the substrate overlap;

[0031] In the first region, along the direction perpendicular to the normal of the substrate, the distance between the surface of the first flat layer away from the substrate and the substrate is greater than the distance between the surface of the conductive pattern away from the substrate and the substrate, and the surface of the second flat layer away from the substrate is planar.

[0032] Beneficial effects:

[0033] This application provides a driving substrate and its fabrication method, as well as a display panel. The driving substrate includes a bonding region, which comprises: a substrate, a conductive pattern, a first planarization layer, a second planarization layer, and conductive traces. The conductive pattern is located in a portion of the substrate. The first planarization layer covers the edge region of the conductive pattern. The second planarization layer covers the conductive pattern and the first planarization layer. The conductive traces are located on the side of the second planarization layer away from the substrate, and at least a portion of the conductive traces is located in a first region. The first region is a region where the orthographic projections of the conductive pattern, the first planarization layer, and the conductive traces on the substrate overlap. Along the normal direction perpendicular to the substrate, the distance between the portion of the surface of the first planarization layer away from the substrate located in the first region and the substrate is greater than the minimum distance between the surface of the conductive pattern away from the substrate and the substrate, and the surface of the second planarization layer away from the substrate is planar.

[0034] In practical applications, the surface of the first planarization layer away from the substrate has a large step difference with the surfaces of other films away from the substrate in the first region. When the second planarization layer is formed, the second planarization layer will form a large protrusion in the first region. In related technologies, when conductive traces are fabricated in this region, due to the flowability of the material, the photoresist coated in the first region will be relatively thin. In subsequent etching processes, it is easy to etch through the photoresist in the first region, corrode the conductive traces, and cause the conductive traces in this region to be over-etched, resulting in damage or breakage.

[0035] This application designs the structure of each film layer in the bonding region of the driving substrate. For example, when there is a step difference between the surface of the first planarization layer away from the substrate in the first region and the surface of the adjacent region away from the substrate, the surface of the first region away from the second planarization layer is set as a plane. In this way, during the fabrication of conductive traces, the photoresist coating thickness is uniform, and the etching gas or etching liquid in the subsequent etching process is not easy to penetrate the photoresist. This improves the problem of damage or breakage of conductive traces due to over-etching, improves the continuity of conductive traces, and enhances the stability of the driving substrate.

[0036] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of a drive substrate bonding area structure provided for an embodiment of this application;

[0039] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the A1A2 direction;

[0040] Figure 3 A schematic diagram of a cross-sectional structure of the bonding region of a driving substrate is provided as an embodiment of this application;

[0041] Figure 4 A schematic diagram illustrating the fabrication principle of the second planarization layer film provided for embodiments of this application;

[0042] Figure 5 A flowchart illustrating a method for fabricating a driving substrate, as provided in the embodiments of the application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0045] In the embodiments of this application, the use of terms such as "first" and "second" to describe the same or similar items with essentially the same function and effect is only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0046] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. "At least one" refers to one or more, and "more than one" refers to at least two.

[0047] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0048] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0049] With the rapid development of display technology, people have increasingly stringent requirements for the performance of display panels. In the composition of the display panel, the driving substrate plays a key role. It is responsible for accurately transmitting various electrical signals and is the core component that ensures the normal operation of the display panel.

[0050] Traditional driving substrates employ a multi-layer stacked structure, where adjacent layers are edge-wrapped to form a perimeter covering structure. This structure easily leads to protrusions at the perimeter. Touch On Cell (TSP) technology, due to its ability to directly perform touch-related processes on the functional layer stack, offers advantages such as thinness, high sensitivity, and low power consumption, making it a significant development direction for display panels. However, in the actual production process of TSP, conductive traces require the formation of a conductive film, followed by uniform application of photoresist, exposure and development to form a photoresist pattern, and finally etching to form a conductive pattern. Because of the high fluidity of the photoresist, protrusions on the driving substrate result in thinner photoresist at the top of the protrusions during photolithography, leading to lower protrusion areas. In subsequent etching processes, this can cause problems such as over-etching of metal and trace breakage, affecting signal transmission stability and severely impacting the performance and yield of the display panel.

[0051] Currently, the industry is attempting to cover raised terrain by increasing the thickness of the photoresist to avoid the formation of step differences in the photoresist at the raised areas. However, this approach prolongs the exposure processing time in the photolithography process, leading to lost factory capacity, reduced production efficiency, and increased production costs.

[0052] Based on this, this application provides a novel driving substrate. The driving substrate provided in this application will now be described and explained in detail with reference to the accompanying drawings.

[0053] Embodiments of this application provide a driving substrate, combined with Figure 1 and Figure 2 As shown, the driving substrate includes a bonding area, which includes:

[0054] Base;

[0055] Conductive pattern 3 is located in a portion of the substrate;

[0056] An insulating layer 1 is located in a portion of the substrate and extends to cover the edge region of the conductive pattern 3;

[0057] The first flattening layer 2 covers the edge region of the conductive pattern 3;

[0058] The second planarization layer 4 covers the conductive pattern 3 and the first planarization layer 2;

[0059] The conductive trace 5 is located on the side of the second planarization layer 4 away from the substrate, and at least a portion of the conductive trace 5 is located in the first region B, which is the region where the orthographic projections of the conductive pattern 3, the first planarization layer 2, and the conductive trace 5 on the substrate overlap.

[0060] In this context, along the direction perpendicular to the substrate, the distance H1 between the portion of the surface of the first flattening layer 2 away from the substrate located in the first region B and the substrate is greater than the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate, and the surface of the second flattening layer 4 away from the substrate is planar.

[0061] The driving substrate of this application includes a substrate, a conductive pattern 3, a first planarization layer 2, a second planarization layer 4, and conductive traces 5.

[0062] Among them, the substrate, as the basic support structure of the entire substrate, utilizes its low cost, good insulation and high surface flatness to lay the foundation for the good performance of the driving substrate.

[0063] For example, the substrate can be a rigid substrate or a flexible substrate.

[0064] For example, the flexible substrate can be made of highly flexible and lightweight polyimide material, which has excellent flatness and chemical stability, and can provide a stable and reliable support foundation for the entire drive substrate.

[0065] For example, rigid substrates can be made of glass or silicon, which have excellent mechanical strength and thermal stability, providing a solid support platform for circuits.

[0066] For example, the conductive pattern 3 can be a display signal line, power signal line, or clock signal line in the bonding area. The conductive pattern 3 is prepared by photolithography using a metal material with low resistivity. It is the physical carrier of the current path and the basis for the stable operation of the entire substrate circuit.

[0067] For example, the driving substrate may include a first source-drain conductive layer (SD1), and the conductive pattern 3 is located in the first source-drain conductive layer;

[0068] For example, the driving substrate may include a first source-drain conductive layer (SD1) and a second source-drain conductive layer (SD2), and the conductive pattern 3 is located in the first source-drain conductive layer and / or the second source-drain conductive layer.

[0069] For example, the material of the conductive pattern 3 can be a metal, such as copper, gold, silver, etc.

[0070] The first planarization layer 2 and the second planarization layer 4 are made of organic insulating materials. By laying the planarization layer, the height difference of the lower film can be eliminated, ensuring the uniformity of subsequent film preparation.

[0071] For example, the first planarization layer 2 and the second planarization layer 4 can be made of organic materials, such as polyimide, epoxy resin, etc.

[0072] The conductive trace 5 is located on the side of the second planarization layer 4 away from the substrate, and is used to form a conductive channel between the driver chip and the flexible circuit board, providing a stable signal transmission path.

[0073] The first region B, meaning the overlapping area where the orthographic projections of the conductive pattern 3, the first planarization layer 2, and the conductive trace 5 on the substrate exist, can include the following situations:

[0074] First scenario: Part of the conductive trace 5 is located in the first region B;

[0075] The second scenario: The entire area of ​​conductive trace 5 is located in the first area B.

[0076] Furthermore, the distance H1 between the portion of the surface of the first planarization layer 2 away from the substrate and the substrate in the first region B is greater than the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate. The minimum distance H2 refers to:

[0077] When the conductive pattern 3 includes a first conductive pattern 31 and a second conductive pattern 32, such as Figure 2 or Figure 3 As shown, in the region where the second conductive pattern 32 is in direct contact with the first conductive pattern 31, the distance H1 between the surface of the second conductive pattern 32 away from the substrate and the substrate.

[0078] For example, the difference between the distance H1 between the portion of the surface of the first planar layer 2 away from the substrate located in the first region B and the substrate and the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate ranges from 1.3 micrometers to 1.7 micrometers.

[0079] In practical applications, the distance H1 between the portion of the first planarization layer 2 away from the substrate in the first region B and the substrate is greater than the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate. Thus, the first planarization layer 2 in the first region B has a large step difference with the conductive pattern 3 in the adjacent region. After the second planarization layer 4 is formed in this region, it will have a large protrusion. In related technologies, if it is necessary to form a conductive trace 5 in this region, a conductive film is first formed on the second planarization layer 4, and then a photoresist pattern is formed as a mask for etching. Due to the high fluidity of the photoresist pattern material, the photoresist pattern formed in the first region B will be relatively thin. During the etching process, the etching liquid or etching gas can easily penetrate the photoresist pattern in the first region B, thereby corroding the conductive trace 5, causing the conductive trace 5 in this region to be over-etched and damaged or broken.

[0080] Currently, the industry is trying to cover the raised terrain by increasing the thickness of the photoresist to avoid the photoresist forming a step difference at the raised part. However, this solution will prolong the exposure processing time in the photolithography process, resulting in factory capacity loss, reduced production efficiency, and increased production costs.

[0081] In the embodiments of this application, such as Figure 2 or Figure 3 As shown, when the distance H1 between the portion of the surface of the first planarization layer 2 away from the substrate in the first region B and the substrate is greater than the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate, the surface of the second planarization layer 4 away from the substrate in the first region B is set as a plane. In this way, during the subsequent formation of the conductive trace 5, a conductive film is first formed on the second planarization layer 4, and then a photoresist pattern is formed as a mask for etching. The leveling thickness of the photoresist pattern is more uniform. During the etching process, the etching liquid or etching gas is less likely to cause over-etching in local areas, thereby improving the problem of damage or breakage of the conductive trace 5 due to over-etching.

[0082] In some of the driving substrates provided in this application, such as Figure 2 or Figure 3 As shown, the conductive pattern 3 includes a first conductive pattern 31 and a second conductive pattern 32; the second conductive pattern 32 is located on the side of the first conductive pattern 31 away from the substrate, and at least a portion of the two are in direct contact.

[0083] Wherein, the second conductive pattern 32 is located on the side of the first conductive pattern 31 away from the substrate, and at least a portion of the two are in direct contact, which may include the following situations:

[0084] The first scenario: (e.g.) Figure 2 As shown, the entire area of ​​the second conductive pattern 32 is in contact with the first conductive pattern 31;

[0085] The second scenario: Figure 3 As shown, a portion of the second conductive pattern 32 is in contact with the first conductive pattern 31.

[0086] In practical applications, when using a single-layer conductive pattern to achieve electrical connections between different layers of circuits, it is necessary to form a vertical conductive channel in the multi-layer structure through via technology to precisely align the via with this conductive pattern. If the via position deviates from the conductive pattern, it will lead to an open circuit or poor contact.

[0087] In the embodiments of this application, the use of a double-layer conductive pattern, the first conductive pattern 31 and the second conductive pattern 32, can enable the first conductive pattern 31 and the second conductive pattern 32 to form a stable electrical connection through direct physical contact. By designing overlapping redundant areas in the first conductive pattern 31 or the second conductive pattern 32, slight alignment errors can be effectively compensated for, and the complexity and defect rate of traditional via processes can be reduced.

[0088] In some of the driving substrates provided in this application, such as Figure 2 As shown, the orthographic projection of the second conductive pattern 32 on the substrate is located within the orthographic projection of the first conductive pattern 31 on the substrate.

[0089] In the embodiments of this application, the orthographic projection of the second conductive pattern 32 on the substrate is located within the orthographic projection of the first conductive pattern 31 on the substrate. This allows the edge electrons of the second conductive pattern 32 to move laterally from the edge to the first conductive pattern 31, effectively reducing the contact resistance of the current path and optimizing signal transmission efficiency.

[0090] In some of the driving substrates provided in this application, such as Figure 2 As shown, in the first region B, the orthographic projections of the second conductive pattern 32 and the first conductive pattern 31 on the substrate do not overlap.

[0091] In practical applications, the second conductive pattern 32 extends to cover the portion of the first planarization layer 2 located in the first region B, which will significantly increase the total thickness of the film between the second planarization layer 4 and the substrate in the first region B. When the second planarization layer 4 is subsequently formed, its material will spread along the undulating state of the underlying film structure, causing the second planarization layer 4 to form a protrusion on the surface of the first region B away from the substrate.

[0092] In the embodiments of this application, by setting the second conductive pattern 32 and the first conductive pattern 31 in the first region B such that their orthogonal projections on the substrate do not overlap, the superposition thickness of multiple film layers in the first region B can be effectively reduced, providing a smoother substrate for the subsequent preparation of the second planarization layer 4, thereby enabling the second planarization layer 4 to flow more uniformly, and further making the surface of the second planarization layer 4 away from the substrate a plane.

[0093] In some of the driving substrates provided in this application, such as Figure 2 As shown, the first region B includes a flat region B1 and an arc region B2. The flat region B1 is located on the side of the arc region B2 away from the second conductive pattern 32. In the flat region B1, the surface of the second flat layer 4 near the substrate is planar. In the arc region B2, the thickness H3 of the portion of the second flat layer 4 away from the second conductive pattern 32 is greater than the thickness H4 of the portion of the second flat layer 4 near the second conductive pattern 32.

[0094] In the embodiments of this application, adjusting the portion of the second flattening layer 4 located on the surface near the substrate in the flattening region B1 to be planar can reduce the step difference between the surface of the second flattening layer 4 located on the surface near the substrate in the flattening region B1 and the surfaces of adjacent film layers, allowing the second flattening layer 4 to be more uniformly leveled during fabrication, and further making the surface of the second flattening layer 4 away from the substrate planar. By setting the thickness H3 of the portion of the second flattening layer 4 away from the second conductive pattern 32 in the arc region B2 to be greater than the thickness H4 of the portion of the second flattening layer 4 near the second conductive pattern 32, the stepped structure at the edge of the second flattening layer 4 can be effectively smoothed, transforming its originally abrupt step difference into a gentle height transition.

[0095] When fabricating conductive traces 5, a conductive film is first formed on the second planarization layer 4, then photoresist is coated on the conductive film, followed by exposure and development to form a photoresist pattern, and finally etching to form conductive traces 5.

[0096] By designing the film structure of the flat region B1 and the arc region B2, a smoother substrate can be provided for the subsequent fabrication of the conductive trace 5. Based on this, uniform photoresist coating can be achieved in the fabrication process, and in the etching process, the etching liquid or etching gas is less likely to cause over-etching in local areas, thereby effectively improving the problem of damage or breakage of the conductive trace 5 due to over-etching.

[0097] In some of the driving substrates provided in this application, such as Figure 3 As shown, the second conductive pattern 32 covers the first conductive pattern 31, and the second conductive pattern 32 extends to cover the portion of the first flat layer 2 located in the first region B.

[0098] In the embodiments of this application, using the second conductive pattern 32 to extend and cover the first planarization layer 2 to form an edge-wrapped covering structure has multiple technical advantages. On the one hand, by increasing the contact area between the second conductive pattern 32 and the first planarization layer 2, the stress concentration at the edge of the film layer is effectively dispersed, the mechanical stability of the overall structure is enhanced, and the risk of edge peeling caused by temperature changes or mechanical impacts in subsequent processes is reduced. On the other hand, the edge-wrapped structure can form a physical barrier, effectively blocking environmental moisture and chemical corrosives from intruding from the edge of the first planarization layer 2, avoiding the film layer performance degradation problem caused by this, and providing a reliable technical guarantee for the manufacturing of high-performance drive substrates.

[0099] In some driving substrates provided in this application, the first region B includes a first edge region B4, a second edge region B5 and a central region B3, with the central region B3 located between the first edge region B4 and the second edge region B5.

[0100] The thickness H5 of the portion of the second flattening layer 4 located in the central region B3 is less than the thickness H7 of the portion of the second flattening layer 4 located in the first edge region B4, and the thickness H5 of the portion of the second flattening layer 4 located in the central region B3 is less than the thickness H6 of the portion of the second flattening layer 4 located in the second edge region B5.

[0101] In some embodiments, due to the leveling properties of the material of the second flattening layer 4, the thickness of the second flattening layer 4 can gradually decrease in the direction from the central region B3 toward the edge regions on both sides.

[0102] In the embodiments of this application, when preparing the conductive trace 5, a conductive film is first formed on the second planarization layer 4, then photoresist is coated on the conductive film, followed by exposure and development to form a photoresist pattern, and finally etching to form the conductive trace.

[0103] By setting the thickness H5 of the second planarization layer 4 in the central region B3 to be less than the thickness H7 of the second planarization layer 4 in the first edge region B4, and the thickness H5 of the second planarization layer 4 in the central region B3 to be less than the thickness H6 of the second planarization layer 4 in the second edge region B5, the protrusions in the first region B caused by the difference in film thickness between the second planarization layer 4 and the substrate can be effectively balanced. This ensures that the surface of the second planarization layer 4 away from the substrate can still maintain an overall flatness, providing a smoother substrate for the subsequent fabrication of conductive traces 5. Based on this, uniform coating can be achieved during subsequent photoresist coating, and during the etching process, the etching liquid or etching gas is less likely to cause over-etching in local areas, thereby effectively improving the problem of damage or breakage of conductive traces 5 due to over-etching.

[0104] In some driving substrates provided in this application, the conductive pattern 3 can be used to form at least one of the following structures: display signal lines, power signal lines, and clock signal lines; the conductive trace 5 can be used to form at least one of the following structures: multiple connection lines for connecting the driving chip and the flexible circuit board.

[0105] For example, the display signal line may include a data signal line (Data);

[0106] For example, the power signal lines may include a first power signal line ELVDD, a second power signal line ELVSS, a ground line GND, a third power signal line VGL, a fourth power signal line VGH, etc.

[0107] In the embodiments of this application, the conductive pattern 3 and conductive trace 5 are prepared by photolithography using a metal material with low resistivity. They are the physical carriers of the current path and the basis for the stable operation of the entire substrate circuit.

[0108] This application provides a display device including a driving substrate as described in the foregoing embodiments.

[0109] The display device provided in this application embodiment can achieve the same technical effect as the driving substrate in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0110] The display device provided in this application can be any product or component with display function, such as a display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc.

[0111] In some examples, the display panel provided in the embodiments of this application can be an OLED (Organic Light-Emitting Diode) display panel, wherein the OLED display panel can include a glass-based OLED display panel and a silicon-based OLED display panel.

[0112] In some examples, the display panel provided in the embodiments of this application can be an LCD (Liquid Crystal Display) display panel, which has multiple display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode.

[0113] Embodiments of this application provide a method for fabricating a driving substrate, applicable to the fabrication of the driving substrate described above, such as... Figure 5 As shown, the method includes:

[0114] S1, Provide the substrate;

[0115] S2, Form the first conductive pattern 31;

[0116] In practical applications, after the first conductive pattern 31 is formed, an insulating layer 1 can be formed on the substrate, and the insulating layer 1 extends to cover the edge area of ​​the first conductive pattern 31.

[0117] S3. Form a first planarization layer 2, which covers the edge region of the first conductive pattern 31.

[0118] S4. A second conductive pattern 32 is formed, the second conductive pattern 32 is located on the side of the first conductive pattern 31 away from the substrate, and at least a portion of the two are in direct contact.

[0119] S5. Form a second planarization layer 4 to cover the first conductive pattern 31, the second conductive pattern 32 and the first planarization layer 2;

[0120] S6. Form conductive trace 5, at least a portion of the conductive trace 5 is located in the first region B, the first region B is the region where the orthographic projections of the conductive pattern, the first planarization layer 2 and the conductive trace 5 on the substrate overlap.

[0121] In the first region B, along the direction perpendicular to the substrate, the distance H1 between the surface of the first flattening layer 2 away from the substrate and the substrate is greater than the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate, and the surface of the second flattening layer 4 away from the substrate is planar.

[0122] like Figure 2 or Figure 3 As shown, in the driving substrate prepared by the method of this application, when the distance H1 between the portion of the surface of the first planarization layer 2 away from the substrate located in the first region B and the substrate is greater than the minimum distance H2 between the surface of the conductive pattern 3 away from the substrate and the substrate, the surface of the second planarization layer 4 away from the substrate in the first region B is set as a plane. In this way, during the subsequent formation of the conductive traces 5, a conductive thin film is first formed on the second planarization layer 4, and then a photoresist pattern is formed as a mask for etching. The leveling thickness of the photoresist pattern is more uniform. During the etching process, the etching liquid or etching gas is less likely to cause over-etching in local areas, thereby improving the problem of damage or breakage of the conductive traces 5 due to over-etching.

[0123] The following is based on Figure 2 Taking the structure shown as an example, the specific fabrication method of this driving substrate is explained:

[0124] 1. A first conductive thin film is formed on a substrate, wherein the material of the first conductive thin film can be a metal, such as copper, gold, silver, etc.

[0125] 2. Coating photoresist, then exposing and developing to form a photoresist pattern, using the photoresist pattern as a mask to etch the first conductive film to form the first conductive pattern 31.

[0126] 3. A patterned insulating layer 1 is formed on the substrate through coating, exposure, development and etching processes. The insulating layer 1 can be an organic material, such as polyimide, epoxy resin, etc.

[0127] 4. A first planarization layer 2 is formed by a coating process. The first planarization layer 2 covers the insulating layer 1. The material of the first planarization layer can be an organic material, such as polyimide, epoxy resin, etc.

[0128] 5. A patterned second conductive pattern 32 is formed on the first conductive pattern 31.

[0129] In the first region B, the orthographic projections of the second conductive pattern 32 and the first conductive pattern 31 onto the substrate do not overlap.

[0130] 6. A second planarization layer 4 is formed through coating, exposure, development, and etching processes. The material of the second planarization layer 4 can be an organic material, such as polyimide, epoxy resin, etc.

[0131] The surface of the second flat layer 4, away from the substrate, is planar.

[0132] 7. Conductive traces 5 are formed on the second planarization layer 4 by photolithography.

[0133] The following is based on Figure 3 Taking the structure shown as an example, another specific fabrication method for this driving substrate is illustrated:

[0134] 1. A first conductive thin film is formed on a substrate, wherein the material of the first conductive thin film can be a metal, such as copper, gold, silver, etc.

[0135] 2. Coating photoresist, then exposing and developing to form a photoresist pattern, using the photoresist pattern as a mask to etch the first conductive film to form the first conductive pattern 31.

[0136] 3. A patterned insulating layer 1 is formed on the substrate through coating, exposure, development and etching processes. The insulating layer 1 can be an organic material, such as polyimide, epoxy resin, etc.

[0137] 4. A first planarization layer 2 is formed by photolithography. The first planarization layer 2 covers the insulating layer 1. The material of the first planarization layer can be an organic material, such as polyimide, epoxy resin, etc.

[0138] 5. A patterned second conductive pattern 32 is formed on the first conductive pattern 31.

[0139] The second conductive pattern 32 extends to cover the portion of the first flat layer 2 located in the first region B.

[0140] 6. A second planarization layer 4 is formed through coating, exposure, development, and etching processes. The material of the second planarization layer 4 can be an organic material, such as polyimide, epoxy resin, etc.

[0141] like Figure 4 As shown, during the preparation of the second planarization layer 4, the transmittance of the mask in the first region B during the exposure process is greater than that of the surrounding region, and the transmittance of the mask in the central region B3 is greater than that of the mask in the first edge region B4, and the transmittance of the mask in the central region B3 is greater than that of the mask in the second edge region B5.

[0142] The thickness H5 of the portion of the second flattening layer 4 located in the central region B3 is less than the thickness H7 of the portion of the second flattening layer 4 located in the first edge region B4, and the thickness H5 of the portion of the second flattening layer 4 located in the central region B3 is less than the thickness H6 of the portion of the second flattening layer 4 located in the second edge region B5.

[0143] The surface of the second flat layer 4, away from the substrate, is planar.

[0144] It should be noted that, Figure 4 The mask and the structure of the second planarization layer 4 shown are for illustrative purposes only. In practical applications, the mask pattern structure can be appropriately adjusted according to the film layer structure between the substrate and the second planarization layer 4.

[0145] 7. Conductive traces 5 are formed on the second planarization layer 4 by photolithography.

[0146] It should be noted that the aforementioned driving substrate may also include other structures and components, and its fabrication method may also include other steps and processes. This specification only describes the structures and fabrication methods related to the inventive point. Other structures and their fabrication methods can be found in the descriptions in related technologies.

[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driving substrate, characterized in that, Includes a binding area, the binding area including: Base; A conductive pattern is located in a portion of the substrate; A first planar layer covers the edge region of the conductive pattern; A second planarization layer covers the conductive pattern and the first planarization layer; The conductive trace is located on the side of the second planarization layer away from the substrate, and at least a portion of the conductive trace is located in a first region, which is the area where the orthographic projections of the conductive pattern, the first planarization layer, and the conductive trace on the substrate overlap. Wherein, along the direction perpendicular to the normal of the substrate, the distance between the portion of the surface of the first flat layer away from the substrate located in the first region and the substrate is greater than the minimum distance between the surface of the conductive pattern away from the substrate and the substrate, and the surface of the second flat layer away from the substrate is planar.

2. The driving substrate according to claim 1, characterized in that, The conductive pattern includes a first conductive pattern and a second conductive pattern. The second conductive pattern is located on the side of the first conductive pattern away from the substrate, and at least a portion of the two are in direct contact.

3. The driving substrate according to claim 2, characterized in that, The orthographic projection of the second conductive pattern on the substrate lies within the orthographic projection of the first conductive pattern on the substrate.

4. The driving substrate according to claim 3, characterized in that, In the first region, the second conductive pattern and the orthographic projection of the first conductive pattern onto the substrate do not overlap.

5. The driving substrate according to claim 4, characterized in that, The first region includes a flat region and an arc region, wherein the flat region is located on the side of the arc region away from the second conductive pattern; In the flat region, the surface of the second flat layer near the substrate is planar.

6. The driving substrate according to claim 2, characterized in that, The second conductive pattern covers the first conductive pattern, and the second conductive pattern extends to cover the portion of the first flat layer located in the first region.

7. The driving substrate according to claim 6, characterized in that, The first region includes a first edge region, a second edge region, and a central region, wherein the central region is located between the first edge region and the second edge region; The thickness of the portion of the second flattening layer located in the central region is less than the thickness of the portion of the second flattening layer located in the first edge region, and the thickness of the portion of the second flattening layer located in the central region is less than the thickness of the portion of the second flattening layer located in the second edge region.

8. The driving substrate according to any one of claims 1 to 7, characterized in that, The conductive pattern can be used to form at least one of the following structures: display signal lines, power signal lines, and clock signal lines; the conductive traces can be used to form at least one of the following structures: multiple connection lines for connecting the driver chip and the flexible circuit board.

9. A display panel, characterized in that, Includes the driving substrate as described in any one of claims 1 to 8.

10. A method for fabricating a driving substrate, characterized in that, The method is applied to the preparation of a driving substrate as described in any one of claims 2 to 8, and includes: Provide a base; Forming the first conductive pattern; A first planarization layer is formed, which covers the edge region of the first conductive pattern; A second conductive pattern is formed, the second conductive pattern being located on the side of the first conductive pattern away from the substrate, and at least a portion of the two are in direct contact; A second planarization layer is formed, covering the first conductive pattern, the second conductive pattern, and the first planarization layer; A conductive trace is formed, at least a portion of which is located in a first region, the first region being an area where the conductive pattern, the first planarization layer and the orthographic projection of the conductive trace on the substrate overlap; Wherein, along the direction perpendicular to the normal of the substrate, the distance between the portion of the surface of the first flat layer away from the substrate located in the first region and the substrate is greater than the minimum distance between the surface of the conductive pattern away from the substrate and the substrate, and the surface of the second flat layer away from the substrate is planar.

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