Method for optimizing barrier layer deposition
By optimizing the barrier layer deposition through a two-step resputtering method, the contradiction between barrier layer sidewall coverage and bottom layer protection in existing technologies is resolved, thereby improving the high performance and reliability of copper interconnect structures and enhancing the electrical performance and stability of semiconductor products.
Patent Information
- Application Number
- CN202511063695.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-11
AI Technical Summary
In existing technologies, single-step argon resputtering processes are difficult to simultaneously cover the sidewalls of the barrier layer and protect the underlying structure during the formation of copper interconnect structures, resulting in physical damage or copper sputtering contamination, which affects device reliability and electrical performance.
A two-step resputtering method is adopted, first using argon plasma to enhance sidewall coverage, and then using helium plasma to reduce bottom damage. Combined with physical vapor deposition and thermal annealing processes, the barrier layer deposition is optimized.
It significantly improves the coverage quality of the barrier layer within the recessed morphology, reduces damage to the underlying structure, enhances the electrical performance and long-term reliability of the copper interconnect structure, and improves the yield and stability of semiconductor products.
Smart Images
Figure CN120933237A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for optimizing barrier layer deposition. Background Technology
[0002] In modern integrated circuit manufacturing, especially after entering the 90-nanometer and more advanced technology nodes, copper has widely replaced aluminum as the main material for back-end metal interconnects due to its excellent conductivity and resistance to electromigration. Copper interconnect structures are typically manufactured using the damascus process, which involves etching trenches and / or vias in a dielectric layer and then filling these structural features with conductive metal.
[0003] Before copper filling, one or more conformal barrier layers and seed layers must be deposited. The main function of the barrier layer (typically a tantalum nitride / tantalum stack structure, TaN / Ta) is to prevent copper atoms from diffusing into the adjacent dielectric material, as copper diffusion can lead to dielectric degradation and even device failure. In addition, the barrier layer also enhances the adhesion between the copper and the dielectric layer. The seed layer (usually a thin layer of copper) provides a conductive substrate for subsequent electrochemical copper plating.
[0004] Barrier layers and seed layers are typically formed using physical vapor deposition (PVD). After depositing the TaN / Ta barrier layer, a one-step plasma resputtering process is commonly employed in existing technologies. This typically uses a heavier inert gas, such as argon, to bombard the bottom of the structural feature (e.g., vias or trenches). The main purposes of this argon resputtering are twofold: first, to sputter and redeposit some of the barrier layer material deposited at the bottom of the structural feature onto the sidewalls, improving the coverage and thickness of the sidewall barrier layer and enhancing the barrier effect; and second, to help remove residues or oxides from the bottom of the structural feature, reducing the contact resistance between subsequently formed upper and lower metal layers (e.g., copper at the bottom of a via and copper filling the via).
[0005] However, traditional single-step argon resputtering processes have inherent limitations. To achieve effective redeposition of the bottom material to the sidewalls and bottom cleaning, relatively high argon plasma energy or bombardment intensity is required. However, intense argon bombardment can cause physical or plasma-induced damage to the material beneath the structural features (typically underlying metal interconnects, such as copper, or exposed low-dielectric-constant dielectric layers), affecting the device's electrical performance and long-term reliability. In particular, excessive bombardment energy can not only damage the underlying structure but may also sputter the underlying copper metal itself, potentially depositing it on the sidewalls of vias or trenches, leading to difficulties in subsequent copper filling or introducing reliability issues (such as poor interface bonding, increased leakage risk, or impaired electromigration performance).
[0006] On the other hand, if the energy or intensity of argon resputtering is reduced in order to mitigate damage to the bottom layer, it may result in insufficient removal of the bottom barrier layer material, affecting the reduction effect of contact resistance Rc. At the same time, the material redeposition efficiency on the sidewalls will also be reduced, which may result in insufficient coverage of the sidewall barrier layer.
[0007] Therefore, how to effectively improve the sidewall coverage of the barrier layer and reduce contact resistance while avoiding or significantly reducing damage to the underlying structure and unintended sputtering of the underlying copper is a challenge faced by barrier layer deposition technology in current advanced copper interconnect processes. Summary of the Invention
[0008] This application aims to address the problems existing in the current barrier layer deposition process, particularly in the formation of copper interconnect structures, when using single-step resputtering (e.g., argon Ar resputtering) to treat barrier layers such as tantalum nitride / tantalum (TaN / Ta). The existing single-step resputtering process faces a dilemma in simultaneously achieving sidewall coverage enhancement and underlying structure protection: while high-energy bombardment can effectively sputter the bottom barrier layer material to the sidewalls, improving sidewall coverage, it can also easily cause physical or plasma-induced damage to the underlying metal (e.g., copper) or dielectric layer at the bottom of recessed morphologies (e.g., vias, trenches), and may even backsputter the underlying metal (e.g., copper) to the sidewalls, affecting barrier layer purity and performance, thereby reducing device reliability; conversely, reducing bombardment energy can reduce damage, but may lead to insufficient improvement in sidewall coverage and incomplete removal of the bottom barrier layer material, affecting contact resistance.
[0009] Therefore, this application provides a method for optimizing barrier layer deposition, the purpose of which is to effectively improve the coverage performance of the barrier layer in the concave topography (especially on the sidewalls), while significantly reducing the damage to the bottom of the concave topography and the structure below it during the resputtering process, and avoiding or reducing backsputtering contamination of the underlying conductive material (such as copper), thereby improving the overall performance and reliability of the final metal interconnect structure.
[0010] To achieve the above and other related objectives, the present invention provides a method for optimizing barrier layer deposition, comprising:
[0011] Step 1: On a substrate containing a pre-layer structure and having a recessed morphology formed in the pre-layer structure, a barrier layer structure is deposited within the recessed morphology.
[0012] Step two: After depositing the barrier layer structure, the barrier layer structure undergoes a first sputtering process using argon plasma; and
[0013] Step 3: After the first sputtering process, a second sputtering process is performed on the barrier layer structure using helium plasma.
[0014] Preferably, in step one, the deposition barrier layer structure includes a tantalum nitride layer and a tantalum layer deposited sequentially.
[0015] Preferably, in step one, the deposition barrier layer structure is deposited using a physical vapor deposition method.
[0016] Preferably, the recessed morphology includes a groove or a through-hole that extends through at least a portion of the front layer structure and exposes the underlying conductive layer.
[0017] Preferably, the underlying conductive layer comprises copper.
[0018] Preferably, in step two, the first resputtering process is used to sputter the barrier layer material deposited at the bottom of the depression onto the sidewall of the depression.
[0019] Preferably, in step two, the process conditions for the first sputtering treatment include: AC bias power of 900 to 1100 W, DC bias power of 400 to 600 W, cavity temperature of 20 to 30 degrees Celsius, and cavity pressure of 2*10-4 to 2*10-4 Pa.
[0020] Preferably, in step three, the second sputtering process is used to reduce damage to the bottom of the concave topography and the material below it.
[0021] Preferably, in step three, the second sputtering process is used to reduce the amount of copper in the underlying conductive layer sputtered onto the sidewalls of the recessed topography.
[0022] Preferably, in step three, the process conditions for the second resputtering process include: an AC bias power of 900 to 1100 W, a DC bias power of 400 to 600 W, a cavity temperature of 20 to 30 degrees Celsius, and a cavity pressure of 2*10-4 to 2*10-4 Pa.
[0023] Preferably, prior to step one, the substrate is further subjected to a degassing treatment and / or a pre-cleaning treatment.
[0024] Preferably, after step four, a step of performing thermal annealing is also included.
[0025] As described above, the optimized barrier layer deposition method of the present invention has the following beneficial effects:
[0026] The two-step resputtering method proposed in this application first utilizes efficient Ar resputtering to primarily enhance sidewall coverage, and then uses mild He resputtering for final bottom treatment, minimizing damage and backsputtering of the underlying material. This balances the needs for enhanced sidewall coverage and bottom protection. Compared to the traditional single-step Ar resputtering process, this method can significantly reduce damage to the bottom metal / dielectric layer, avoid excessive bottom copper sputtering to the sidewalls, and simultaneously ensure or improve the overall filling capability of the barrier layer within the recessed morphology, especially the coverage quality of the sidewalls. Ultimately, this helps improve the electrical performance (such as reducing contact resistance Rc) and long-term reliability (such as electromigration resistance and leakage characteristics) of the copper interconnect structure, thereby improving the yield and stability of semiconductor products. Attached Figure Description
[0027] Figure 1 The diagram shown is a schematic representation of the process flow of this invention. Detailed Implementation
[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] Please see Figure 1 This application provides a method for optimizing barrier layer deposition, comprising the following steps:
[0030] Step 1: On a substrate containing a pre-layer structure and within which a recessed morphology is formed, a barrier layer structure is deposited within the recessed morphology. The pre-layer structure may include, for example, a pre-formed dielectric layer, underlying metal interconnects, or other semiconductor device structures. The recessed morphology is pre-etched to allow for subsequent filling with conductive material (such as copper) to form metal interconnects (such as wires or vias).
[0031] In some embodiments, prior to step one, a degassing and / or pre-cleaning process is performed on the substrate. Degassing helps remove adsorbed moisture or other volatiles from the substrate surface, preventing contamination and interface problems in subsequent processes, especially in high-vacuum PVD environments.
[0032] Pre-cleaning treatments, such as plasma cleaning, can effectively remove the natural oxide layer or other residual contaminants on the subsequent deposition interface, ensuring good physical and electrical contact between the subsequently deposited barrier layer structure and the substrate. This is crucial for reducing contact resistance and improving device reliability.
[0033] In some embodiments, the recessed morphology includes a groove or a through-hole, the groove typically used to form horizontal wiring of metal wires, and the through-hole used to vertically connect metal wires of different layers, the groove or through-hole extending through at least a portion of the front layer structure and exposing the underlying conductive layer.
[0034] In some embodiments, the underlying conductive layer comprises copper. Vias need to be filled with copper to connect to the underlying copper conductors, and the deposition quality of the barrier layer directly affects the performance and reliability of the copper interconnect.
[0035] In some embodiments, step one, the deposition of the barrier layer structure includes the sequential deposition of a tantalum nitride (TaN) layer and a tantalum (Ta) layer. The TaN layer primarily serves as an excellent copper barrier, preventing copper from diffusing into the surrounding dielectric material, while also exhibiting good adhesion to the dielectric layer. The Ta layer, on the other hand, can bond well with the subsequently deposited copper seed layer, providing a good interface for electrochemical copper plating.
[0036] In some embodiments, in step one, the deposition of the barrier layer structure includes deposition using a physical vapor deposition (PVD) method.
[0037] Step 2: After depositing the barrier layer structure, an argon (Ar) plasma is used to perform a first sputtering treatment on the barrier layer structure. This step uses argon plasma to bombard the barrier layer structure that has just been deposited within the depression morphology (including the bottom and sidewalls).
[0038] In some embodiments, in step two, the first sputtering process is used to sputter the barrier layer material deposited at the bottom of the recessed morphology onto the sidewalls of the recessed morphology. Argon gas has a relatively large atomic mass and high plasma bombardment energy, effectively sputtering the TaN / Ta material deposited at the bottom of the recessed morphology (especially vias or high aspect ratio trenches) and redepositing it onto the sidewalls of the recessed morphology through a specific angular distribution. This process significantly enhances the coverage thickness of the barrier layer on the sidewalls, improves the uniformity and density of the sidewall coverage, thereby improving the overall structure's ability to block copper diffusion. The purpose of using Ar gas is its high sputtering yield and good redeposition efficiency, enabling faster enhancement of the sidewall coverage.
[0039] In some embodiments, in step two, the process conditions for the first sputtering treatment include: an AC bias power of 900 to 1100 W, a DC bias power of 400 to 600 W, a cavity temperature of 20 to 30 degrees Celsius, and a cavity pressure of 2 × 10⁻⁴ to 2 × 10⁻⁴ Pa. In this step, the bombardment energy and directionality of Ar ions can be precisely controlled by adjusting the AC or DC bias applied to the substrate. A relatively medium or high bias level needs to be set to provide sufficient energy (e.g., above the sputtering threshold of TaN / Ta) to effectively sputter the bottom barrier layer material, and the ion directionality introduced by the bias guides the sputtered particles, promoting their redeposition onto the sidewalls of the recessed morphology, thereby enhancing sidewall coverage. Precise control of the bias is key to balancing sputtering efficiency and avoiding excessive damage.
[0040] Step 3: Following the first sputtering process, a second sputtering process using helium (He) plasma is performed on the barrier layer structure. This is immediately followed by the first Ar resputtering, leading to the second resputtering process using helium plasma.
[0041] In some embodiments, in step three, the second sputtering process is used to reduce damage to the bottom of the recessed morphology and the material beneath it. Helium (He) is the least heavy inert gas, and its physical bombardment capability is far lower than that of argon. Using He plasma for the second sputtering step can significantly reduce physical damage (such as lattice damage) and plasma-induced damage to the exposed material (such as a copper conductive layer or a sensitive low-dielectric-constant medium) at the bottom of the recessed morphology and below it, without significantly sacrificing or even possibly continuing to slightly clean the bottom interface.
[0042] In some embodiments, in step three, the second sputtering process is also used to reduce the sputtering of copper from the underlying conductive layer onto the sidewalls of the recessed morphology. This is another important advantage of using He for the second sputtering step. Strong Ar bombardment can not only damage the underlying layer but also sputter the bombarded copper atoms from the underlying layer and deposit them onto the sidewalls of the recessed morphology, forming so-called "copper sputtering contamination." This can seriously affect the purity and performance of the barrier layer and may even lead to voids or interface problems in subsequent copper plating. He's physical bombardment is much gentler and can effectively avoid or significantly reduce this backsputtering phenomenon of the underlying copper, thereby protecting the integrity and effectiveness of the sidewall barrier layer and reducing adverse effects on subsequent process steps.
[0043] In some embodiments, in step three, the process conditions for the second sputtering process include: an AC bias power of 900 to 1100 W, a DC bias power of 400 to 600 W, a cavity temperature of 20 to 30 degrees Celsius, and a cavity pressure of 2 × 10⁻⁴ to 2 × 10⁻⁴ Pa. In this step, the applied AC or DC bias is also adjusted, but the goal is to set a relatively low bias level. This allows for precise control of the bombardment energy of very light He ions, keeping it within a low, carefully controlled range. This energy level needs to be below the threshold that would cause significant physical damage to the underlying copper or dielectric layer, and insufficient to effectively sputter heavier copper atoms, thereby achieving the core objectives of reducing bottom damage and suppressing copper backsputtering. Simultaneously, this low bias still provides sufficient driving force to guide He ions to the bottom of the recessed morphology for gentle processing.
[0044] In summary, the two-step resputtering method proposed in this application balances the needs of sidewall coverage enhancement and bottom protection by first using efficient Ar resputtering to primarily enhance sidewall coverage, and then using mild He resputtering for final bottom treatment while minimizing damage and backsputtering of the underlying material. Compared to the traditional single-step Ar resputtering process, this method can significantly reduce damage to the bottom metal / dielectric layer, avoid excessive bottom copper sputtering to the sidewalls, and ensure or improve the overall filling capability of the barrier layer within the recessed morphology, especially the coverage quality of the sidewalls. Ultimately, this helps to improve the electrical performance (such as reducing contact resistance Rc) and long-term reliability (such as anti-electromigration capability and leakage characteristics) of the copper interconnect structure, thereby improving the yield and stability of semiconductor products.
[0045] In some embodiments, after step three, a step of performing rapid thermal annealing of tantalum is further included. This step can be performed after barrier layer deposition and resputtering, for example using a rapid thermal annealing (RTA) apparatus. By rapidly heating and cooling the deposited Ta layer, its microstructure can be improved, such as promoting grain growth or phase transformation, potentially reducing its sheet resistance and enhancing its properties as a substrate for subsequent copper seed layer deposition, improving the adhesion and stability of the Ta / Cu interface. This is beneficial for the electrical performance and reliability of the overall interconnect structure.
[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for optimizing barrier layer deposition, characterized in that, At least including: Step 1: On a substrate containing a pre-layer structure and having a recessed morphology formed in the pre-layer structure, a barrier layer structure is deposited within the recessed morphology. Step two: After depositing the barrier layer structure, the barrier layer structure undergoes a first sputtering process using argon plasma; and Step 3: After the first sputtering process, a second sputtering process is performed on the barrier layer structure using helium plasma.
2. The method for optimizing barrier layer deposition according to claim 1, characterized in that: In step one, the deposition barrier layer structure includes a tantalum nitride layer and a tantalum layer deposited sequentially.
3. The method for optimizing barrier layer deposition according to claim 1 or 2, characterized in that: In step one, the deposition barrier layer structure is deposited using a physical vapor deposition method.
4. The method for optimizing barrier layer deposition according to claim 1, characterized in that: The recessed morphology includes grooves or through holes that extend through at least a portion of the front layer structure and expose the underlying conductive layer.
5. The method for optimizing barrier layer deposition according to claim 4, characterized in that: The underlying conductive layer comprises copper.
6. The method for optimizing barrier layer deposition according to claim 1, characterized in that: In step two, the first sputtering process is used to sputter the barrier layer material deposited at the bottom of the depression onto the sidewall of the depression.
7. The method for optimizing barrier layer deposition according to claim 1, characterized in that: In step two, the process conditions for the first sputtering process include: AC bias power of 900 to 1100 W, DC bias power of 400 to 600 W, cavity temperature of 20 to 30 degrees Celsius, and cavity pressure of 2*10-4 to 2*10-4 Pa.
8. The method for optimizing barrier layer deposition according to claim 1, characterized in that: In step three, the second sputtering process is used to reduce damage to the bottom of the concave topography and the material below it.
9. The method for optimizing barrier layer deposition according to claim 5, characterized in that: In step three, the second sputtering process is used to reduce the amount of copper in the underlying conductive layer sputtered onto the sidewalls of the recessed topography.
10. The method for optimizing barrier layer deposition according to claim 1, characterized in that: In step three, the process conditions for the second sputtering process include: AC bias power of 900 to 1100 W, DC bias power of 400 to 600 W, cavity temperature of 20 to 30 degrees Celsius, and cavity pressure of 2*10-4 to 2*10-4 Pa.
11. The method for optimizing barrier layer deposition according to claim 1, characterized in that: Prior to step one, the substrate is further subjected to degassing and / or pre-cleaning treatment.
12. The method for optimizing barrier layer deposition according to claim 1, characterized in that: Following step four, a thermal annealing step is also included.