Level switching circuit and chip

Abstract

The present application relates to the technical field of integrated circuit design, and relates to a level switching circuit and a chip, which solves the main current contention problem through an up-down pull driving network of a current mirror type structure, uses a transmission tube to shorten the circuit conversion reaction time and reduce the static current of an inverter, simultaneously forms a feedback delay network through an input and an output, inserts a novel feedback switch tube in a current mirror branch, and makes the feedback delay network control the switch tube to realize low static current. In addition, a novel feedback controlled clamping tube is added to the up-down pull driving network, the clamping tube uses a transistor with a high threshold and a small width-length ratio to compensate the influence of the switch tube on the up-down pull driving network, makes the output node Q1 have a full voltage swing, thereby improving the level switching speed and energy utilization efficiency, improving the system stability and reducing the static current of a next stage inverter, and effectively improving the comprehensive switching performance of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to a level switching circuit and chip. Background Technology

[0002] In integrated circuits, level switching circuits are typically used to switch voltages between different voltage domains during signal transmission. For example, in memory chips, as operating frequencies increase, level switching circuits need to have fast switching capabilities to meet the transmission rate requirements of high-speed signals, while simultaneously achieving low power consumption to meet the application requirements of mobile devices and low-power memories. Traditional level switching circuit designs often employ cross-coupling structures. However, when the voltage levels differ significantly between different voltage domains, severe current contention arises, leading to either inability to switch normally or excessively long switching times. To address this, researchers have proposed current mirror level switching circuits. While this circuit solves the current contention problem, it suffers from a large quiescent current when the input signal IN is high, resulting in insufficient overall switching performance. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a level switching circuit and a memory chip, which can effectively improve the overall switching performance of the circuit and has advantages such as high speed, low static power consumption and full output swing.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a level switching circuit is provided, including a feedback delay network, a transmission transistor, a switching transistor, a current mirror, a pull-down transistor, a clamping transistor, and an output inverter. The power supply terminal of the feedback delay network, the source of the current mirror, and the source of the clamping transistor are all used to connect to the high voltage domain voltage. The ground terminal of the feedback delay network is grounded, and the source of the pull-down transistor is grounded.

[0006] The first control input terminal of the feedback delay network is used to receive the input signal. The second control input terminal of the feedback delay network is connected to the output terminal of the output inverter. The output terminal of the feedback delay network is connected to the gate of the switching transistor and the gate of the clamping transistor, respectively. The drain of the first transistor of the current mirror is connected to the drain of the transmission transistor through the switching transistor. The gate of the transmission transistor is used to receive the low voltage domain voltage. The source of the transmission transistor and the gate of the pull-down transistor are both used to receive the input signal. The input terminal of the output inverter is connected to the third control input terminal of the feedback delay network, the output terminal of the clamping transistor, the output terminal of the current mirror, and the drain of the pull-down transistor, respectively.

[0007] The feedback delay network is used to control the switching transistor and clamping transistor to eliminate quiescent current based on the input signal, the input signal of the output inverter, and the output signal of the output inverter, respectively. The clamping transistor is used to compensate for the influence of the switching transistor on the pull-up and pull-down drive network. The width-to-length ratio of the switching transistor and the transmission transistor is less than the width-to-length ratio of the transistors in the pull-up and pull-down drive network but greater than the width-to-length ratio of the other transistors in the circuit.

[0008] In one embodiment, the feedback delay network includes transistors MP4, MP5, MN4, and MN5. The sources of transistors MP4 and MP5 are both used to connect to a high-voltage domain voltage. The gate of transistor MP4 is connected to the output terminal of the output inverter, and the gate of transistor MP5 is connected to the input terminal of the output inverter. The drain of transistor MP4 is connected to the drain of transistor MN4 and the gate of transistor MN5. The drain of transistor MP5 is connected to the drain of transistor MN5, the gate of the switching transistor, and the gate of the clamping transistor. The gate of transistor MN4 is used to connect to the input signal, and the sources of transistors MN4 and MN5 are both grounded.

[0009] In one embodiment, the current mirror includes transistor MP1 and transistor MP2, the source of transistor MP1 and the source of transistor MP2 are both used to access the high voltage domain voltage, and the gate of transistor MP1 is connected to the gate of transistor MP2 and connected to the drain of transmission transistor through a switching transistor.

[0010] In one embodiment, the switching transistor is an N-channel switching transistor MN3.

[0011] In one embodiment, the clamping tube is a P-channel clamping tube MP3.

[0012] On the other hand, a memory chip is also provided, which uses any of the above-mentioned level switching circuits to perform voltage switching between different voltage domains.

[0013] One of the above technical solutions has the following advantages and beneficial effects:

[0014] The aforementioned level switching circuit and chip address the primary current contention issue through a current mirror-structured pull-up / pull-down drive network. A transmission transistor is used to shorten the circuit's switching response time and reduce the quiescent current of one inverter. Simultaneously, a feedback delay network is formed by the input and output, and a novel feedback switch is inserted into the current mirror branch. This feedback delay network controls the switch to achieve low quiescent current. Furthermore, a novel feedback-controlled clamping transistor is added to the pull-up / pull-down drive network. This clamping transistor uses a high threshold voltage and a small aspect ratio to compensate for the influence of the switch on the pull-up / pull-down drive network, allowing the output node Q1 to achieve a full voltage swing. This improves level switching speed and energy efficiency, enhances system stability, and reduces the quiescent current of the next-stage inverter, effectively improving the overall switching performance of the circuit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a traditional cross-coupled level switching circuit.

[0017] Figure 2 This is a schematic diagram of a traditional current mirror level switching circuit;

[0018] Figure 3 This is a schematic diagram of the structure of a new level switching circuit in one embodiment;

[0019] Figure 4 This is a schematic diagram of a new level switching circuit in another embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0021] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] like Figure 1 The diagram shows a traditional cross-coupled level switching circuit, consisting of an inverter, P-channel PMOS transistors MP1 and MP2, and N-channel NMOS transistors MN1 and MN2. VDDL is the low-voltage domain voltage, and VDDH is the high-voltage domain voltage. When the input signal IN switches to the low-voltage domain voltage VDDL, transistor MN1 begins to pull down the potential at point Q. As the potential at point Q decreases, the current of transistor MP1 gradually increases. This means that even when the current of transistor MN1 equals the current of transistor MP1, the potential at point Q may not have decreased beyond a threshold voltage V. TH At this time, transistor MP2 is not conducting, so the voltage of the output signal OUT cannot rise, and the circuit does not enter positive feedback, resulting in the inability to complete voltage switching; if the potential drop at point Q exceeds a threshold voltage V TH The circuit completes the normal voltage switching, but the level switching speed is slow due to the pull-up current of transistor MP1.

[0024] like Figure 2 As shown, this is a traditional current mirror level switching circuit. Its difference lies in the fact that transistors MP1 and MP2 employ a current mirror structure to solve the current contention problem. However, a large quiescent current exists when the input signal IN is high, resulting in low energy utilization efficiency. Therefore, this invention provides a new level switching circuit that overcomes the limitations of traditional cross-coupled and current mirror level switching circuits. Its design features high speed, low quiescent power consumption, and full output swing.

[0025] In one embodiment, such as Figure 3As shown, a level switching circuit is provided, including a feedback delay network, a transmission transistor MN1, a switching transistor, a current mirror, a pull-down transistor MN2, a clamping transistor, and an output inverter INV. The power supply terminal of the feedback delay network, the source of the current mirror, and the source of the clamping transistor are all connected to a high-voltage domain voltage. The ground terminal of the feedback delay network is grounded, and the source of the pull-down transistor MN2 is grounded. The first control input terminal of the feedback delay network is used to receive the input signal, and the second control input terminal of the feedback delay network is connected to the output terminal of the output inverter INV. The output terminal of the feedback delay network is connected to the gate of the switching transistor and the gate of the clamping transistor, respectively. The drain of the first transistor of the current mirror is connected to the drain of the transmission transistor MN1 through the switching transistor. The gate of the transmission transistor MN1 is used to receive a low-voltage domain voltage, and the source of the transmission transistor MN1 and the gate of the pull-down transistor MN2 are both used to receive the input signal. The input terminal of the output inverter INV is connected to the third control input terminal of the feedback delay network, the output terminal of the clamping transistor, the output terminal of the current mirror, and the drain of the pull-down transistor MN2, respectively. The feedback delay network is used to control the switching transistor and clamping transistor to eliminate quiescent current based on the input signal, the input signal of the output inverter INV, and the output signal of the output inverter INV. The clamping transistor is used to compensate for the influence of the switching transistor on the pull-up and pull-down drive network. The width-to-length ratio of the switching transistor and the transmission transistor MN1 is smaller than the width-to-length ratio of the transistors in the pull-up and pull-down drive network but larger than the width-to-length ratio of the other transistors in the circuit.

[0026] It can be understood that the input signal is VIN, the low-voltage domain voltage is VDDL, and the high-voltage domain voltage is VDDH. The gate voltage of the transmission transistor MN1 is connected to the low-voltage domain voltage VDDL. The transistors MN2 and MP2 in the pull-up / pull-down drive network are designed with a large aspect ratio to drive the voltage conversion of the output node Q1. The switching transistor and clamping transistor are controlled by the input signal VIN, the output node Q1, and the output signal VOUT through a feedback delay network. Compared to the transistors in the pull-up / pull-down drive network, the transmission transistor and the switching transistor are designed with a medium aspect ratio, while the remaining transistors in the circuit are designed with a smaller aspect ratio to ensure the switching control effect of the circuit.

[0027] The switching transistor can be either an N-channel or P-channel transistor. Similarly, the clamping transistor can also be either an N-channel or P-channel transistor, depending on the specific application requirements. The feedback delay network is a feedback control delay structure consisting of at least two transistor stages. The specific number of transistor stages can be selected based on the required delay effect, as long as the desired control function is achieved. The current mirror can employ a traditional current mirror level switching circuit design, or a more complex current mirror structure with more transistors, as long as the desired current mirror effect is achieved.

[0028] The aforementioned level switching circuit addresses current contention through a pull-up / pull-down drive network with a current mirror structure. A transmission transistor is used at transistor MN1 to shorten the circuit's switching response time. Simultaneously, a feedback delay network is formed by the input and output, and a novel feedback switch is inserted into the current mirror branch. This feedback delay network controls the switch to achieve low quiescent current. Furthermore, a novel feedback-controlled clamping transistor MP3 is added to the pull-up / pull-down drive network. MP3 uses a high threshold voltage and a small aspect ratio transistor to compensate for the influence of the switch on the pull-up / pull-down drive network, allowing the output node Q1 to achieve a full voltage swing. This improves level switching speed and energy efficiency, enhances system stability, and reduces the quiescent current of the next-stage inverter, effectively improving the overall switching performance of the circuit.

[0029] In one embodiment, such as Figure 4 As shown, the feedback delay network includes transistors MP4, MP5, MN4, and MN5. The sources of transistors MP4 and MP5 are both connected to the high-voltage domain. The gate of transistor MP4 is connected to the output terminal of the output inverter INV, and the gate of transistor MP5 is connected to the input terminal of the output inverter INV. The drain of transistor MP4 is connected to the drain of transistor MN4 and the gate of transistor MN5. The drain of transistor MP5 is connected to the drain of transistor MN5, the gate of the switching transistor, and the gate of the clamping transistor. The gate of transistor MN4 is used to receive the input signal, and the sources of transistors MN4 and MN5 are both grounded.

[0030] It is understood that this embodiment adopts a feedback control delay structure composed of two-stage transistors, with a total of four MOS transistors. The feedback control function is realized through the input signal VIN, the output signal VOUT, and the input signal of the output inverter INV. The circuit structure is simple and efficient, which can save production costs while improving the response efficiency and reliability of the circuit.

[0031] In one embodiment, such as Figure 4 As shown, the current mirror includes transistor MP1 and transistor MP2. The source of transistor MP1 and the source of transistor MP2 are both used to connect to the high voltage domain voltage. The gate of transistor MP1 is connected to the gate of transistor MP2 and connected to the drain of the transmission transistor through a switching transistor.

[0032] It is understood that this embodiment uses the simplest structure design of traditional P-channel dual MOS transistors to realize the current mirror function, thereby further improving the circuit's working efficiency and reliability.

[0033] In one embodiment, such as Figure 4As shown, the switching transistor is an N-channel MOSFET MN3. It can be understood that this embodiment uses an N-channel MOSFET as the switching transistor MN3 to efficiently address the static power consumption issue.

[0034] In one embodiment, the clamping transistor is a P-channel clamping transistor MP3. It can be understood that this embodiment uses a P-channel MOSFET as the clamping transistor MP3 to efficiently compensate for the influence of the switching transistor MN3, thereby achieving the full voltage swing of the output node Q1.

[0035] More specifically, with Figure 4 Taking the specific level switching circuit shown as an example, when the input signal VIN is 0V, the output node Q1 is VDDH, the output signal VOUT is 0V, the output node Q2 of the feedback delay network is 0V, and node VB is VDDH-V. TH At this time, transistors MN2, MN3, MN4, MP1, MP2, and MP5 are all completely off, while transistors MN1, MN5, MP3, and MP4 are in the deep linear region. At this point, all branches of the entire circuit system are completely shut off, and there is no quiescent current.

[0036] When the input signal VIN transitions from 0V to VDDL, transistor MN2 turns on, pulling down the potential at point Q1. At this time, transmission transistor MN1 turns off, and transistors MP1 and MP2 remain off. Although clamping transistor MP3 is on, its aspect ratio is small and its driving capability is weak. Therefore, transistor MN2 successfully pulls the potential at point Q1 down to near 0V, and the output signal VOUT switches to VDDH output. The entire low-voltage to high-voltage switching process eliminates the main current contention problem and achieves high-speed switching.

[0037] When the output signal VOUT completes its rise transition, the output node Q2 of the feedback delay network rises to VDDH. The output node Q2 of the feedback delay network completely turns off the clamping transistor MP3, thus pulling the output node Q1 completely down to 0V. Simultaneously, the output Q2 of the feedback delay network also fully turns on the switching transistor MN3. Since the transmission transistor MN1 is completely off, there is no quiescent current in this branch. After the rise transition is complete, the potentials at all points in the system are at a stable logic low or logic high, and all transistors are completely off, achieving zero quiescent current.

[0038] When the input signal VIN switches from VDDL to 0V, transistor MN2 turns off and transmission transistor MN1 turns on. Transmission transistor MN1 and transistor MP1 form a conduction current, which is amplified by a current mirror and supplied to transistor MP2. Transistor MP2 quickly charges and pulls up the output node Q1 to near VDDH, and the output signal VOUT switches to 0V. The entire high-voltage to low-voltage switching process has no current contention problem and achieves high-speed switching.

[0039] When the output signal VOUT completes its droop transition, the output node Q2 of the feedback delay network drops to 0V. The output node Q2 of the feedback delay network then fully opens the clamping transistor MP3, pulling the output node Q's potential fully up to VDDH. Simultaneously, the output node Q2 of the feedback delay network also completely turns off the switching transistor MN3, resulting in no quiescent current in this branch. After the droop transition is complete, all system points are at a stable logic low or logic high, and all transistors are completely off, thus achieving no quiescent current.

[0040] As can be seen from the circuit analysis above, the level switching circuit can not only realize the level switching function, but also has significant performance characteristics such as high-speed switching, low static power consumption and strong system stability.

[0041] In one embodiment, a memory chip is also provided, which employs the level switching circuit of any of the above embodiments to perform voltage switching between different voltage domains.

[0042] It is understood that the memory chip can be any type of memory chip, and the level switching circuit of any of the above embodiments can be used to replace the traditional level switching circuit in the chip, thereby improving the chip's working efficiency and reducing the chip's power consumption.

[0043] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0044] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A level switching circuit, characterized in that, It includes a feedback delay network, a transmission transistor, a switching transistor, a current mirror, a pull-down transistor, a clamping transistor, and an output inverter. The power supply terminal of the feedback delay network, the source of the current mirror, and the source of the clamping transistor are all used to connect to the high voltage domain voltage. The ground terminal of the feedback delay network is grounded, and the source of the pull-down transistor is grounded. The feedback delay network includes transistors MP4, MP5, MN4, and MN5. The sources of transistors MP4 and MP5 are used to connect to the high-voltage domain voltage. The gate of transistor MP4 is connected to the output terminal of the output inverter. The drain of transistor MP4 is connected to the drain of transistor MN4 and the gate of transistor MN5. The drain of transistor MP5 is connected to the drain of transistor MN5, the gate of the switching transistor, and the gate of the clamping transistor. The gate of transistor MN4 is used to connect to the input signal. The sources of transistor MN4 and MN5 are grounded. The drain of the first transistor of the current mirror is connected to the drain of the transmission transistor through the switching transistor. The gate of the transmission transistor is used to connect to the low-voltage domain voltage. The source of the transmission transistor and the gate of the pull-down transistor are used to connect to the input signal. The input terminal of the output inverter is connected to the gate of transistor MP5, the output terminal of the clamping transistor, the output terminal of the current mirror, and the drain of the pull-down transistor. The feedback delay network is used to control the switching transistor and clamping transistor to eliminate quiescent current based on the input signal, the input signal of the output inverter, and the output signal of the output inverter, respectively. The clamping transistor is used to compensate for the influence of the switching transistor on the pull-up and pull-down drive network. The width-to-length ratio of the switching transistor and the transmission transistor is less than the width-to-length ratio of the transistors in the pull-up and pull-down drive network but greater than the width-to-length ratio of the other transistors in the circuit.

2. The level switching circuit according to claim 1, characterized in that, The current mirror includes transistors MP1 and MP2. The source of transistors MP1 and MP2 are both used to connect to the high voltage domain voltage. The gate of transistor MP1 is connected to the gate of transistor MP2 and connected to the drain of the transmission transistor through a switching transistor.

3. The level switching circuit according to claim 2, characterized in that, The switching transistor is an N-channel transistor MN3.

4. The level switching circuit according to claim 2, characterized in that, The clamping tube is a P-channel clamping tube MP3.

5. A memory chip, characterized in that, Voltage switching between different voltage domains is performed using the level switching circuit described in any one of claims 1 to 4.

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