Antenna modules as radio frequency (RF) integrated circuit (IC) dies with integrated antenna substrates and related methods of manufacture

Abstract

An antenna module serves as a radio frequency (RF) integrated circuit (IC) semiconductor die ("die") with an integrated antenna substrate. As an example, a die with an integrated antenna substrate may be provided as part of a single IC chip that is fabricated as part of a wafer level fabrication process. The antenna element is formed as a part of the antenna substrate in the one or more antenna layers. The antenna layer may be formed as a redistribution layer (RDL), for example to support smaller line spacing (LS) and / or smaller pitch metal interconnects for forming and interconnecting to smaller wavelength antenna elements to support higher frequency communications. An antenna substrate is formed on a semiconductor wafer of an IC as part of a die. In this manner, the antenna layers may be formed as part of a wafer level fabrication process that is used to form dies to form the antenna layers.

Description

Background Technology

[0001] I. Open Domain

[0002] This disclosure relates to antenna modules, such as “Antenna Package (AiP)”, which include a radio frequency (RF) integrated circuit (IC) coupled to an antenna as part of an IC package.

[0003] II. Background

[0004] Modern smartphones and other portable devices have expanded the use of different wireless links using various technologies across different RF bands. For example, fifth-generation (5G) cellular networks (often referred to as 5G New Radio (NR)) encompass frequencies in the 24.25 to 86 GHz range, with the lower 19.25 GHz (24.25–43.5 GHz) being more likely to be used by mobile devices. This spectrum for 5G communication falls within the millimeter wave (mmWave) or millimeter band range. Millimeter waves enable higher data rates compared to lower frequencies, such as those used for Wi-Fi and current cellular networks. Furthermore, there may be a desire to support communication devices at higher frequencies, which are submillimeter wave frequencies of the sixth-generation (6G) spectrum (such as, for example, the D-band spectrum in the 110–170 GHz frequency range) to utilize additional available spectrum.

[0005] Radio frequency (RF) transceivers are incorporated into mobile devices and other portable devices designed to support communication signals in the desired spectrum. To support the integration of the RF transceiver into the device, it can be integrated into an RF integrated circuit (IC) within an RF IC chip provided as part of an antenna module. The RF IC chip is implemented in an RF IC semiconductor die (“RFIC die”). The antenna module is also known as an “antenna in package” (AiP). A typical antenna module includes a die module comprising one or more RF ICs, a power management IC (PMIC), and passive electrical components (such as inductors, capacitors, etc.) mounted on a package substrate as a support structure. The RF IC die includes an RF signal transmitter and a receiver capable of modulating RF signals to be transmitted in the supported frequency band(s) and demodulating RF signals received in the supported frequency band(s). The package substrate includes multiple metallization layers (e.g., laminated FR2 metallization layers) that include metal lines / traces to metal interconnects. These metal lines / traces provide chip-to-chip interfaces and external signal interfaces for the die module. The package substrate also includes other metallization layers in which one or more antennas are formed. These antennas are electrically coupled to the die module via the metal interconnects of the package substrate, enabling the reception and radiation of RF electrical signals as electromagnetic (EM) signals. The package substrate may include multiple antennas (also referred to as an antenna array) to provide signal coverage over a desired large area around the antenna module.

[0006] As the spectrum supported by antenna modules continues to increase, it is necessary to design antennas in such modules that can support higher frequencies (for example, such as D-band frequencies).

[0007] Public Overview

[0008] The aspects disclosed herein include an antenna module as a radio frequency (RF) integrated circuit (IC) semiconductor die (“die”) having an integrated antenna substrate. As an example, the die with the integrated antenna substrate may be provided as part of a single IC chip manufactured as part of a wafer-level manufacturing process. Such related manufacturing processes are also disclosed. The die includes an RF IC that includes RF circuitry (e.g., front-end process RF circuitry) including RF signal transmission and / or reception capabilities. The RF IC, as part of the die, is coupled to an antenna vibrator in the antenna substrate to receive and radiate such RF signals. It is desirable for the antenna module to support higher frequency communications (which support shorter wavelengths, e.g., D-band frequencies). This may require smaller antenna vibrators, which necessitate a manufacturing process capable of forming metal elements (e.g., metal traces, metal lines) in a small line-to-spacing (L / S) metal pattern with metal interconnects, the pitch of which is smaller than that achievable, for example, in an antenna in package (AiP). In AiP (Anti-Package), the antenna layer is formed in a separate package substrate, which is separately manufactured and packaged with the IC die via a coupled bump structure as part of the IC package. In this regard, in an exemplary aspect, to enable the formation of smaller antenna elements supporting higher frequencies within the antenna substrate, smaller L / S metal patterns and / or smaller pitch metal interconnects coupled to these antenna elements are formed as part of one or more antenna layers on a semiconductor wafer (e.g., a complementary metal-oxide-semiconductor (CMOS) wafer). The RF IC is formed as part of the die within the semiconductor wafer. In this way, the antenna layer can be formed as part of a wafer-level manufacturing process for forming the RF IC within the semiconductor wafer and, within the same die, forming an antenna layer with smaller L / S metal patterns and / or smaller pitch metal interconnects to support antenna elements capable of supporting higher frequency communications. Furthermore, by providing an antenna module with the antenna substrate integrated into the die, the antenna module can be fully tested at the wafer level (if desired) to improve quality and yield.

[0009] In one exemplary aspect, the antenna layer of the antenna substrate may be formed on the back side of the RF IC circuitry, adjacent (i.e., directly adjacent or indirectly adjacent) to the back side of the semiconductor layer of the RF IC in which active semiconductor devices are formed. In the example, the back side of the semiconductor layer is located on the opposite side of the front side of the semiconductor layer, which is adjacent to a BEOL metallization structure. The semiconductor layer may be formed as part of a front-end process (FEOL) process. Forming the antenna substrate on the back side of the RF IC and adjacent to the back side of the semiconductor layer allows the antenna elements of the antenna substrate to be positioned closer to the IC metal layers to minimize the distance between them, thereby reducing transmission losses. For example, if the RF IC is a bulk device, the antenna substrate may be formed adjacent to a bulk semiconductor material layer (e.g., a bulk silicon substrate). Alternatively, as another example, if the RF IC is a semiconductor-on-insulator (SOI) device, the antenna substrate may be formed adjacent to a buried oxide (BOX) layer. In these examples, a metal layer formed as part of the back-end process (BEOL) interconnect structure of the RF IC to provide signal routing to the RF IC is formed on the opposite side of the semiconductor layer adjacent to the antenna substrate. In this example, forming the antenna layer of the antenna substrate on the back side of the RF IC allows these antenna layers to be built on a stalk coupled to the semiconductor layer without interfering with the formation of the BEOL interconnect structure of the RF IC.

[0010] Furthermore, since the antenna module is supplied as a die including an integrated antenna substrate, the distance between the antenna layer in which the antenna elements are formed and the RF IC is shortened compared to the distance between the antenna layer and the die in an AiP (Analog-In-Package) system. This reduces the headroom between the antenna elements and the RF IC, thereby reducing transmission loss. Reducing transmission loss may be particularly important in antenna modules supporting higher frequencies (e.g., D-band frequencies) because data transmission rates may be higher, making it more difficult to keep the signal-to-noise ratio (SNR) of the RF signal below desired limits. Reducing the headroom between the antenna elements and the RF IC within the die also reduces the distance between these antenna elements and the ground plane formed in the metal layer of the RF IC (e.g., the ground plane in a BEOL interconnect structure), further reducing transmission loss.

[0011] In other exemplary aspects, a dielectric substrate of the dielectric material may be formed adjacent to the semiconductor layer of the RF IC to provide a surface on which the antenna layer of the antenna substrate may be formed as part of a wafer fabrication process for the die. In this example, since the die is manufactured using a wafer-level manufacturing process, the dielectric substrate may be formed as a silicon substrate. The dielectric substrate may serve as a handle in which the semiconductor layer of the RF IC and the BEOL interconnect structure are formed. The antenna layer of the antenna substrate may then be formed on the dielectric substrate opposite the semiconductor layer. The dielectric substrate may be processed (e.g., thinned) to control the ideal clearance distance between the antenna vibrator formed in the antenna layer of the antenna substrate and the RF IC in the semiconductor layer, thereby controlling transmission loss. Through-holes (e.g., through-silicon vias (TSVs)) may be formed in the antenna substrate and pass through the BEOL interconnect structure of the semiconductor layer and the RF IC to interconnect the antenna vibrator with the RF IC. The wafer fabrication process for the RF IC die may support control over the thickness of the dielectric substrate between the antenna substrate and the RF IC, making it compatible with the process height limitations of via formation.

[0012] In other examples, the dielectric substrate (e.g., a silicon substrate) between the antenna substrate and the RF IC may have a higher dielectric constant than desired, resulting in transmission losses in an undesirable manner. These transmission losses can be unacceptable, especially if the antenna module and its antenna element are designed to support higher frequency communications. In this regard, in one example, the dielectric substrate between the antenna substrate and the RF IC die can be provided as a porous silicon layer. As an example, after the semiconductor layer and BEOL interconnect structure of the RF IC are formed on the dielectric substrate using a silicon layer as a shank layer, this silicon layer can be porousned to control and tune its dielectric constant and loss tangent to desired levels, thereby achieving the desired performance for the supported communication frequencies. Controlling the porosity of the silicon layer between the semiconductor layer and the antenna substrate controls the dielectric constant of the silicon layer, thereby controlling the transmission losses between the antenna element and the RF IC in the antenna substrate. In another example, to prevent damage to the semiconductor layer during a porousification process on the silicon layer adjacent to it, an etch stop layer (e.g., a nitride layer) may be disposed on the silicon layer as a shank layer before the semiconductor layer is formed on the shank silicon layer. The etch stop layer prevents the porousification of the semiconductor layer when the silicon layer is processed into a porous silicon layer.

[0013] In another exemplary aspect, in an antenna module provided as a die including an integrated antenna substrate, the antenna layer of the antenna substrate can be formed as a redistribution layer (RDL). The RDL can be built on a semiconductor wafer as part of an RDL fabrication process within a wafer-level manufacturing process. The RDL fabrication process supports the formation of smaller L / S metal patterns and smaller pitch metal interconnects. The RDL can also support redistribution of connections to antenna elements so that these connections do not need to be aligned with metal interconnects (e.g., vias) that couple these antenna elements to the RF IC via the antenna substrate.

[0014] In this regard, in one exemplary aspect, a semiconductor die is provided. The semiconductor die includes: a semiconductor layer and a BEOL interconnect structure. The semiconductor layer includes a first side; a back side opposite to the first side; and radio frequency (RF) circuitry. The BEOL interconnect structure is coupled to the RF circuitry. The BEOL interconnect structure includes: a front side; and a second side opposite to the front side; the second side is coupled to the first side of the semiconductor layer. The semiconductor die also includes: an antenna substrate adjacent to the back side of the semiconductor layer. The antenna substrate includes one or more antenna layers, the first antenna layer of the one or more antenna layers including one or more antenna elements. The semiconductor die also includes: one or more first vias, each via coupling an antenna element of the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuitry.

[0015] In another exemplary aspect, a method of manufacturing a semiconductor die is provided. The method of manufacturing the die includes: forming a semiconductor layer including a first side; a back side opposite to the first side; and radio frequency (RF) circuitry. The method of manufacturing the die further includes: forming a BEOL interconnect structure coupled to the RF circuitry, the BEOL interconnect structure including a front side; and a second side opposite to the front side, the second side being coupled to the semiconductor layer. The method of manufacturing the die further includes: forming an antenna substrate adjacent to the back side of the semiconductor layer, wherein forming the antenna substrate includes forming one or more antenna layers, wherein a first antenna layer of the one or more antenna layers includes one or more antenna elements; and forming one or more first vias, each via coupling an antenna element of the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuitry. Brief description of the attached diagram

[0017] Figure 1A and 1B This is a side view of an antenna module in the form of an antenna-in-package (AiP) comprising a radio frequency (RF) integrated circuit (IC) die coupled to a package substrate that supports an antenna formed in a metallization layer therein.

[0018] Figure 2A and 2B This is a side view of an exemplary semiconductor die (“die”) providing an antenna module, wherein the die includes an RF IC having RF circuitry and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC.

[0019] Figure 3 This is a side view of an exemplary electronic device, which includes components coupled to a package substrate. Figure 2A and 2B The semiconductor die in the package is coupled to the circuit board by the packaging substrate.

[0020] Figure 4 This is a side view of another exemplary die for providing an antenna module, wherein the die is a semiconductor-on-insulator (SOI) device with RF circuitry, and an integrated antenna substrate for providing an antenna for the RF circuitry, wherein the die further includes a dielectric material layer in the form of a porous silicon substrate disposed between the semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and control the clearance distance between the antenna vibrator and the RF circuitry, thereby controlling transmission loss;

[0021] Figure 5 This is a side view of another exemplary die for providing an antenna module, wherein the die includes a body device having RF circuitry and an integrated antenna substrate to provide an antenna for the RF circuitry, wherein the die further includes a dielectric material layer disposed between a semiconductor layer of an RF IC and the antenna substrate to support the formation of the antenna substrate and control the clearance distance between the antenna vibrator and the RF circuitry to control transmission loss.

[0022] Figure 6 This is a flowchart illustrating an exemplary manufacturing process for manufacturing a die that provides an antenna module, wherein the die includes an RF IC having RF circuitry, and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC, and the die includes, but is not limited to, [other components]. Figures 2A-5 The core in the tube;

[0023] Figures 7A-7E This is a flowchart illustrating another exemplary manufacturing process for manufacturing a die for providing an antenna module, wherein the die is an SOI device having RF circuitry, and manufacturing an integrated antenna substrate for providing an antenna for the RF circuitry, wherein the die further includes a dielectric material layer disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and control the clearance distance between the antenna vibrator and the RF circuitry to control transmission loss. The die includes, but is not limited to, […]. Figures 2A-5The core in the tube;

[0024] Figures 8A-8F The explanation was based on Figures 7A-7E An exemplary manufacturing stage during the manufacturing process of a die manufactured using the manufacturing process described above;

[0025] Figures 9A-9E This is a flowchart illustrating another exemplary manufacturing process for producing a die for providing an antenna module, wherein the die includes a bulk device having RF circuitry and an integrated antenna substrate to provide an antenna for the RF circuitry. The die further includes a dielectric material layer disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and control the clearance between the antenna element and the RF circuitry to control transmission loss. The die includes, but is not limited to, […]. Figures 2A-5 The core in the tube;

[0026] Figures 10A-10F The explanation was based on Figures 9A-9E An exemplary manufacturing stage during the manufacturing process of a die manufactured using the manufacturing process described above;

[0027] Figure 11 This is a block diagram of an exemplary wireless communication device, which includes a die providing an antenna module, wherein the die includes an RF IC having RF circuitry, and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC, including but not limited to... Figures 2A-5 , Figure 8F and Figure 10F The core in the tube, and can be according to Figure 6 , Figures 7A-7E and Figures 9A-9E Manufactured using any of the exemplary manufacturing processes;

[0028] Figure 12 This is a block diagram of an exemplary processor-based system, including a die providing an antenna module, wherein the die includes an RF IC with RF circuitry, and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC, including but not limited to... Figures 2A-5 , Figure 8F and Figure 10F The core in the tube, and can be according to Figure 6 , Figures 7A-7E and Figures 9A-9E Manufactured using any of the exemplary manufacturing processes described above.

[0029] Detailed description

[0030] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than the other aspects.

[0031] The aspects disclosed herein include an antenna module as a radio frequency (RF) integrated circuit (IC) semiconductor die (“die”) having an integrated antenna substrate. As an example, the die with the integrated antenna substrate may be provided as part of a single IC chip manufactured as part of a wafer-level manufacturing process. Such related manufacturing processes are also disclosed. The die includes an RF IC that includes RF circuitry (e.g., front-end process RF circuitry) including RF signal transmission and / or reception capabilities. The RF IC is coupled to an antenna vibrator in an antenna substrate that is part of the die to receive and radiate such RF signals. It may be desirable for the antenna module to support higher frequency communications (which support shorter wavelengths, e.g., D-band frequencies). This may require smaller antenna vibrators, which necessitate a manufacturing process capable of forming metal elements (e.g., metal traces, metal lines) in a small line-to-spacing (L / S) metal pattern with metal interconnects, the pitch of which is smaller than that achievable, for example, in an antenna in package (AiP). In AiP (Antenna-in-Package), antenna layers are formed in separate package substrates, which are individually manufactured and packaged with a die as part of an IC package via a coupled bump structure. In this regard, in an exemplary aspect, to enable the formation of smaller antenna elements supporting higher frequencies within an antenna substrate, these antenna elements, along with smaller L / S metal patterns and / or smaller pitch metal interconnects coupled to these antenna elements, are formed as part of one or more antenna layers on a semiconductor wafer (e.g., a complementary metal-oxide-semiconductor (CMOS) wafer). The RF IC is formed as part of the die within the semiconductor wafer. In this way, the antenna layers can be formed as part of a wafer-level manufacturing process for forming the RF IC within the semiconductor wafer and, within the same die, forming an antenna layer with smaller L / S metal patterns and / or smaller pitch metal interconnects to support antenna elements capable of supporting higher frequency communications. Furthermore, by providing an antenna module that integrates the antenna substrate within a die, the antenna module can be fully tested at the wafer level (if desired) to improve quality and yield.

[0032] From Figure 2A Before discussing examples of dies that provide antenna modules (where the die includes an RFIC with RF circuitry and an integrated antenna substrate that provides an antenna for the RF circuitry), please refer to the following... Figure 1A and 1BAn example of an antenna module 100 provided in AiP form as a PoP structure is discussed.

[0033] In this regard, Figure 1A This is a side view of antenna module 100, which is an IC package arranged side-by-side. Figure 1B Too Figure 1A A partial side view of antenna module 100 is shown, but rotated 180 degrees in the vertical direction (Z-axis direction) to further illustrate antenna module 100. Antenna module 100 includes an antenna substrate 102 supporting antenna elements (e.g., patch and / or dipole antenna elements) for supporting RF communication. Antenna module 100 includes an IC die layer 106 disposed in a horizontal plane (X-axis and Y-axis plane), wherein IC die layer 106 includes an RF IC semiconductor die (RF IC die) 108, and RF IC die 108 includes an RF transceiver. RF IC die 108 may be in the form of a packaged IC chip 109. IC die layer 106 having RF IC die 108 is mounted on a package substrate 110 to provide a support structure for IC die layer 106 and to provide interconnection structures for coupling RF IC die 108 to other components and circuitry in antenna module 100. Antenna module 100 may also include, Figure 1A The separate, adjacent power management IC (PMIC) die 112 (which may also be an IC chip) shown provides power to the RF IC chip 108. The RF IC die 108 and PMIC die 112 are arranged side-by-side in the horizontal direction (X-axis direction). The IC die layer 106 also includes other passive components 114 (e.g., capacitors, inductors) electrically coupled to the RF IC die 108 and / or PMIC die 112 via the package substrate 110 as part of the circuitry formed therein. The size of these passive components 114 may make integration into the RF IC die 108 or PMIC die 112 unsuitable or impractical. Electromagnetic interference (EMI) shielding 117 is arranged around the RF IC die 108 and other components in the IC die layer 106.

[0034] Continue to refer to Figure 1AIn this example, the package substrate 110 includes a metallized substrate 116 adjacent to the IC die layer 106. The metallized substrate 116 includes a plurality of substrate metallization layers 118, each substrate metallization layer 118 including metal interconnects 120 (e.g., pads, vertical interconnect vias, traces, lines) formed therein to provide interconnect structures facilitating interconnection, providing an electrical interface between the RF IC die 108 and other components and circuitry in the antenna module 100. Die interconnects 121 couple the RF IC die 108 to the metal interconnects 120 in the metallized substrate 116. The metallized substrate 116 may be a coreless substrate. The substrate metallization layers 118 may be formed as separate substrate layers, which are laminated together to form the metallized substrate 116. In this example, the metallized substrate 116 is coupled to the core substrate 122 as part of the package substrate 110. The core substrate 122 also includes one or more metallization layers 124, which include metal interconnects 126 coupled to vias 128 (e.g., metal bond posts) and metal interconnects 126 coupled to metal interconnects 120 in an adjacent metallization substrate 116 to provide electrical connectivity between the metallization substrate 116 and the core substrate 122.

[0035] Continue to refer to Figure 1A and 1BThe packaging substrate 110 in the antenna module 100 also includes an antenna substrate 102, which may be a prepreg or a laminated substrate. In this example, the antenna substrate 102 is coupled to a core substrate 122 such that the core substrate 122 is arranged in the vertical direction (Z-axis direction) between the antenna substrate 102 and the metallized substrate 116. The antenna substrate 102 also includes one or more metallization layers 130, which include metal interconnects 132 coupled to vias 134, which are coupled to metal interconnects 126 in the core substrate 122. In this example, the antenna substrate 102 includes four (4) antennas 136(1)-136(4), which are electrically coupled to the RF IC die 108 through interconnections between the antennas 136(1)-136(4) and the metal interconnects 120, 126, 132 in the corresponding metallized substrate 116, core substrate 122, and antenna substrate 102. In this example, each antenna 136(1)-136(4) is a patch antenna, comprising a first antenna element 138(1)-138(4) in the form of a metal patch adjacent to the core substrate 122 and an antenna element in the form of a second metal patch 140(1)-140(4) disposed below the respective first antenna element 138(1)-138(4). The first antenna elements 138(1)-138(4) are coupled to the RF IC die 108 through a via 134 and metal interconnects 132, 126, 120 that serve as antenna feed lines. The second metal patch 140(1)-140(4) does not contact the first antenna element 138(1)-138(4). Instead, when the first antenna element 138(1)-138(4) receives the RF signal to be radiated, the second metal patch 140(1)-140(4) is configured to be electromagnetically (EM) coupled to the first antenna element 138(1)-138(4). Similarly, when the second metal patch 140(1)-140(4) is excited by the received RF signal, the second metal patch 140(1)-140(4) is EM-coupled to the first antenna element 138(1)-138(4) with the received RF signal.

[0036] The dimensions of the antenna elements 138(1)-138(4) and 140(1)-140(4) in the antenna substrate 102 of the antenna module 100 are set to support the desired wavelength for the desired communication frequency capability of the antenna module 100. As an example, the antenna elements 138(1)-138(4) and 140(1)-140(4) can be 3.0 mm x 3.0 mm metal patches to support 5G communication spectrum. This can be used to manufacture similar... Figure 1BThe AiP manufacturing process of the antenna module 100 may be sufficient to provide the metal interconnects 132 in the antenna substrate 102 to support L / S metal patterns and pitches, thereby supporting interconnections with the antenna elements 138(1)-138(4), 140(1)-140(4) according to their shape and size. However, as an example, for higher communication frequencies, such as in the D-band spectrum, the wavelengths supported by the antenna elements 138(1)-138(4), 140(1)-140(4) may require the antenna elements 138(1)-138(4), 140(1)-140(4) to be manufactured in a metallization layer of the antenna substrate 102 that is much smaller in size (e.g., 150 micrometers (μm) × 150 μm). This is because the higher the frequency of the signal, the smaller its wavelength. The manufacturing techniques available for fabricating antenna substrate 102 may not be able to form metal interconnects 132 in antenna substrate 102 with sufficiently small or fine L / S metal patterns and pitches to enable interconnection to smaller antenna elements. Therefore, like... Figure 1A and 1B Antenna modules such as antenna module 100 (which is in AiP or PoP package) may not be adequately manufactured to support higher frequency communications.

[0037] Reference Figure 1B The clearance D1 between the antenna elements 138(1)-138(2) and the RF IC die 108 of the antenna module 100 also needs to be compatible to provide the desired trade-off between transmission loss and the form factor of the antenna module 100. Figure 1B Only antenna elements 138(1)-138(2) and 140(1)-140(2) for antennas 136(1)-136(2) are shown. Figure 1BAs shown, in this example, the RF IC die 108 includes a power amplifier (PA) 142 and a low-noise amplifier (LNA) 144 formed in a semiconductor layer 146. The RF IC die 108 also includes a back-end process interconnect (BEOL) structure 148, which includes multiple metal layers of insulated metal lines or traces to provide vertical (Z-axis) interconnect paths between the PA 142 and LNA 144 and the metallized substrate 116. These PA 142 and LNA 144 are exemplary circuits in the RF IC die 108 that support RF signal reception and transmission capabilities with antennas 136(1)-136(2). The PA 142 and LNA 144 are located at a distance D1 from the antenna elements 138(1)-138(2). Transmission loss increases with increasing signal frequency. Therefore, providing a short interconnect path between the RFIC die 108 and the antenna elements 138(1)-138(2) in the antenna module 100 to reduce transmission loss may be important. In the context of AiP Figure 1B In the antenna module 100, the clearance distance D1, based on the dimensions of the antenna substrate 102, core substrate 122, and metallized substrate 116 according to their manufacturing technology, can be between 500-600 μm. Furthermore, if the clearance distance D1 is too large, there is a risk of increased EMI (and therefore reduced signal-to-noise ratio (SNR)) between the RF IC die 108 and the antenna elements 138(1)-138(2), leading to performance degradation. The clearance distance D1 also affects the distance between the antenna elements 138(1)-138(2) and, for example, a ground plane provided in the metallized substrate 116. The clearance distance D1 also affects the clearance distance between the antenna elements 138(1)-138(2) and any ground plane, as the clearance distance D1 affects the antenna's impedance, radiation pattern, and gain, which in turn affect the data transmission rate.

[0038] The clearance distance D1 between antenna elements 138(1)-138(2) and RF IC die 108 may be acceptable to provide the desired performance in antenna module 100 at, for example, millimeter-wave frequencies. However, for higher frequencies (e.g., D-band frequencies), the clearance distance D1 may lead to unacceptable losses. For example, the clearance distance D1 between antenna elements 138(1)-138(2) and RF IC die 108 may ideally be 70-80 μm to avoid transmission losses between RF IC die 108 and antenna elements 138(1)-138(2), which would result in unacceptable performance based on performance parameters affected by such clearance distances as described above. Due to the PoP configuration and the manufacturing process limitations of the antenna substrate 102, core substrate 122, and / or metallized substrate 116 of the packaging substrate 110 used to manufacture the antenna module 100, it may not be possible to manufacture with such a reduced clearance distance D1 between the antenna elements 138(1)-138(2) and the RFIC die 108. Figure 1A and 1B Antenna module 100 in the middle.

[0039] Therefore, in conclusion, as Figure 1A and 1B The antenna module 100 in the AiP may not be feasible for supporting higher frequency RF signals, for example, in the D-band spectrum. To support the transmission of higher frequency RF signals, the antenna element may need to be manufactured in a smaller size to be compatible with (i.e., support) higher frequency RF signals at smaller wavelengths. This may require manufacturing the antenna substrate of the antenna module with smaller L / S patterns and / or pitch metal interconnects, which can be fabricated in the antenna substrate 102, as per packaging substrate manufacturing techniques. Figure 1A and 1B The same applies to antenna module 100. The dimensions are set to support smaller antenna elements for shorter wavelengths, so that the metal interconnects in antenna substrate 102 may not be manufactured small enough to provide interconnects to these antenna elements without the risk of short circuits. In addition, to support such higher frequency RF signals, the clearance distance D1 between antenna elements 138(1)-138(2) and RF IC die 108 needs to be reduced to less than the size that can be provided in antenna module 100 due to manufacturing limitations, in order to reduce signal path distance and EMI, thereby achieving the desired SNR.

[0040] In this regard, as an example, to provide an antenna module capable of supporting higher RF signal frequencies (e.g., D-band frequencies of 110 to 170 GHz), the antenna module could be formed as part of the die, rather than as... Figure 1A and 1BThe antenna module 100 is formed as an AiP or PoP. As described in more detail below, integrating the antenna module into the die allows the metal interconnects in the antenna layer of the antenna substrate in the antenna module to be fabricated with smaller L / S patterns and / or pitches, enabling interconnections to the smaller antenna element formed therein, thereby supporting higher RF signal frequencies. Furthermore, as described in more detail below, integrating the antenna module into the die also allows the clearance between the antenna element and the coupled IC in the die, which supports RF signal transmission and reception, to be reduced as can be varied by the manufacturing process technology used to manufacture the die. The die can be manufactured using a wafer-level manufacturing process that allows the antenna layer of the antenna substrate to be built on the substrate in the wafer to minimize the height distance of the antenna layer, thereby minimizing the clearance between the antenna element and the coupled IC in the die. These possibilities allow the antenna module integrated into the die to be manufactured in a manner compatible with and capable of supporting higher RF signal frequencies, which would otherwise be present in an AiP (such as...) Figure 1A and 1B This may not be possible in the antenna module 100.

[0041] In this regard, Figure 2A and 2B This is a side view of an exemplary die 200, which provides an integrated antenna module 202 integrated into the die 200, the integrated antenna module 202 being capable of supporting higher frequency RF signals (e.g., D-band frequencies). However, Figure 2A and 2BThe die 200 in the die does not need to support any specific frequency or band of RF signal. The die 200 is an RF die, which is a semiconductor die including an RF IC 204 with RF circuitry 206. The RF circuitry 206 is electrically coupled to an antenna vibrator 208 provided in an integrated antenna substrate 210 in the die 200 to provide an antenna 212 for the RF circuitry 206. In this example, six (6) antenna vibrators 208(1)-208(6) in the form of six (6) metal patch antennas formed in the horizontal direction (X-axis and Y-axis direction) form six (6) corresponding antennas 212(1)-212(6), but this is not limiting. In this way, as discussed in more detail below, the die 200 with integrated antenna substrate 210 can be provided as part of a single IC chip 209, for example, the single IC chip 209 is manufactured as part of a wafer-level manufacturing process. Die 200 includes an RF IC 204, which includes RF circuitry 206 (e.g., front-end RF circuitry) to provide RF signal transmission and / or reception capabilities. In this example, for an antenna module 202 integrated into die 200 (which has a small L / S pattern and / or small pitch metal interconnects in antenna substrate 210 to support interconnects to antenna elements supporting higher RF signal frequencies), antenna elements 208(1)-208(6) are formed in antenna substrate 210 on a semiconductor wafer (e.g., a complementary metal-oxide-semiconductor (CMOS) wafer). RF IC 204 is formed in the semiconductor wafer as part of die 200. In this way, antenna substrate 210 can be formed as part of a wafer-level manufacturing process for forming RF IC 204 in a semiconductor wafer and forming antenna substrate 210 with small L / S pattern and / or small pitch metal interconnects to support antenna elements capable of supporting higher frequency communications. Furthermore, by providing an antenna module 202 that integrates the antenna substrate 210 into the die 200, the antenna module 202 can be fully tested at the wafer level (if needed) to improve quality and yield.

[0042] Continue to refer to Figure 2BIn this example, die 200 includes an RF IC 204, which includes RF circuitry 206. For example, RF circuitry 206 may be included as part of an LNA 214 and PA 216 (and / or, for example, other front-end process RF circuitry) to provide RF signal transmission and / or reception capabilities. RF IC 204 includes a semiconductor layer 218 (e.g., a silicon layer) in which active electrical devices (e.g., transistors) are formed (hence also referred to as an "active semiconductor layer"). Semiconductor layer 218 has a first side 220 and a side 222 opposite to the first side 220 in the vertical direction (Z-axis direction). The opposite side 222 of semiconductor layer 218 is also referred to as the "back side" 222 because it is the side of semiconductor layer 218 that is not adjacent to the BEOL interconnect structure 224, while the "first side 220" is adjacent to the BEOL interconnect structure 224. The back side 222 of semiconductor layer 218 (which in this example is the back side 222 of RF IC 204) has a back side or back side surface located on the opposite side of the first side 220 (where RF circuitry 206 is formed adjacent to first side 220). The back side 222 of RF IC 204 may not contain active electronic components or electrical connections. Active components 225 (such as transistors) may be formed in semiconductor layer 218 as part of RF circuitry 206 adjacent to and coupled to BEOL interconnect structure 224. In this example, RFIC 204 is a semiconductor-on-insulator (SOI) device because semiconductor layer 218 includes a semiconductor substrate 229 (e.g., a silicon substrate) adjacent to the back side 222 of semiconductor layer 218 and a buried oxide (BOX) layer 227 adjacent to the first side 220 of semiconductor layer 218. BOX layer 227 is located between semiconductor substrate 229 and first side 220 of semiconductor layer 218. BOX layer 227 forms a buried insulating layer between semiconductor substrate 229 and first side 220 of semiconductor layer 218.

[0043] Continue to refer to Figure 2BRFIC 204 also includes a BEOL interconnect structure 224 adjacent to semiconductor layer 218. Typically, after the semiconductor substrate of semiconductor layer 218 has been manufactured and active components 225 have been formed in semiconductor layer 218 as part of front-end process line (FEOL) manufacturing process, BEOL interconnect structure 224 is formed on semiconductor layer 218 as part of BEOL manufacturing process in wafer manufacturing process. BEOL interconnect structure 224 includes a plurality of metal layers 226(1)-226(4) (also referred to as metallization layers 226(1)-226(4)) adjacent to each other in the vertical direction (Z-axis direction), each metal layer including metal interconnects 228(1)-228(4) formed as metal traces or metal lines in the corresponding insulating layers 230(1)-230(4). Second vias 232(1)-232(3) (e.g., through-silicon vias (TSVs)) are formed in corresponding metal layers 226(2)-226(4) to interconnect metal interconnects 228(1)-228(4) in the different metal layers 226(1)-226(4), thereby forming a signal routing path to the RF IC 204 and between the RF IC 204 and the antenna substrate 210. The BEOL interconnect structure 224 has a front side 234 and a second side 236 opposite to the front side 234 in the vertical direction (Z-axis direction). In this example, the second side 236 of the BEOL interconnect structure 224 is adjacent to and coupled to the semiconductor layer 218 and its RF circuit 206. Side 234 of the BEOL interconnect structure 224 is also referred to as the “front side” 234 of the RF IC 204 because it is the side of the RF IC 204 adjacent to the external metal interconnect, wherein the die 200 is coupled to an external device as part of the BEOL interconnect structure 224. The front side 234 of the RF IC 204 and the BEOL interconnect structure 224 is one side of the RF IC 204, wherein the metal interconnect 228(1) forming the BEOL interconnect structure 224 provides a connection to the RF circuit 206. (Refer to...) Figure 2A and 2BAntenna substrate 210 is provided in die 200 adjacent to the back side 222 of RF IC 204. In this example, antenna substrate 210 is not directly adjacent to the back side 222 of RF IC 204, which is disposed on the same side of the back side 222 of RF IC 204 opposite to the front side 234 of RF IC 204, because, as discussed below, dielectric substrate 250 is disposed between antenna substrate 210 and the back side 222 of RF IC 204 in the vertical direction (Z-axis direction). Indirect (or indirect) adjacency means that one object (e.g., antenna substrate 210) is not directly next to or in contact with another object (e.g., back side 222), but there is another intervening object between these objects. Alternatively, antenna substrate 210 may be directly adjacent to the back side 222 of RF IC 204. Directly adjacent objects are objects that are directly adjacent to or coupled to each other, and there is no intervening object between them.

[0044] exist Figure 2A and 2BIn this example die 200, the antenna substrate 210 includes multiple antenna layers 238(1)-238(3). The antenna layers 238(1)-238(3) may be metal layers or metallization layers manufactured as or similar to the metal layers 226(1)-226(4) in the BEOL interconnect structure 224. Metal interconnects 240(1)-240(3) in the form of metal lines or traces may be formed in the respective antenna layers 238(1)-238(3). In this example, the metal interconnects 240(3) formed in the first antenna layer 238(3) are antenna elements 208(1)-208(6), each antenna element forming a corresponding antenna 212(1)-212(6). For example, the antenna elements 208(1)-208(6) may be metal patch antennas. For example, since the antenna substrate 210 can be manufactured as an integrated portion of the die 200, the same wafer-level processing techniques used to manufacture the RF IC 204 can also be used to manufacture the antenna layers 238(1)-238(3) of the antenna substrate 210. In this way, it is feasible to manufacture metal interconnects 240(1)-240(3) (e.g., metal lines or metal traces) in the respective antenna layers 238(1)-238(3) with sufficiently small L / S metal patterns and / or pitch to form smaller antenna elements 208(1)-208(6) and metal interconnects 240(1)-240(3) with sufficient resolution to provide interconnections to the antenna elements 208(1)-208(6). For example, the antenna elements 208(1)-208(6) can each support a wavelength less than or equal to one (1) millimeter. Antenna substrate 210 can be fabricated by constructing antenna layers 238(1)-238(3) directly or indirectly adjacent to the back side 222 of RF IC 204, so that antenna elements 208(1)-208(6) do not need to be formed in BEOL interconnect structure 224 to minimize routing complexity in BEOL interconnect structure 224. In addition, it may be desirable to fabricate antenna substrate 210 directly or indirectly adjacent to the back side 222 of RF IC 204 so that the first clearance distance D2 between antenna elements 208(1)-208(6) and RF circuit 206 can be controlled to reduce transmission loss in RF signals conveyed by RF circuit 206 and antenna elements 208(1)-208(6), as discussed in more detail below.

[0045] For example, the first antenna layer 238(3) in the antenna substrate 210 in which antenna elements 208(1)-208(6) are formed can be formed as a first redistribution layer (RDL), which includes metal interconnects 240(3) embedded in a corresponding dielectric insulating layer 242(3) of the first antenna layer 238(3). In this example, the second antenna layer 238(2) of the antenna layers 238(1)-238(2) is also a second RDL, with its metal interconnects 240(2) embedded in the insulating layer 242(2), such that the antenna substrate 210 is a multi-level RDL. A non-limiting advantage of providing one or more antenna layers 238(2), 238(3) including the first antenna layer 238(3) as an RDL is the ability to redistribute signal routes within and between the antenna substrate 210 and the BEOL interconnect structure 224. For example, a first via 244 is formed in die 200 to interconnect metal interconnects 240(1) in antenna layer 238(1) to metal interconnects 228(4) in first metal layer 226(4) in BEOL interconnect structure 224. This provides a signal routing path between antenna elements 208(1)-208(6) in antenna substrate 210 and RF circuit 206 via interconnects 228(1)-228(4) coupled to the first via 244 to the RF circuit 206. For example, the first via 244 may be a TSV. The first via 244 is arranged in the vertical direction (Z-axis direction) in the die 200, but the signal routing path including the first via 244 can be redistributed in the horizontal direction (X-axis and / or Y-axis direction) through the RDL in the antenna layers 238(2), 238(3) to couple to other metal interconnects 240(2)-240(3) and the desired antenna elements 208(1)-208(6).

[0046] Another non-limiting benefit of providing one or more antenna layers 238(2)-238(3) including the first antenna layer 238(3) as an RDL is to provide a reduced layer height in the vertical direction (Z-axis direction). This is in part because the metal interconnects 240(2), 240(3) in the respective antenna layers 238(2), 238(3) are embedded in the respective insulating layers 242(2), 242(3). The process of forming the metal interconnects 240(2), 240(3) in the corresponding antenna layers 238(2), 238(3) as RDLs also allows the metal interconnects 240(2), 240(3) to be formed from smaller L / S metal patterns and / or formed with smaller pitches, so that, for example, the antenna elements 208(1)-208(6) can be made in smaller dimensions to support smaller wavelengths, thereby supporting higher RF frequencies, and to provide sufficiently fine resolution for the metal interconnects 240(2), 240(3) to provide interconnections with the antenna elements 208(1)-208(6). For example, the metal interconnects 240(1)-240(3) formed in the antenna layers 238(1)-238(3) can have L / S metal patterns of less than 3 μm. As another example, the pitch of the metal interconnects 240(1)-240(3) formed in the antenna layers 238(1)-238(3) can be less than five (5) μm, and as another example, it is between 3.0 and 5.0 μm. As another example, the antenna elements 208(1)-208(2) can be manufactured in the first antenna layer 238(3) to have a dimension of less than or equal to 500 μm in the horizontal direction (X-axis and Y-axis direction). For example, the antenna elements 208(1)-208(6) can be manufactured in the first antenna layer 238(3) to have a dimension of less than 1 millimeter (mm) in the horizontal direction (X-axis and Y-axis direction). As another example, the dimension of the antenna elements 208(1)-208(6) can be less than or equal to 500 μm to support higher frequencies. For example, in order to support D-band frequencies, the size of antenna elements 208(1)-208(6) can be set to be a metal patch antenna of approximately 150μm×150μm in the first antenna layer 238(3).

[0047] As described above, the first clearance distance D2 between the antenna elements 208(1)-208(6) and the RF circuit 206 affects the transmission loss of the RF signal between the antenna elements 208(1)-208(6) and the RF circuit 206. Figure 2B As shown, by integrating the antenna substrate 210 with the RF IC 204, which is part of the die 200, the first clearance distance D2 can be reduced because antenna layers 238(1)-238(2) with reduced vertical (Z-axis) height can be formed in the antenna substrate 210. This is consistent with the fact that... Figure 1A and 1BCompared to the antenna substrate 102 in the package substrate 110 of the AiP antenna module 100, it has a greater height in the vertical direction (Z-axis direction) than the antenna substrate 210 in the die 200. For example, a first clearance distance D2 between the antenna elements 208(1)-208(6) and the RF circuit 206 is expected to be between seventy (70) and eighty (80) μm to support higher frequency RF signals.

[0048] In this example, a dielectric substrate 250 is also provided in the die 200 not only to provide a substrate for forming the antenna substrate 210 during the manufacturing of the die 200, but also to control the first clearance distance D2 between the antenna elements 208(1)-208(6) and the RF circuit 206. The dielectric substrate 250 is disposed between the antenna substrate 210 and the RF IC 204 in the die 200, and more specifically, between the back side 222 of the RF IC 204 and its semiconductor layer 218. For example, the dielectric substrate 250 may be a silicon substrate, which is an readily available material for wafer-level processing and can be used to form the dielectric substrate 250 during the manufacturing of the die 200. The first thickness or first height H1 of the dielectric substrate 250 may be controlled during the manufacturing of the die 200 (e.g., by a polishing process) to control the first clearance distance D2 between the antenna elements 208(1)-208(6) and the RF circuit 206. For example, the first height H1 of the dielectric substrate 250 can be between 50 and 60 μm. For example, in order to achieve a first clearance distance D2 between seventy (70) and eighty (80) μm between the antenna elements 208(1)-208(6) and the RF circuit 206 to support higher frequency RF signals, the first height H1 of the dielectric substrate 250 between the antenna substrate 210 and the back side 222 of the RF IC 204 can be between 40 and 60 μm.

[0049] The dielectric constant of the dielectric substrate 250 can affect the RF transmission loss in the RF signal between the RF circuit 206 and the antenna elements 208(1)-208(6). For example, the dielectric substrate 250 can be formed from a dielectric material such that it has a dielectric constant of less than 6.0 farads per meter (F / m). The selection and manufacturing method of forming the dielectric substrate 250 and controlling its dielectric material also allow control of the loss tangent and resistivity of the dielectric substrate 250 to control the RF transmission loss. For example, the dielectric substrate 250 can be selected from a dielectric material and manufactured such that its loss tangent at 20 GHz is approximately 2 × 10⁻⁶. -3 As another example, the dielectric material substrate 250 may be selected from the dielectric material and manufactured to have a resistivity greater than 10. 7Ohms per centimeter (cm). The antenna module 202 integrated in the die 200 may have various improvements, such as improved isolation between RF circuits 206 (e.g., >= 20 dB), the antenna 212 has an effective isotropic radiated power (EIRP) of approximately 2 dB, and has a reduction in overall cost.

[0050] Figure 3 This is a side view of an exemplary electronic device 300, which includes as... Figure 2A and 2B The die 200 of the antenna module 202 is coupled to the package substrate 302. For example, the package substrate 302 may include a metallization layer 304 that provides signal routing paths to and from the antenna module 202. Die interconnects 306 (e.g., metal pads, microbumps, bumps formed on under-bump metallization (UBM) pads) are formed in contact with metal interconnects 228 (1) in the metal layer 226 (1) of the BEOL interconnect structure 224, and these metal interconnects 228 (1) are then coupled to the package substrate 302. The package substrate 302 may be a package substrate including a metallization layer, such as a package substrate with a metallization layer. Figure 1A and 1B The metallized substrate 116 is in the middle. External interconnects 308 (e.g., solder bumps, ball grid array (BGA) interconnects) are formed to contact the package substrate 302 and can be coupled to the printed circuit board (PCB) 310 to electrically couple the antenna module 202 to the PCB 310 and other electronic circuits coupled to the PCB 310.

[0051] Reference Figure 2A and 2B Introducing the dielectric substrate 250 into the die 200 may result in unintended consequences such as RF transmission loss in the RF signal between the RF circuit 206 and the antenna elements 208(1)-208(6). The dielectric constant of the dielectric substrate 250 can affect the RF transmission loss in the RF signal between the RF circuit 206 and the antenna elements 208(1)-208(6). For example, the dielectric substrate 250, formed of silicon and serving as a silicon substrate, may have a higher dielectric constant than FR4 or another material used to manufacture the packaging substrate, such as... Figure 1A and 1BThe packaging substrate 110 in the antenna module 100. Therefore, although the introduction of the dielectric substrate 250 can help control the first clearance distance D2 between the antenna elements 208(1)-208(6) and the RF circuit 206 between seventy (70) and eighty (80) μm to support higher frequency RF signals, the dielectric substrate 250 can also cause RF transmission loss in the RF signal between the RF circuit 206 and the antenna elements 208(1)-208(6) in an unintended and undesirable manner, which may cause the antenna module 202 to fail to support the desired spectrum with sufficient performance.

[0052] In this regard, Figure 4 This is a side view of another exemplary die 400, which provides an integrated antenna module 402 integrated into the die 400, and the integrated antenna module 402 is capable of supporting higher frequency RF signals (e.g., D-band frequencies). However, the die 400 does not need to support any specific frequency or band of RF signals. As an example, the die 400 may be provided as part of a single IC chip 409, which is manufactured as part of a wafer-level manufacturing process. Figure 4 The 400 core and Figure 2A and 2B Common components among the dies 200 are shown by common component numbers and will not be described further. However, in Figure 4 In the 400-type die, similar to Figure 2A and 2B The dielectric material substrate 450 of the dielectric material substrate 250 in the die 200 is provided as a porous silicon substrate to control its dielectric constant. For example, during the manufacture of the die 400, a porousing process can be performed on the dielectric material substrate 450, which is a silicon substrate, to control and tune its dielectric constant and loss tangent to desired levels, thereby achieving the desired performance of the supported communication frequencies. The porousing of the dielectric material substrate 450, which is a silicon substrate, is controlled to control the transmission loss between the antenna elements 208(1)-208(6) in the antenna substrate 210 and the RF IC 204. For example, the dielectric material substrate 450, which is a porous silicon substrate, may have a dielectric constant between 4 F / m and 6 F / m. As another example, the dielectric material substrate 450, which is a porous silicon substrate, may have a dielectric constant of less than 6.0 F / m.

[0053] Also in Figure 4In this example of die 400, to avoid damage to the semiconductor layer 218 during the porousification process performed on the dielectric substrate 450, which serves as a silicon substrate, an etch stop layer 452 (e.g., a nitride layer) may be disposed on the dielectric substrate 450 as a shank layer before the semiconductor layer 218 is formed on the dielectric substrate 450. The etch stop layer 452 prevents the porousification of the semiconductor layer 218 when the silicon substrate is processed into a porous silicon layer.

[0054] Figure 5 This is a side view of another exemplary die 500, which provides an integrated antenna module 502 integrated into the die 500, and the integrated antenna module 502 is capable of supporting similar... Figure 4 The die 400 in the chip can transmit higher frequency RF signals (e.g., D-band frequencies). As an example, the die 500 may be provided as part of a single IC chip 509, which is manufactured as part of a wafer-level manufacturing process. Figure 5 The 500 core and Figure 4 The common components among the dies 400 are shown by common component numbers and will not be described again. However, in Figure 5 Among the 500 cores, there are those similar to Figure 4 The RF IC 204 in the MOSFET 400 is an RF IC 504. However, Figure 5 The RF IC 504 in the 500 chip is a bulk device, not an SOI device. Figure 5 In this configuration, the antenna substrate 210 of the die 500 is formed adjacent to a bulk semiconductor material layer on a dielectric material substrate 450 (e.g., a bulk silicon substrate) such that the die 500 is a bulk device. In this respect, Figure 4 The BOX layer 227 in die 400 does not exist. Figure 5 The RF IC 504 is located in die 500. RF IC 504 includes a semiconductor substrate 529 (e.g., a silicon substrate) adjacent to the back side 222 of semiconductor layer 218. It should also be noted that, although... Figure 5 The die 500 includes a dielectric material substrate 450 as a porous silicon substrate, but this is not necessary. The dielectric material substrate 450 need not be a silicon substrate, and need not be a porous substrate.

[0055] There are various ways to form and manufacture an antenna module, which includes a die providing the antenna module, wherein the die includes an RF IC having RF circuitry, and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC, and the die includes, but is not limited to, […]. Figures 2A-5 The cores in the tubes are 200, 400, and 500. In this regard, Figure 6This is a flowchart illustrating an exemplary manufacturing process 600 used to manufacture this die. As an example, combined with... Figure 2A and 2B Discussion of the 200-inch die in the middle Figure 6 The manufacturing process is 600, but this is not limiting.

[0056] In this regard, such as Figure 6 The manufacturing process 600 shown, which forms die 200, includes forming semiconductor layer 218. Figure 6 In box 602), semiconductor layer 218 includes a first side 220, a back side 222 opposite to the first side 220, and RF circuitry 206. Manufacturing process 600 also includes forming a BEOL interconnect structure 224, which is coupled to the RF circuitry 206 for die 200. Figure 6 (See box 604 in the image). The BEOL interconnect structure 224 includes a front side 234 and a second side 236 opposite to the front side 234. The second side 236 of the BEOL interconnect structure 224 is adjacent to the semiconductor layer 218. In this example, the second side 236 of the BEOL interconnect structure 224 is coupled to the semiconductor layer 218 and is also adjacent to the RF circuit 206. The manufacturing process 600 for forming the die 200 may further include forming an antenna substrate 210, which is adjacent to the back side 222 of the semiconductor layer 218. Figure 6 (in frame 606). The manufacturing process 600 for forming the die 200 may further include forming one or more first through-holes 244, each of which couples one or more antenna elements 208(1)-208(6) to the BEOL interconnect structure 224 to couple one or more antenna elements 208(1)-208(6) to the RF circuit 206 (in frame 606). Figure 6 (Box 608 in the middle).

[0057] Other manufacturing methods may also produce a die for providing an antenna module, wherein the die includes an RFIC with RF circuitry and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RFIC. For example, Figures 7A-7E This is a flowchart of another exemplary manufacturing process 700, used to manufacture such as Figures 2A-5 The 200, 400, and 500 dies in the tubes, and they are based on Figures 8A-8F The exemplary manufacturing stages 800A-800F in the example describe a die that is an SOI device with RF circuitry, and an integrated antenna substrate for manufacturing an antenna for the RF circuitry. The die further includes a dielectric material layer disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and control the clearance between the antenna element and the RF circuitry to control transmission loss. The die includes, but is not limited to, […]. Figures 2A-5The cores in the tubes are 200, 400, and 500. According to... Figures 7A-7E Exemplary manufacturing process 700 in the example, Figures 8A-8F The manufacturing stages 800A-800F will now be discussed regarding SOI devices. Figure 4 The die 400 in the example is discussed as a non-limiting example.

[0058] In this regard, such as Figure 8A As shown in the exemplary manufacturing stage 800A, the first step in the manufacturing process 700 is to provide a starter wafer 802, in which layers will be processed and built to form a die 400. Figure 7A (See box 702 in the image). Note that after the initial wafer 802 has been fully processed following the complete formation of its layers, it will be cut into separate dies, which will be similar to... Figure 4 The 400 core in the tube.

[0059] In this regard, such as Figure 8A As shown in the exemplary manufacturing stage 800A, the manufacturing process 700 includes forming a dielectric material substrate 804 (during which it is processed to form...) Figure 4 Before the dielectric material substrate 450 in the middle, it can be a silicon substrate ( Figure 7A (See box 702 in the text). Additionally, as... Figure 8A As shown in manufacturing stage 800A, an etch stop layer 452 is formed on the dielectric material substrate 804. Figure 7A (See box 702 in the diagram). As previously discussed, the etch stop layer 452 is used to protect the RF IC 204 from damage during the porosification of the dielectric substrate 804 in subsequent processing steps to control its dielectric constant. For example, the etch stop layer 452 may be formed of silicon nitride. As an example, the thickness of the etch stop layer 452 may be 1000 angstroms. In addition, such as Figure 8A As shown in manufacturing stage 800A, a semiconductor layer in the form of a BOX layer 227 and an insulating layer 806 is formed as part of the semiconductor layer 218 to be formed on the etch stop layer 452 to form an active component. Figure 7A (Box 702 in the middle).

[0060] Subsequently, as Figure 8B As shown in exemplary manufacturing stage 800B, the semiconductor layer 218 of RF IC 204 is formed as part of the FEOL manufacturing process. Figure 7A (Box 704 in the image). RF circuitry 206 is formed in semiconductor layer 218 ( Figure 7A (See box 704 in the image). BEOL interconnect structure 224 is also formed adjacent to semiconductor layer 218 as part of the BEOL fabrication process to form RFIC 204. Figure 7A(See box 704 in the image). In this example, the process is part of a CMOS manufacturing process.

[0061] Subsequently, as Figure 8C As shown in the exemplary manufacturing stage 800C, a temporary shank die 808 (“shank die 808”) is attached to an RF IC 204 adjacent to the BEOL interconnect structure 224. Figure 7B (See box 706 in the image). Therefore, the starting wafer 802 can be disposed to process the dielectric substrate 450 to control its final first height H1, thereby controlling the clearance between the RF circuit 206 and the antenna elements 208(1)-208(6) in the antenna substrate 210 for integration as part of the die 400. For example, the dielectric substrate 450 can be thinned to control its final first height H1 (see box 706 in the image). Figure 7B (See box 706 in the image). As an example, the dielectric substrate 450 can be thinned so that its first height H1 is between 50-60 μm. Subsequently, as... Figure 8D As shown in exemplary manufacturing stage 800D, a hard mask layer 810 is formed on the shank wafer 808. Figure 7C The hard mask layer 810 is configured to protect the starting wafer 802 when the dielectric substrate 450 is subsequently porous (e.g., porous silicon) to control its dielectric constant. For example, the hard mask layer 810 may be a low-pressure chemical vapor deposition (LPCVD) silicon nitride layer.

[0062] Subsequently, as Figure 8E As shown in exemplary manufacturing stage 800E, a porousing process is performed on dielectric material substrate 450 to make dielectric material substrate 450 a porous substrate in order to control its dielectric constant. Figure 7D (See box 710 in the figure). The amount of porosity added to the dielectric substrate 450 controls its dielectric constant. For example, the dielectric substrate 450 can be transformed into a porous substrate by electrolytic etching of the dielectric substrate 450 in hydrofluoric acid (HF) and ethanol. The electrolytic etching stops at the etch stop layer 452. Furthermore, as... Figure 8E As shown in manufacturing stage 800E, the hard mask layer 810 and the shank wafer 808 are removed. Figure 7D (Box 710 in the middle).

[0063] Subsequently, as Figure 8F As shown in exemplary manufacturing stage 800F, antenna substrate 210 is formed on dielectric material substrate 450. Figure 7E (See box 712). Antenna substrate 210 may be constructed on separate antenna layers 238(1)-238(3) on dielectric substrate 450 (see box 712). Figure 4In this context, it can be an RDL layer as described above. Antenna layers 238(1)-238(3) can be formed and constructed as RDL layers on a photopolymer polyimide material on a dielectric substrate 450. Antenna elements 208(1)-208(6) are formed in the first antenna layer 238(3). Furthermore, as Figure 8F As shown in the exemplary manufacturing stage 800F, a first via 244 is formed through the dielectric substrate 450, the etch stop layer 452, and the RF IC 204 to couple the metal interconnect 240(1) in the antenna layer 238(1) to the metal interconnect 228(4) in the BEOL interconnect structure 224. Figure 7E (See box 712 in the image). As an example, the first via 244 can be formed by a drilling process. The first via 244 provides a signal routing path between the antenna elements 208(1)-208(6) in the antenna substrate 210 and the BEOL interconnect structure 224, and then provides these signal routing paths to the RF circuit 206 in the RF IC 204.

[0064] Figures 9A-9E This is a flowchart of another exemplary manufacturing process 900, which is used to manufacture something similar to... Figure 5 The die 500 is used as the body device, and according to Figures 10A-10F Exemplary manufacturing stages 1000A-1000F. According to Figures 9A-9E Exemplary manufacturing process 900, Figures 10A-10F Manufacturing stages 1000A-1000F in the present invention will now be used as non-limiting examples regarding Figure 5 We will discuss the 500 core in the process.

[0065] In this regard, such as Figure 10A As shown in the exemplary manufacturing stage 1000A, the first step in the manufacturing process 900 is to provide a starter wafer 1002, in which layers are processed and built to form a die 500. Figure 9A (See box 902 in the image). Note that after the starting wafer 1002 has been fully processed following its complete layer formation, it will be cut into separate dies, which will resemble... Figure 5 The 500mm die in the tube. (For example...) Figure 10A As shown in the exemplary manufacturing stage 1000A, the manufacturing process 900 includes forming a dielectric material substrate 1004, which may be a silicon substrate. Figure 9A (See box 902 in the text). Additionally, as... Figure 10A As shown in manufacturing stage 1000A, an etch stop layer 452 is formed on the dielectric material substrate 1004. Figure 9A(See box 902 in the diagram). As previously discussed, the etch stop layer 452 is used to protect the RF IC 504 from damage during the porosification of the dielectric substrate 1004 in subsequent processing steps to control its dielectric constant. For example, the etch stop layer 452 may be formed of silicon nitride. As an example, the thickness of the etch stop layer 452 may be 1000 angstroms. In addition, such as Figure 10A As shown in manufacturing stage 1000A, semiconductor layers in the form of a silicon substrate 1006 are formed as part of the semiconductor layer 218 to be formed on the etch stop layer 452 to form an active component. Figure 9A (Box 902 in the middle).

[0066] Subsequently, as Figure 10B As shown in exemplary manufacturing stage 1000B, the semiconductor layer 218 of RF IC 504 is formed as part of the FEOL manufacturing process. Figure 9A (Box 904 in the image). RF circuit 206 is formed in the semiconductor layer ( Figure 9A (Box 904 in the middle). The BEOL interconnect structure 224 is also formed as part of the BEOL fabrication process adjacent to the semiconductor layer 218 to form the RFIC 504 ( Figure 9A (See box 904 in the image). In this example, the process is part of a CMOS manufacturing process.

[0067] Subsequently, as Figure 10C As shown in the exemplary manufacturing stage 1000C, a temporary shank die 1008 (“shank die 808”) is attached to an RFIC 504 adjacent to the BEOL interconnect structure 224. Figure 9B (in box 906). Therefore, the starting wafer 1002 can be disposed to process the dielectric substrate 450 to control its final first height H1, thereby controlling the clearance between the RF circuit 206 and the antenna elements 208(1)-208(6) in the antenna substrate 210 for integration as part of the die 500. For example, the dielectric substrate 450 can be thinned to control its final first height H1 (in box 906). Figure 9B (See box 906 in the image). As an example, the dielectric substrate 450 may be thinned so that its first height H1 is between 50 and 60 μm.

[0068] Subsequently, as Figure 10D As shown in exemplary manufacturing stage 1000D, a hard mask layer 1010 is formed on the shank wafer 1008. Figure 9CThe hard mask layer 1010 is configured to protect the starting wafer 1002 when the dielectric substrate 450 is subsequently porous (e.g., porous silicon) to control its dielectric constant. For example, the hard mask layer 1010 may be a low-pressure chemical vapor deposition (LPCVD) silicon nitride layer.

[0069] Subsequently, as Figure 10E As shown in the exemplary manufacturing stage 1000E, a porousing process is performed on a dielectric material substrate 450 to make the dielectric material substrate 450 a porous substrate in order to control its dielectric constant. Figure 9D (See box 910 in the image). The amount of porosity added to the dielectric substrate 450 controls its dielectric constant. For example, the dielectric substrate 450 can be transformed into a porous substrate by electrolytic etching of the dielectric substrate 450 in hydrofluoric acid (HF) and ethanol. The electrolytic etching stops at the etch stop layer 452. Furthermore, as... Figure 10E As shown in manufacturing stage 1000E, the hard mask layer 1010 and the shank wafer 1008 are removed. Figure 9D (Box 910 in the middle).

[0070] Subsequently, as Figure 10F As shown in the exemplary manufacturing stage 1000F, the antenna substrate 210 is formed on the dielectric material substrate 450. Figure 9E (See box 912). Antenna substrate 210 may be constructed on dielectric substrate 450 with separate antenna layers 238(1)-238(3) (as shown in the figure). Figure 5 As shown in the diagram, it can be an RDL layer as previously described. Antenna layers 238(1)-238(3) can be formed and constructed as RDL layers on a photopolymer polyimide material on a dielectric substrate 450. Antenna elements 208(1)-208(6) are formed in the first antenna layer 238(3). Furthermore, as shown in the diagram... Figure 10F As shown in the exemplary manufacturing stage 1000F, a first via 244 is formed through the dielectric substrate 450, the etch stop layer 452, and the RF IC 504 to couple the metal interconnect 240(1) in the antenna layer 238(1) to the metal interconnect 228(4) in the BEOL interconnect structure 224. Figure 9E (See box 912 in the image). As an example, the first via 244 can be formed by a drilling process. The first via 244 provides a signal routing path between the antenna elements 208(1)-208(6) in the antenna substrate 210 and the BEOL interconnect structure 224, and then provides these signal routing paths to the RF circuit 206 in the RF IC 504.

[0071] Note that the discussion above... Figures 2A-5 , Figure 8F and Figure 10FExamples of dies 200, 400, and 500 refer to their corresponding antennas 212, which are capable of supporting specific exemplary frequencies and / or bands, including the D-band spectrum. Note that antenna 212 is not so limited. Figures 2A-5 , Figure 8F and Figure 10F The antenna 212 in the die 200, 400, 500 and / or any other die providing the antenna module (where the die includes an RF IC with RF circuitry and an integrated antenna substrate providing the antenna for the RF circuitry) can be designed and manufactured to support any desired frequency and / or spectrum, including but not limited to 5G and 6G bands as well as lower and higher frequency bands.

[0072] The term "adjacent" as discussed in this article refers to an object located next to or adjacent to another object. Adjacent objects may not be physically coupled to each other. An object may be directly adjacent to another object, meaning that these objects are directly next to or adjacent to another object without any other object or layer intervening or being arranged between the directly adjacent objects. An object may be indirectly or indirectly adjacent to another object, meaning that these objects are not directly next to or adjacent to each other, but rather an intermediary object or layer is arranged between the non-directly adjacent objects.

[0073] The die providing the antenna module can be provided in or integrated into any wireless communication device and / or processor-based device, wherein the die includes an RF IC with RF circuitry and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the die further includes a dielectric material layer disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and control the clearance distance between the antenna element and the RF circuitry to control transmission loss, and the die includes, but is not limited to, […]. Figures 2A-5 , Figure 8F and Figure 10F The cores in the tubes are 200, 400, and 500, and can be customized according to... Figure 6 , Figures 7A-7E and Figures 9A-9EAny of the exemplary manufacturing processes 600, 700, or 900. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SiP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0074] Figure 11 An exemplary wireless communication device 1100 including an antenna module 1102 has been described. The antenna module 1102 is provided in the form of a die 1103, which includes an RF IC having RF circuitry and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC. As a non-limiting example, the die 1103 may include… Figures 2A-5 , Figure 8F or Figure 10F The cores in the tubes are 200, 400, and 500, and can be customized according to... Figure 6 , Figures 7A-7E or Figures 9A-9E It can be manufactured using any of the following manufacturing processes: 600, 700, or 900. Figure 11 As shown, the wireless communication device 1100 includes an RF transceiver 1104 and a data processor 1106. Components of the RF transceiver 1104 and / or the data processor 1106 may be disassembled into multiple different chips 1105(1), 1105(2). The data processor 1106 may include memory for storing data and program code. The RF transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. Generally, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the RF transceiver 1104 may be implemented on one or more analog ICs, RF ICs, mixed-signal ICs, etc.

[0075] Transmitter 1108 or receiver 1110 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 1110, it might be from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 11 In the wireless communication device 1100, the transmitter 1108 and the receiver 1110 are implemented using a direct frequency conversion architecture.

[0076] In the transmission path, data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1108. In the exemplary wireless communication device 1100, data processor 1106 includes digital-to-analog converters (DACs) 1112(1) and 1112(2) to convert digital signals generated by data processor 1106 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0077] Within transmitter 1108, low-pass filters 1114(1) and 1114(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1116(1) and 1116(2) amplify the signals from low-pass filters 1114(1) and 1114(2), respectively, and provide I and Q baseband signals. Upconverter 1118 upconverts the I and Q baseband signals from transmit (TX) local oscillator (LO) signal generator 1122 using mixers 1120(1) and 1120(2) to provide upconverted signal 1124. Filter 1126 filters upconverted signal 1124 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1128 amplifies the up-converted signal 1124 from filter 1126 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1130 and transmitted via antenna 1132.

[0078] In the receiving path, antenna 1132 receives signals transmitted by the base station and provides a received RF signal, which is routed through duplexer or switch 1130 and provided to low-noise amplifier (LNA) 1134. Duplexer or switch 1130 is designed to operate with specific receive (RX) and TX duplexer frequencies separated, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Downconversion mixers 1138(1) and 1138(2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1) and 1142(2) and further filtered by low-pass filters 1144(1) and 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes analog-to-digital converters (ADCs) 1146(1) and 1146(2) to convert the analog input signals into digital signals to be further processed by data processor 1106.

[0079] exist Figure 11 In the wireless communication device 1100, a TX LO signal generator 1122 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1140 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1148 receives timing information from a data processor 1106 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1122. Similarly, an RXILL circuit 1150 receives timing information from a data processor 1106 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1140.

[0080] Figure 12 An example of a processor-based system 1200 is described, which may include an antenna module in the form of dies 1202, 1202(1)-1202(6). Dies 1202, 1202(1)-1202(6) include an RF IC having RF circuitry, and an integrated antenna substrate providing an antenna for the RF circuitry, wherein the antenna substrate is adjacent to the back side of the RF IC. As a non-limiting example, dies 1202, 1202(1)-1202(6) may include Figures 2A-5 , Figure 8F or Figure 10F The cores in the tubes are 200, 400, and 500, and can be customized according to... Figure 6 , Figures 7A-7E or Figures 9A-9E It can be manufactured using any of the following manufacturing processes: 600, 700, or 900.

[0081] In this example, the processor-based system 1200 may be configured as a system-on-a-chip (SoC) 1206 including a die 1202. The processor-based system 1200 includes a CPU 1208, which includes one or more processors 1210, which may also be referred to as CPU cores or processor cores. The CPU 1208 may have a cache memory 1212 coupled to the CPU 1208 for fast access to data in temporary storage. The CPU 1208 is coupled to a system bus 1214 and may be coupled to master and slave devices included in the processor-based system 1200. As is well known, the CPU 1208 communicates with these other devices by exchanging address, control, and data information on the system bus 1214. For example, the CPU 1208 may communicate a bus transaction request to a memory controller 1216, which is an example of a slave device. Although in Figure 12 Not described in the text, but multiple system buses 1214 may be provided, each system bus 1214 forming a different texture. CPU 1208 may include die 1202 (1).

[0082] Other master and slave devices can be connected to system bus 1214. For example... Figure 12As explained herein, by way of example, these devices may include a memory system 1220 (which may include die 1202(2)) including a memory controller 1216 and a memory array 1218, one or more input devices 1222 (which may include die 1202(3)), one or more output devices 1224 (which may include die 1202(4)), one or more network interface devices 1226 (which may include die 1202(5)), and one or more display controllers 1228 (which may include die 1202(6)). Each of the memory system 1220, one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228 may be provided in the same or different IC packages. Input devices 1222 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1224 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (Various) Network interface devices 1226 may be any device configured to allow data exchange to and from network 1230. Network 1230 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. TM Networks, including the Internet. The network interface device 1226 can be configured to support any type of communication protocol desired.

[0083] CPU 1208 can also be configured to access display controllers 1228 via system bus 1214 to control information sent to one or more displays 1232. Display controllers 1228 send information to be displayed to the displays 1232 via one or more video processors 1234, which process the information to be displayed into a format suitable for the displays 1232. For example, display controllers 1228 and video processors 1234 may be included in the same or different IC packages, and in the same or different IC packages containing CPU 1208. Displays 1232 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0084] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in their functional form. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0085] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0086] The aspects disclosed herein can be implemented in hardware and instructions stored in hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read / write information from / to the storage medium. In alternatives, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. In alternatives, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0087] It should also be noted that the operational steps described in any exemplary aspect of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order explained. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps explained in the flowcharts. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0088] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

[0089] Examples of implementations are described in the following numbered clauses:

[0090] 1. A semiconductor die, comprising:

[0091] Semiconductor layer, including:

[0092] First side;

[0093] The dorsal side, which is opposite to the first side; and

[0094] Radio frequency (RF) circuits;

[0095] Back-end process online (BEOL) interconnect structure coupled to RF circuitry, the BEOL interconnect structure comprising:

[0096] Front side; and

[0097] The second side is opposite to the front side and is coupled to the first side of the semiconductor layer;

[0098] Antenna substrate, which is adjacent to the back side of the semiconductor layer;

[0099] The antenna substrate includes one or more antenna layers, and a first antenna layer in the one or more antenna layers includes one or more antenna elements; and

[0100] One or more first vias, each of which couples one or more antenna elements in the antenna element to a BEOL interconnect structure to couple the one or more antenna elements to an RF circuit.

[0101] 2. The semiconductor die as described in Clause 1, wherein: the first antenna layer includes a metal layer, the metal layer including one or more metal structures, the one or more metal structures including one or more antenna elements.

[0102] 3. The semiconductor die as described in Clause 2, wherein: the first antenna layer has a metal pattern with a line spacing (L / S) of less than 3 μm.

[0103] 4. A semiconductor die of any of the terms 1-3, wherein: the first antenna layer includes a first redistribution layer (RDL).

[0104] 5. A semiconductor die as described in any of Clauses 1-3, wherein: each of the one or more antenna layers includes a redistribution layer (RDL).

[0105] 6. A semiconductor die of any of the terms 1-5, wherein: the one or more antenna elements comprise one or more metal patch antennas.

[0106] 7. A semiconductor die of any of the terms 1-6, wherein: each dimension of the one or more antenna elements is less than or equal to 500 micrometers (μm).

[0107] 8. A semiconductor die of any of the terms 1-7, wherein: each of the one or more antenna elements supports a wavelength of less than or equal to one (1) millimeter (mm).

[0108] 9. A semiconductor die of any of the terms 1-8, wherein: each of the one or more antenna elements supports at least one communication frequency between 110 and 170 GHz.

[0109] 10. The semiconductor die of any of Clauses 1-9 further includes: a dielectric material substrate between the back side of the semiconductor layer and the antenna substrate.

[0110] 11. The semiconductor die of Clause 10 further includes: an etch stop layer between the dielectric substrate and the semiconductor layer.

[0111] 12. Semiconductor dies as described in Clause 10 or 11, wherein: the dielectric substrate includes a silicon substrate.

[0112] 13. A semiconductor die as described in Clause 12, wherein: the silicon substrate includes a porous silicon substrate.

[0113] 14. A semiconductor die of any of the terms 10-13, wherein: the dielectric material substrate has a dielectric constant between 4 farads per meter (F / m) and 6 F / m.

[0114] 15. A semiconductor die of any of the terms 10-14, wherein: the dielectric constant of the dielectric material substrate is less than or equal to 5.0 farads per meter (F / m).

[0115] 16. A semiconductor die of any of Clauses 10-15, wherein: the dielectric substrate has a first thickness of 40 to 60 micrometers (μm) between the antenna substrate and the semiconductor layer.

[0116] 17. A semiconductor die of any of the terms 1-16, wherein: one or more antenna elements are each arranged at a first distance between seventy (70) and eighty (80) micrometers (μm) from the RF circuit.

[0117] 18. The semiconductor die of any of the terms 1-17 further includes: an integrated circuit (IC) including a semiconductor layer and a BEOL interconnect structure;

[0118] The IC includes a bulk device, and the semiconductor layer includes a bulk semiconductor material layer.

[0119] 19. The semiconductor die of any of the terms 1-17 further includes:

[0120] An integrated circuit (IC) including a silicon-on-insulator (SOI) device, the SOI device including a semiconductor layer and a BEO interconnect structure;

[0121] The semiconductor layer includes a buried oxide (BOX) layer adjacent to the front side and a semiconductor substrate adjacent to the back side, such that the BOX layer is located between the front side and the semiconductor substrate.

[0122] 20. A semiconductor die such as any of the terms 1-19, wherein

[0123] The BEOL interconnect structure includes multiple metal layers located between the front and second sides, each of the multiple metal layers including one or more metal interconnects; and

[0124] Each of the one or more first vias couples an antenna element in one or more antenna elements to one or more metal interconnects in a first metal layer of multiple metal layers; and

[0125] The semiconductor die further includes:

[0126] One or more second vias, each via coupled to an RF circuit, and each via coupled to one or more metal interconnects in a first metal layer of the plurality of metal layers.

[0127] 21. A semiconductor die of any of the terms 1-20, wherein: the one or more first vias include one or more first through-silicon vias (TSVs).

[0128] 22. A semiconductor die of any of the terms 1-21, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SiP) phones; tablet computers; phablets; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0129] 23. A method for manufacturing a semiconductor die, comprising:

[0130] A semiconductor layer is formed, the semiconductor layer comprising:

[0131] First side;

[0132] The dorsal side, which is opposite to the first side; and

[0133] Radio frequency (RF) circuits;

[0134] A back-end process online (BEOL) interconnect structure is formed, which is coupled to an RF circuit. The BEOL interconnect structure includes:

[0135] Front side; and

[0136] The second side is opposite to the front side and is coupled to the semiconductor layer.

[0137] An antenna substrate is formed adjacent to the back side of the semiconductor layer, comprising:

[0138] Forming one or more antenna layers, wherein a first antenna layer in the one or more antenna layers includes one or more antenna elements; and

[0139] One or more first vias are formed, each of which couples one or more antenna elements to a BEOL interconnect structure to couple the one or more antenna elements to an RF circuit.

[0140] 24. The method of Clause 23, wherein forming one or more antenna layers comprises: forming a first antenna layer, the first antenna layer comprising forming a metal layer, the metal layer comprising one or more metal structures, the one or more metal structures comprising one or more antenna elements in the first antenna layer.

[0141] 25. The method of Clause 23 or 24, wherein: forming the metal layer includes forming a first redistribution layer (RDL).

[0142] 26. The method of any of clauses 23-25, further comprising: forming a dielectric material substrate adjacent to the back side of the semiconductor layer; and

[0143] The formation of the antenna substrate further includes: forming the antenna substrate on a dielectric material substrate.

[0144] 27. The methods described in Clauses 23-25 ​​further include:

[0145] A dielectric substrate is formed adjacent to the back side of the semiconductor layer; and

[0146] An etch stop layer is formed on a dielectric material substrate;

[0147] The formation of the antenna substrate further includes: forming the antenna substrate adjacent to the etch stop layer.

[0148] 28. The method of clause 26 or 27, wherein forming the dielectric material substrate further comprises:

[0149] A silicon substrate is formed adjacent to the back side of the semiconductor layer; and

[0150] The silicon substrate is made porous to form a porous silicon substrate adjacent to the back side of the semiconductor layer.

[0151] 29. The method of any of clauses 23-28, wherein forming the BEOL interconnect structure further comprises: forming a plurality of metal layers between a front side and a second side, each of the plurality of metal layers comprising one or more metal interconnects; and

[0152] The method further includes forming one or more first vias in the antenna substrate and the BEOL interconnect structure, each of which couples the antenna element in the one or more antenna elements to the one or more metal interconnects in the first metal layer of the plurality of metal layers.

[0153] 30. The method of Clause 29 further includes: forming one or more second vias, each coupled to an RF circuit, and each via coupled to one or more metal interconnects in a first metal layer of the plurality of metal layers.

[0154] 31. The method of clause 29 or 30, wherein: forming the one or more first vias comprises: forming one or more first through-silicon vias (TSVs) in the antenna substrate and the BEOL interconnect structure, each of which couples the antenna element of the one or more antenna elements to the one or more metal interconnects in the first metal layer of the plurality of metal layers.

[0155] 32. The method of any of Clauses 26-31 further includes: thinning a dielectric substrate to a desired first thickness to control the distance between the one or more antenna elements and the RF circuit.

[0156] 33. The method of any of clauses 26-32, wherein forming the semiconductor layer further comprises:

[0157] A semiconductor substrate is formed on a dielectric material substrate, the semiconductor substrate including a back side; and

[0158] A buried oxide (BOX) layer formed on a semiconductor substrate;

[0159] in:

[0160] The formation of the BEOL interconnect structure further includes: forming the BEOL interconnect structure adjacent to the BOX layer.

[0161] 34. The method of any of clauses 26-32, wherein forming the semiconductor layer further comprises: forming a silicon layer on a dielectric material substrate, the silicon layer including a first side and a back side; and

[0162] in:

[0163] Forming a BEOL interconnect structure further includes: forming a BEOL interconnect structure adjacent to a silicon layer.

Claims

1. A semiconductor die, comprising: Semiconductor layer, including: First side; The back side, which is opposite to the first side; and Radio frequency (RF) circuits; Back-end process interconnect (BEOL) structure, the BEOL interconnect structure being coupled to the RF circuit, the BEOL interconnect structure comprising: Front side; and The second side is opposite to the front side and is coupled to the first side of the semiconductor layer; An antenna substrate, the antenna substrate being adjacent to the back side of the semiconductor layer; The antenna substrate includes one or more antenna layers, and a first antenna layer in the one or more antenna layers includes one or more antenna elements; and One or more first vias, each first via coupling one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuit.

2. The semiconductor die as claimed in claim 1, wherein: The first antenna layer includes a metal layer, the metal layer includes one or more metal structures, and the one or more metal structures include the one or more antenna elements.

3. The semiconductor die as described in claim 2, wherein: The first antenna layer has a metal pattern with a line spacing (L / S) of less than 3 μm.

4. The semiconductor die as claimed in claim 1, wherein: The first antenna layer includes a first redistribution layer (RDL).

5. The semiconductor die as claimed in claim 1, wherein: Each of the one or more antenna layers includes a redistribution layer (RDL).

6. The semiconductor die as claimed in claim 1, wherein: The one or more antenna elements include one or more metal patch antennas.

7. The semiconductor die as claimed in claim 1, wherein: Each of the one or more antenna elements has a dimension of less than or equal to 500 micrometers (μm).

8. The semiconductor die as claimed in claim 1, wherein: Each of the one or more antenna elements supports a wavelength of less than or equal to one (1) millimeter (mm).

9. The semiconductor die as claimed in claim 1, wherein: Each of the one or more antenna elements supports at least one communication frequency between 110 and 170 GHz.

10. The semiconductor die of claim 1, further comprising: A dielectric material substrate, the dielectric material substrate being located between the back side of the semiconductor layer and the antenna substrate.

11. The semiconductor die of claim 10, further comprising: An etch stop layer is provided between the dielectric substrate and the semiconductor layer.

12. The semiconductor die of claim 10, wherein: The dielectric material substrate includes a silicon substrate.

13. The semiconductor die of claim 12, wherein: The silicon substrate includes a porous silicon substrate.

14. The semiconductor die of claim 10, wherein: The dielectric material substrate has a dielectric constant between 4 farads per meter (F / m) and 6 F / m.

15. The semiconductor die of claim 10, wherein: The dielectric material substrate has a dielectric constant of less than or equal to 5.0 farads per meter (F / m).

16. The semiconductor die of claim 10, wherein: The dielectric material substrate has a first thickness between 40 and 60 micrometers (μm) between the antenna substrate and the semiconductor layer.

17. The semiconductor die as claimed in claim 1, wherein: The one or more antenna elements are each arranged at a first distance between seventy (70) and eighty (80) micrometers (μm) from the RF circuit.

18. The semiconductor die of claim 1, further comprising: An integrated circuit (IC), the IC including the semiconductor layer and the BEOL interconnect structure; The IC includes a bulk device, and the semiconductor layer includes a bulk semiconductor material layer.

19. The semiconductor die of claim 1, further comprising: An integrated circuit (IC), the IC including a silicon-on-insulator (SOI) device, the SOI device including the semiconductor layer and the BEO interconnect structure; The semiconductor layer includes a buried oxide (BOX) layer adjacent to the front side and a semiconductor substrate adjacent to the back side, such that the BOX layer is located between the front side and the semiconductor substrate.

20. The semiconductor die of claim 1, wherein: The BEOL interconnect structure includes a plurality of metal layers located between the front side and the second side, each of the plurality of metal layers including one or more metal interconnects; as well as Each of the one or more first vias couples an antenna element in one or more antenna elements to one or more metal interconnects in the first metal layer of the plurality of metal layers; as well as The semiconductor die further includes: One or more second vias, each second via coupled to the RF circuit, and each second via coupled to one or more metal interconnects in the first metal layer of the plurality of metal layers.

21. The semiconductor die as claimed in claim 1, wherein: The one or more first vias include one or more first through-silicon vias (TSVs).

22. The semiconductor die of claim 1, integrated into a device selected from the group consisting of: Set-top box; Entertainment unit; navigation equipment; Communication equipment; Fixed-position data unit; Mobile location data unit; Global Positioning System (GPS) device; mobile phone; cellular phone; smartphone; Session Initiation Protocol (SiP) phone; tablet computer; tablet phone; server; computer; portable computer; mobile computing device; wearable computing device; desktop computer; personal digital assistant (PDA); monitor; computer monitor; television; tuner; radio; Satellite radio; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

23. A method for manufacturing a semiconductor die, the method comprising: Forming a semiconductor layer includes: First side; The back side, which is opposite to the first side; and Radio frequency (RF) circuits; A back-end process online (BEOL) interconnect structure is formed, the BEOL interconnect structure being coupled to the RF circuit, the BEOL interconnect structure comprising: Front side; and A second side, opposite to the front side, is coupled to the semiconductor layer; an antenna substrate is formed, the antenna substrate being adjacent to the back side of the semiconductor layer, comprising: Forming one or more antenna layers, wherein a first antenna layer in the one or more antenna layers comprises one or more antenna elements; and One or more first vias are formed, each first via coupling an antenna element in the one or more antenna elements to the BEOL interconnect structure, so as to couple the one or more antenna elements to the RF circuit.

24. The method of claim 23, wherein forming the one or more antenna layers includes forming the first antenna layer, and includes forming a metal layer, the metal layer comprising one or more metal structures, the one or more metal structures comprising the one or more antenna elements in the first antenna layer.

25. The method of claim 24, wherein forming the metal layer includes forming a first redistribution layer (RDL).

26. The method of claim 23, further comprising: A dielectric material substrate is formed, the dielectric material substrate being adjacent to the back side of the semiconductor layer; as well as The formation of the antenna substrate further includes: forming the antenna substrate on the dielectric material substrate.

27. The method of claim 23, further comprising: A dielectric substrate is formed adjacent to the back side of the semiconductor layer; as well as An etch stop layer is formed on the dielectric material substrate; The formation of the antenna substrate further includes: forming the antenna substrate adjacent to the etch stop layer.

28. The method of claim 26, wherein forming the dielectric material substrate further comprises: A silicon substrate is formed adjacent to the back side of the semiconductor layer; as well as The silicon substrate is made porous to form a porous silicon substrate adjacent to the back side of the semiconductor layer.

29. The method of claim 23, wherein forming the BEOL interconnect structure further comprises: A plurality of metal layers are formed between the front side and the second side, each of the plurality of metal layers including one or more metal interconnects; as well as The method further includes forming one or more first vias in the antenna substrate and the BEOL interconnect structure, each first via coupling an antenna element in one or more antenna elements to one or more metal interconnects in the first metal layer of the plurality of metal layers.

30. The method of claim 29, further comprising: One or more second vias are formed, each second via being coupled to the RF circuit, and each second via being coupled to the one or more metal interconnects in the first metal layer of the plurality of metal layers.

31. The method of claim 29, wherein forming the one or more first through holes comprises: One or more first through-silicon vias (TSVs) are formed in the antenna substrate and the BEOL interconnect structure, each first TSV coupling an antenna element in the one or more antenna elements to the one or more metal interconnects in the first metal layer of the plurality of metal layers.

32. The method of claim 26, further comprising: The dielectric material substrate is thinned to a desired first thickness to control the distance between the one or more antenna elements and the RF circuit.

33. The method of claim 26, wherein forming the semiconductor layer further comprises: A semiconductor substrate is formed on the dielectric material substrate, the semiconductor substrate including the back side; as well as A buried oxide (BOX) layer is formed on the semiconductor substrate; in: Forming the BEOL interconnect structure further includes: forming the BEOL interconnect structure adjacent to the BOX layer.

34. The method of claim 26, wherein forming the semiconductor layer further comprises: A silicon layer is formed on the dielectric material substrate, the silicon layer including the first side and the back side; as well as in: Forming the BEOL interconnect structure further includes: forming the BEOL interconnect structure adjacent to the silicon layer.

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