Capacitance detection circuit, capacitance sensor, and electronic device

Abstract

The invention relates to a capacitance detection circuit, a capacitance sensor and electronic equipment. The capacitance detection circuit comprises an induction capacitor which is used for receiving a driving signal and charging and discharging according to the driving signal; the capacitance frequency conversion module is connected with the induction capacitor and is used for at least receiving the driving signal and detecting the capacitance value of the induction capacitor according to the driving signal so as to output a square wave signal; the frequency of the square wave signal is related to the capacitance value of the induction capacitor; the frequency digital conversion module is connected with the capacitance frequency conversion module and is used for receiving a threshold voltage signal and outputting a capacitance detection signal according to the threshold voltage signal and the square wave signal; the amplitude of the capacitance detection signal is related to the frequency of the square wave signal. The capacitance detection circuit can rapidly detect the capacitance change.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of capacitance detection, in particular to a capacitance detection circuit, a capacitance sensor and an electronic device. BACKGROUND

[0002] A capacitance sensor is a conversion device that converts a measured physical quantity into a capacitance change. The capacitance sensor is widely used in industrial and consumer electronic product fields due to its simple structure, stable performance, high sensitivity, long service life and other advantages, such as pressure, displacement, acceleration, thickness, liquid level measurement, etc. Capacitive touch screens or keys are widely used in electronic products due to their good performance and long service life.

[0003] However, the capacitance detection method in the related art often needs to convert the measured physical quantity into a digital signal through an analog to digital converter (ADC) first, and then detect the capacitance change according to the converted digital signal. This detection method has the problem of large delay. SUMMARY

[0004] Therefore, it is necessary to provide a capacitance detection circuit, a capacitance sensor and an electronic device capable of quickly detecting capacitance changes in view of the above technical problems.

[0005] In a first aspect, the present application provides a capacitance detection circuit, which comprises:

[0006] An inductive capacitance is configured to receive a driving signal and perform charging and discharging according to the driving signal.

[0007] A capacitance frequency conversion module is connected to the inductive capacitance and configured to receive at least the driving signal and detect a capacitance value of the inductive capacitance according to the driving signal, so as to output a square wave signal; the frequency of the square wave signal is related to the capacitance value of the inductive capacitance.

[0008] A frequency digital conversion module is connected to the capacitance frequency conversion module and configured to receive a threshold voltage signal and output a capacitance detection signal according to the threshold voltage signal and the square wave signal; the amplitude of the capacitance detection signal is related to the frequency of the square wave signal.

[0009] In one embodiment, the capacitance frequency conversion module comprises:

[0010] A capacitance sensing unit is connected to the inductive capacitance and configured to receive at least the driving signal and detect the capacitance value of the inductive capacitance according to the driving signal, so as to output a capacitance sensing signal; the amplitude of the capacitance sensing signal is positively related to the capacitance value of the inductive capacitance.

[0011] The capacitance frequency conversion unit is connected with the capacitance sensing unit, configured to receive a power signal, and convert the capacitance sensing signal into the square wave signal according to the power signal.

[0012] In one of the embodiments, the capacitance sensing unit comprises:

[0013] The capacitance sensing sub-unit is connected with the sensing capacitance, configured to receive the driving signal, and detect the capacitance value of the sensing capacitance according to the driving signal, so as to output an initial sensing signal; wherein the amplitude of the initial sensing signal is negatively related to the capacitance value of the sensing capacitance.

[0014] The voltage adjustment sub-unit is connected with the capacitance sensing sub-unit, configured to receive a power signal, and differentially process the initial sensing signal according to the power signal, so as to output the capacitance sensing signal; wherein the amplitude of the capacitance sensing signal is negatively related to the amplitude of the initial sensing signal.

[0015] In one of the embodiments, the capacitance frequency conversion unit comprises:

[0016] The first integration sub-unit is connected with the capacitance sensing unit, configured to integrate the capacitance sensing signal, so as to output a first ramp signal; wherein the frequency of the first ramp signal is positively related to the amplitude of the capacitance sensing signal.

[0017] The first trigger sub-unit is connected with the first integration sub-unit and the frequency digital conversion module respectively, configured to receive a power signal, and convert the first ramp signal into the square wave signal according to the power signal; wherein the frequency of the square wave signal is positively related to the frequency of the first ramp signal.

[0018] In one of the embodiments, the first trigger sub-unit is further configured to output the square wave signal as a first level, in the case that the amplitude of the first ramp signal is greater than or equal to a first voltage threshold.

[0019] The first trigger sub-unit is further configured to output the square wave signal as a second level, in the case that the amplitude of the first ramp signal is greater than or equal to a second voltage threshold, or less than the first voltage threshold; wherein the first voltage threshold and the second voltage threshold are respectively related to the power signal, and the amplitude of the first level is greater than the amplitude of the second level.

[0020] In one of the embodiments, the first trigger sub-unit is further configured to reset the first ramp signal, in the case that the amplitude of the first ramp signal is greater than the second voltage threshold, so as to reduce the amplitude of the first ramp signal to the first voltage threshold and start integration again.

[0021] The integral time required for the amplitude of the first ramp signal to rise from a first voltage threshold to a second voltage threshold is positively correlated with the amplitude of the capacitive induction signal.

[0022] In one of the embodiments, the frequency-to-digital conversion module comprises:

[0023] An integral accumulation unit, connected with the capacitive frequency conversion module, is configured to perform integral processing on the square wave signal to output a primary detection signal.

[0024] A reset unit, connected with the integral accumulation unit, is configured to perform reset processing on the primary detection signal according to a preset period.

[0025] A first trigger unit, connected with the integral accumulation unit, is configured to receive a threshold voltage signal and compare the threshold voltage signal with the primary detection signal to output a capacitive detection signal.

[0026] In one of the embodiments, in the case that the primary detection signal is greater than the threshold voltage signal, the capacitive detection signal is a valid level.

[0027] In the case that the primary detection signal is less than or equal to the threshold voltage signal, the capacitive detection signal is an invalid level.

[0028] In one of the embodiments, the circuit further comprises:

[0029] An isolation module, connected with the capacitive frequency conversion module and the frequency-to-digital conversion module respectively, is configured to perform buffer processing on the square wave signal.

[0030] In a second aspect, the application provides a capacitive sensor comprising the capacitive detection circuit according to any one of the embodiments.

[0031] In a third aspect, the application provides an electronic device comprising the capacitive sensor according to the embodiments.

[0032] The capacitive detection circuit, the capacitive sensor and the electronic device, comprising an induction capacitor, a capacitive frequency conversion module and a frequency digital conversion module, when the external physical quantity to be measured changes, the induction capacitor will charge and discharge under the action of the driving signal, thereby causing the change of the capacitance value of the induction capacitor, the capacitive frequency conversion module can detect the change of the capacitance value of the induction capacitor according to the driving signal, and output a square wave signal related to the capacitance value of the induction capacitor, further, the frequency digital conversion module can output a capacitive detection signal related to the frequency of the square wave signal according to the threshold voltage signal and the square wave signal, thereby, the change of the capacitance value of the induction capacitor can be converted into the change of the amplitude of the capacitive detection signal, compared with the related art that the touch signal is transmitted to the DSP or the MCU for signal conversion and judgment, the capacitive detection circuit of the present application can map the capacitive charging and discharging process into a square wave frequency in real time, without discrete steps, realize the continuous change of the signal with time, thereby being capable of quickly detecting the capacitance change. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0034] Figure 1 It is a structural schematic diagram of a touch detection circuit in the related art;

[0035] Figure 2 It is a structural schematic diagram of an analog-to-digital circuit in the related art;

[0036] Figure 3 It is a structural schematic diagram of a capacitive detection circuit in an embodiment of the present application;

[0037] Figure 4 It is a structural schematic diagram of a capacitive detection circuit in another embodiment of the present application;

[0038] Figure 5 It is a structural schematic diagram of a capacitive detection circuit in another embodiment of the present application;

[0039] Figure 6 It is a circuit structural diagram of a capacitive frequency conversion module in an embodiment of the present application;

[0040] Figure 7 It is a structural schematic diagram of a capacitive detection circuit in another embodiment of the present application;

[0041] Figure 8 It is a structural schematic diagram of a capacitive detection circuit in another embodiment of the present application;

[0042] Figure 9 Circuit structure diagram of frequency digital conversion module in one embodiment of the present application;

[0043] Figure 10 Timing diagram of capacitance detection circuit in one embodiment of the present application.

[0044] Explanation of reference signs:

[0045] 10-capacitance frequency conversion module, 11-capacitance sensing unit, 111-capacitance sensing subunit, 112-voltage adjusting subunit, 12-capacitance frequency conversion unit, 121-first integration subunit, 122-first trigger subunit, 20-frequency digital conversion module, 21-integration accumulation unit, 22-reset unit, 23-first trigger unit, 30-isolation module. DETAILED DESCRIPTION

[0046] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein in the specification merely describe the specific embodiments of the present application for the purpose of the description and are not intended to limit the present application.

[0048] It can be understood that the terms "first", "second" and the like used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the other element. For example, without departing from the scope of the present application, the first resistor can be referred to as the second resistor, and similarly, the second resistor can be referred to as the first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0049] It can be understood that "connection" in the following embodiments, if the circuits, modules, units and the like connected to each other have the transmission of electrical signals or data, should be understood as "electrically connected", "communicatively connected" and the like.

[0050] It can be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of the element" means part or all of the element.

[0051] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] As described in the background section, the related art capacitive detection method often needs to convert the measured physical quantity into a digital signal through an analog-to-digital converter (ADC) first, and then detects the capacitive change according to the converted digital signal. Please refer to Figure 1 For example, in a touch capacitive sensor, when a finger touches a touch pad, the inductance of the touch pad changes, and a touch signal is transmitted to a digital signal processor (DSP) or a micro control unit (MCU) to generate an on / off signal. Since the DSP / MCU itself can only process digital signals, the touch signal needs to be converted into ADC data through the ADC in the DSP / MCU. In applications, a binary capacitive charge / discharge switching switch is usually used. Please refer to Figure 2 For example, in a 10-bit ADC, 10 sets of capacitive charge / discharge switching need to be completed in sequence. The conversion process alone requires multiple clock cycles. After the signals of the ten sets are charged and discharged, the ADC data needs to be sent to the DSP / MCU for judgment. After the DSP / MCU judges the ADC data according to the conditions set by the program, it decides whether to output an on / off signal. As can be seen, the detection method in the related art not only causes time delay, but also increases the workload of the DSP / MCU.

[0053] To solve the above technical problems, in one exemplary embodiment, please refer to Figure 1 The application provides a capacitive detection circuit. In the following embodiments, the capacitive detection circuit of the application is taken as a touch capacitive detection circuit for illustration. The capacitive detection circuit of the application comprises an inductive capacitor Cx, a capacitive frequency conversion module 10, and a frequency-to-digital conversion module 20.

[0054] The inductive capacitor Cx is used to receive a driving signal Iref and charge / discharge according to the driving signal Iref.

[0055] The capacitance frequency conversion module 10 is connected with the sensing capacitance Cx, and is configured to receive at least the driving signal Iref, and detect the capacitance value of the sensing capacitance C according to the driving signal Iref, so as to output a square wave signal VFsq_out; the frequency of the square wave signal VFsq_out is related to the capacitance value of the sensing capacitance C.

[0056] The frequency digital conversion module 20 is connected with the capacitance frequency conversion module 10, and is configured to receive the threshold voltage signal Vth, and output a capacitance detection signal Dout according to the threshold voltage signal Vth and the square wave signal VFsq_out; the amplitude of the capacitance detection signal Dout is related to the frequency of the square wave signal VFsq_out.

[0057] In the application, a reference current source can be included in the capacitance detection circuit, and the reference can output the driving signal Iref. By using a constant current source design for the driving signal Iref, the application avoids the shunt effect of parasitic capacitance on the signal in the voltage driving mode, and can enhance the anti-interference capability. Under the action of the driving signal Iref, the capacitance frequency conversion module 10 can generate a sensing voltage according to the capacitance value of the sensing capacitance C, and convert the sensing voltage into a square wave signal VFsq_out. Then, the frequency digital conversion module 20 can periodically integrate the square wave signal VFsq_out, and compare the result of the integration of the square wave signal VFsq_out with the threshold voltage signal Vth, so as to determine the amplitude of the output capacitance detection signal Dout, that is, according to the comparison result of the integrated square wave signal VFsq_out and the threshold voltage signal Vth, the output capacitance detection signal Dout is controlled to be at a high level or a low level.

[0058] It can be understood that when the user performs a touch operation, the size of the sensing capacitance Cx at the corresponding position on the touchpad changes, and then the size of the sensing voltage generated by the capacitance frequency conversion module 10 changes, and further, the frequency of the square wave signal VFsq_out changes, and the integral value of the integrated square wave signal VFsq_out also changes, and then the level state of the capacitance detection signal Dout changes. Therefore, the capacitance value change of the sensing capacitance Cx can be determined according to the level state of the capacitance detection signal Dout. Since all the process signals in the entire capacitance detection circuit, such as the sensing voltage generated by the capacitance frequency conversion module 10 and the square wave signal VFsq_out, are analog signals, the continuous processing of the signals in time can be realized, so as to reduce the time delay of signal transmission, which is beneficial to rapid detection of capacitance change.

[0059] The capacitive detection circuit includes an inductive capacitor, a capacitive frequency conversion module and a frequency digital conversion module. When an external physical quantity to be detected changes, the inductive capacitor charges and discharges under the action of a driving signal, thereby causing a change in the capacitance value of the inductive capacitor. The capacitive frequency conversion module can detect the change in the capacitance value of the inductive capacitor according to the driving signal and output a square wave signal related to the capacitance value of the inductive capacitor. Further, the frequency digital conversion module can output a capacitive detection signal related to the frequency of the square wave signal according to a threshold voltage signal and the square wave signal. Thus, the change in the capacitance value of the inductive capacitor can be converted into a change in the amplitude of the capacitive detection signal. Compared with the related art in which a touch signal is transmitted to a DSP or MCU for signal conversion and judgment, the capacitive detection circuit can map the capacitive charging and discharging process into a change in the frequency of a square wave in real time, without a discrete step, realize continuous change of the signal with time, and thus can quickly detect the change in the capacitance.

[0060] In one exemplary embodiment, referring to Figure 4 The capacitive frequency conversion module 10 includes a capacitive sensing unit 11 and a capacitive frequency conversion unit 12.

[0061] The capacitive sensing unit 11 is connected with the inductive capacitor Cx and is configured to receive at least the driving signal Iref and detect the capacitance value of the inductive capacitor Cx according to the driving signal Iref to output a capacitive sensing signal V2. The amplitude of the capacitive sensing signal V2 is positively correlated with the capacitance value of the inductive capacitor Cx.

[0062] The capacitive frequency conversion unit 12 is connected with the capacitive sensing unit 11 and is configured to receive a power supply signal VDD and convert the capacitive sensing signal V2 into a square wave signal VFsq_out according to the power supply signal VDD.

[0063] In the present application, the capacitive sensing unit 11 can generate a corresponding capacitive sensing signal V2 according to the size of the inductive capacitor under the action of the driving signal Iref. It can be understood that when the capacitance value of the inductive capacitor Cx changes, the amplitude of the capacitive sensing signal V2 generated by the capacitive sensing unit 11 will also change accordingly.

[0064] Further, the capacitive frequency conversion unit 12 can convert the capacitive sensing signal V2 into a square wave signal VFsq_out under the action of the power supply signal VDD. Similarly, in the case where the capacitance value of the inductive capacitor Cx does not change, the frequency of the square wave signal VFsq_out output by the capacitive frequency conversion unit 12 remains constant. When the capacitance value of the inductive capacitor Cx changes, the frequency of the square wave signal VFsq_out output by the capacitive frequency conversion unit 12 will change. Thus, the change in the capacitance value of the inductive capacitor Cx can be converted into a change in the frequency of the square wave signal VFsq_out.

[0065] In this embodiment, firstly, the change of the capacitance value of the sensing capacitor Cx is converted into the change of the capacitance sensing signal V2 by the capacitance sensing unit 11, so as to realize the preliminary mapping of the physical quantity to the electrical signal. Then, the change of the capacitance sensing signal V2 is further converted into the change of the frequency of the square wave signal VFsq_out by the capacitance frequency conversion unit 12, so as to realize the high-precision quantization through the frequency modulation, realize the continuous change of the signal with time, and be beneficial to the rapid detection of the capacitance change.

[0066] In one example embodiment, referring to Figure 5 , the capacitance sensing unit 11 comprises a capacitance sensing sub-unit 111 and a voltage adjusting sub-unit 112.

[0067] The capacitance sensing sub-unit 111 is connected with the sensing capacitor Cx, is used for receiving the driving signal Iref, and detects the capacitance value of the sensing capacitor Cx according to the driving signal Iref, so as to output the initial sensing signal V1; wherein the amplitude of the initial sensing signal Cx is negatively related to the capacitance value of the sensing capacitor Cx.

[0068] The voltage adjusting sub-unit 112 is connected with the capacitance sensing sub-unit 111, is used for receiving the power signal VDD, and differentially processes the initial sensing signal Cx according to the power signal VDD, so as to output the capacitance sensing signal V2; wherein the amplitude of the capacitance sensing signal V2 is negatively related to the amplitude of the initial sensing signal V1.

[0069] In one example, referring to Figure 6 , the capacitance sensing sub-unit 111 can comprise a gain buffer, and the gain buffer comprises an operational amplifier U1, the positive input end of the operational amplifier U1 is connected with the sensing capacitor Cx and the reference current source respectively, and is used for receiving the driving signal Iref. Wherein, when the user does not perform the touch operation, the size of the sensing capacitor Cx on the touch panel remains constant, and the size of the sensing capacitor Cx is CRef, in one period T, the capacitance sensing sub-unit 111 can detect the initial sensing signal V1=(Iref*T) / CRef; when the user performs the touch operation, the size of the sensing capacitor Cx at the corresponding position on the touch panel changes, the size of the sensing capacitor Cx becomes CRef+CTp, and the size of the initial sensing signal V1 also changes, and the size of the initial sensing signal V1 becomes V1=(Iref*T) / (CRef+CTp). Since the capacitance value of the sensing capacitor Cx increases, the amplitude of the initial sensing signal V1 decreases.

[0070] The voltage adjusting sub-unit 112 can include a voltage regulator, which can include an operational amplifier U2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first end of the first resistor R1 is connected with the output end of the capacitance sensing sub-unit 111. The negative input end of the operational amplifier U2 is connected with the second end of the first resistor R1 and the first end of the third resistor R3, respectively. The second end of the third resistor R3 is connected with the output end of the operational amplifier U2. The positive input end of the operational amplifier U2 is connected with the first end of the second resistor R2 and the fourth resistor R4, respectively. The second end of the second resistor R2 is used to receive a power supply signal VDD. The second end of the fourth resistor R4 is grounded. The output end of the operational amplifier U2 is used to output a capacitance sensing signal V2. In an example, R1=R2, R3=R4. The amplitude of the capacitance sensing signal V2 is V2=R3 / R1*(VDD-V1). It can be seen that the amplitude of the capacitance sensing signal V2 is negatively correlated with the amplitude of the initial sensing signal V1, and the amplitude of the capacitance sensing signal V2 is positively correlated with the capacitance value of the sensing capacitance Cx. The polarity inversion design of the present application makes the capacitance sensing signal V2 consistent with the trend of the physical quantity, conforms to the engineering application habit, and is beneficial to subsequent processing.

[0071] In the embodiment, the initial sensing signal V1 related to the capacitance value of the sensing capacitance Cx is detected by the capacitance sensing sub-unit 111, and the initial sensing signal V1 is buffered. The reflection and distortion in the signal transmission process can be reduced. The ground potential difference and electromagnetic coupling between the sensing capacitance Cx and the voltage adjusting sub-unit 112 are cut off by the capacitance sensing sub-unit 111, so that the anti-interference ability of the circuit can be improved. In a touch detection scenario, the parasitic capacitance usually behaves as a common mode signal. The voltage adjusting sub-unit 112 adopts a differential amplification technology. The differential structure can effectively suppress common mode noise. The voltage adjusting sub-unit 112 can track the change of the initial sensing signal V1, and ensure timely detection of the change of the size of the sensing capacitance.

[0072] In an example embodiment, the capacitance frequency conversion unit 12 includes a first integration sub-unit 121 and a first trigger sub-unit 122.

[0073] The first integration sub-unit 121 is connected with the capacitance sensing unit 11, and is used to perform integration processing on the capacitance sensing signal to output a first slope signal Vout. The frequency of the first slope signal Vout is positively correlated with the amplitude of the capacitance sensing signal V2.

[0074] The first trigger sub-unit 122 is connected with the first integration sub-unit 121 and the frequency digital conversion module 20, respectively, and is used to receive a power supply signal VDD, and convert the first slope signal Vout into a square wave signal VFsq_out according to the power supply signal VDD. The frequency of the square wave signal VFsq_out is positively correlated with the frequency of the first slope signal Vout.

[0075] In the embodiment, the square wave signal VFsq_out output by the first trigger subunit 122 is at a first level when the amplitude of the first ramp signal Vout is greater than or equal to a first voltage threshold VUH, and is at a second level when the amplitude of the first ramp signal Vout is greater than or equal to a second voltage threshold VDH or is less than the first voltage threshold VUH; the first voltage threshold VUH and the second voltage threshold VDH are respectively related to the power supply signal VDD, and the amplitude of the first level is greater than the amplitude of the second level.

[0076] The first trigger subunit 122 is further configured to, when the amplitude of the first ramp signal Vout is greater than the second voltage threshold VDH, perform a reset processing on the first ramp signal Vout, so as to reduce the amplitude of the first ramp signal Vout to the first voltage threshold VUH and start the integration again; the integration time required for the amplitude of the first ramp signal Vout to rise from the first voltage threshold VUH to the second voltage threshold VDH is positively correlated with the amplitude of the capacitive induction signal V2.

[0077] In one example, please refer to Figure 6 The first integration subunit 121 includes an operational amplifier U3, a fifth resistor R5, a sixth resistor R6, a first capacitor C1 and a second capacitor C2. The positive input terminal of the operational amplifier U3 is connected with the first terminal of the fifth resistor R5 and the first terminal of the first capacitor C1 respectively, the second terminal of the fifth resistor R5 is configured to receive the capacitive induction signal V2, the second terminal of the first capacitor C1 is grounded, the negative input terminal of the operational amplifier U3 is connected with the first terminal of the sixth resistor R6 and the first terminal of the second capacitor C2 respectively, the second terminal of the sixth resistor R6 is grounded, the second terminal of the second capacitor C2 is connected with the output terminal of the operational amplifier U3, and the output terminal of the operational amplifier U3 is configured to output the first ramp signal Vout. The resistance value of the fifth resistor R5 and the sixth resistor R6 can be the same, and the capacitance value of the first capacitor C1 and the second capacitor C2 can be the same.

[0078] The first trigger subunit 122 can include an operational amplifier U4, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The negative input terminal of the operational amplifier U4 is configured to receive the first ramp signal Vout, the positive input terminal of the operational amplifier U4 is connected to the first end of the seventh resistor R7, the first end of the eighth resistor R8, and the first end of the ninth resistor R9 respectively, the second end of the seventh resistor R7 is configured to receive a power signal VDD, the second end of the eighth resistor R8 is grounded, the second end of the ninth resistor R9 is connected to the output terminal of the operational amplifier U4, and the output terminal of the operational amplifier U4 is configured to output a square wave signal VFsq_out. The rising edge of the square wave signal VFsq_out triggers a voltage, i.e., a first voltage threshold VUH = R8 / [R8+(R7 / / R9)]*VDD, and the falling edge of the square wave signal VFsq_out triggers a voltage, i.e., a second voltage threshold VDH=(R8 / / R9) / [R7+(R8 / / R9)]*VDD. In the case where the resistances of the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9 are the same, VUH=1 / 3*VDD and VDH=2 / 3*VDD.

[0079] It can be understood that the first integral subunit 121 can integrate the capacitive sensing signal V2 to obtain the first ramp signal Vout, and the first trigger subunit 122 can trigger the first integral subunit 121 to output the square wave signal VFsq_out. When the amplitude of the first ramp signal Vout reaches the first voltage threshold VUH, the first trigger subunit 122 is triggered to output a square wave signal VFsq_out with a first level, i.e., a high level. Then, the first integral subunit 121 continues to integrate the capacitive sensing signal V2. When the amplitude of the first ramp signal Vout reaches the second voltage threshold VDH, the first trigger subunit 122 is triggered to output a square wave signal VFsq_out with a second level, i.e., a low level. In order to make the signal output by the first trigger subunit 122 a square wave, the present application designs a feedback adjustment mechanism between the first integral subunit 121 and the first trigger subunit 122: when the amplitude of the first ramp signal Vout reaches the second voltage threshold VDH, the first trigger subunit 122 can control the first integral subunit 121 to perform reverse integration, i.e., control the amplitude of the first ramp signal Vout to decrease from the second voltage threshold VDH to the first voltage threshold VUH; when the amplitude of the first ramp signal Vout reaches the first voltage threshold VUH, control the first integral subunit 121 to perform forward integration, i.e., control the amplitude of the first ramp signal Vout to increase from the first voltage threshold VUH to the second voltage threshold VDH. In this way, the amplitude of the first ramp signal Vout can be clamped between the first voltage threshold VUH and the second voltage threshold VDH, so that the signal output by the first trigger subunit 122 is a square wave.

[0080] In the embodiment, the amplitude of the capacitive sensing signal V2 is positively correlated with the capacitance value of the sensing capacitor Cx. When the amplitude of the capacitive sensing signal V2 is large, the integration time required for the first integral sub-unit 121 to output the first ramp signal Vout from the first voltage threshold VUH to the second voltage threshold VDH is less than the integration time required for the first integral sub-unit 121 to output the first ramp signal Vout from the first voltage threshold VUH to the second voltage threshold VDH when the amplitude of the capacitive sensing signal V2 is small. Similarly, when the amplitude of the capacitive sensing signal V2 is large, the integration time required for the first ramp signal Vout to decrease from the second voltage threshold VDH to the first voltage threshold VUH is less than the integration time required for the first ramp signal Vout to decrease from the second voltage threshold VDH to the first voltage threshold VUH when the amplitude of the capacitive sensing signal V2 is small. Therefore, in the same time period, the frequency of the square wave signal VFsq_out is larger when the amplitude of the capacitive sensing signal V2 is large than when the amplitude of the capacitive sensing signal V2 is small. That is, in the same time period, the frequency of the square wave signal VFsq_out is larger when the capacitance value of the sensing capacitor Cx is large than when the capacitance value of the sensing capacitor Cx is small.

[0081] In the embodiment, the capacitive sensing signal V2 is integrated, the first trigger sub-unit 122 outputs signals at the first level and the second level, and the first integral sub-unit 121 is reset, so that the first trigger sub-unit 122 can be continuously triggered to output signals at the first level and the second level, thereby enabling the first trigger sub-unit 122 to output the square wave signal VFsq_out. In the present application, the closed-loop hardware design of integration-triggering-resetting directly converts the capacitance change into a frequency signal, avoids the quantization loss of traditional ADC conversion, and improves the anti-interference ability and dynamic response speed through hysteresis comparison and automatic reset mechanism, thereby providing a low-delay and low-power core solution for high-precision touch systems.

[0082] In one exemplary embodiment, referring to Figure 8 , the frequency-to-digital conversion module 20 includes an integral accumulation unit 21, a reset unit 22, and a first trigger unit 23.

[0083] The integral accumulation unit 21 is connected to the capacitive frequency conversion module 10 and is configured to perform integral processing on the square wave signal VFsq_out to output a primary detection signal VFTD.

[0084] The reset unit 22 is connected to the integral accumulation unit 21 and is configured to reset the primary detection signal VFTD according to a preset period.

[0085] The first trigger unit 23 is connected with the integral unit 21, and is used for receiving the threshold voltage signal Vth and comparing the threshold voltage signal Vth with the primary detection signal VFTD to output the capacitance detection signal Dout.

[0086] In one example, referring to Figure 9 The integral unit 21 includes an operational amplifier U6, a tenth resistor R10, an eleventh resistor R11, a third capacitor C3 and a fourth capacitor C4. The positive input terminal of the operational amplifier U6 is connected with the first terminal of the tenth resistor R10 and the first terminal of the third capacitor C3 respectively, the second terminal of the tenth resistor R10 is used for receiving the square wave signal VFsq_out, the second terminal of the third capacitor C3 is grounded, the negative input terminal of the operational amplifier U6 is connected with the first terminal of the eleventh resistor R11 and the first terminal of the fourth capacitor C4 respectively, the second terminal of the eleventh resistor R11 is grounded, the second terminal of the fourth capacitor C4 is connected with the output terminal of the operational amplifier U6, and the output terminal of the operational amplifier U6 is used for outputting the primary detection signal VFTD. The resistance values of the tenth resistor R10 and the eleventh resistor R11 can be the same, and the capacitance values of the third capacitor C3 and the fourth capacitor C4 can be the same. The reset unit 22 can include a reset switch Reset, the first terminal of the reset switch Reset is connected with the positive input terminal of the operational amplifier U6, and the second terminal of the reset switch Reset is grounded. The first trigger unit 23 includes an operational amplifier U7, the negative input terminal of the operational amplifier U7 is used for receiving the threshold voltage signal Vth, the positive input terminal of the operational amplifier U7 is used for receiving the primary detection signal VFTD, and the output terminal of the operational amplifier U7 is used for outputting the capacitance detection signal Dout.

[0087] In the embodiment, when the square wave signal VFsq_out is at a high level, the integral unit 21 can integrate the square wave signal VFsq_out, and when the square wave signal VFsq_out is at a low level, the integral unit 21 stops integrating the square wave signal VFsq_out. When the preset period T ends, the reset unit 22 can control the integral value of the integral unit 21, i.e. the primary detection signal VFTD is cleared, so that the integral unit 21 starts to integrate again. In the process of integration of the integral unit 21, the first trigger unit 23 compares the primary detection signal VFTD with the threshold voltage signal Vth in real time, when the amplitude of the primary detection signal VFTD is greater than the threshold voltage signal Vth, the capacitance detection signal is at a valid level; when the primary detection signal VFTD is less than or equal to the threshold voltage signal Vth, the capacitance detection signal is at an invalid level.

[0088] In this embodiment, the integral accumulation unit 21 integrates the square wave signal VFsq_out, which can convert the frequency change into the accumulation of the voltage amplitude. This design is equivalent to low-pass filtering the high-frequency noise, which improves the signal-to-noise ratio of the detection signal. The first trigger unit 23 compares the primary detection signal VFTD obtained by integrating the square wave signal VFsq_out with the threshold voltage signal Vth, and directly outputs a digital signal without complex software algorithm, which further reduces the processing burden of the DSP / MCU.

[0089] In an exemplary embodiment, please continue to refer to Figure 8 and Figure 9 The capacitance detection circuit of the application further comprises an isolation module 30 connected with the capacitance frequency conversion module 10 and the frequency digital conversion module 20, respectively, for buffering the square wave signal VFsq_out.

[0090] The isolation module 30 can include an operational amplifier U5, the positive input terminal of the operational amplifier U5 is used to receive the square wave signal VFsq_out, the negative input terminal of the operational amplifier U5 is connected with the output terminal of the operational amplifier U5, and the output terminal of the operational amplifier U5 is used to output the buffered square wave signal VFsq_out.

[0091] In this embodiment, the square wave signal VFsq_out is buffered by the isolation module 30, which can reduce the reflection and distortion in the signal transmission process, and at the same time, the isolation module 30 cuts off the ground potential difference and electromagnetic coupling between the capacitance frequency conversion module 10 and the frequency digital conversion module 20, which improves the anti-interference ability of the circuit.

[0092] In a detailed embodiment, please refer to Figure 6 , Figure 9 and Figure 10 In the first period T1, the user's finger does not touch the touchpad, and the capacitance value of the sensing capacitor Cx does not change, the size of the sensing capacitor Cx is CRef, at this time V1=(Iref*T) / CRef; the frequency of the square wave signal VFsq_out output by the first trigger subunit 122 is low, the integral accumulation unit 21 integrates the square wave signal VFsq_out, and the amplitude of the primary detection signal VFTD obtained by integrating the square wave signal VFsq_out does not exceed the amplitude of the threshold voltage signal Vth, so the capacitance detection signal Dout remains low. In period T2, the user's finger touches the touchpad, and the capacitance value of the corresponding position of the sensing capacitor Cx changes, Cx=CRef+CTP, at this time V1=(Iref*T) / (CRef+CTP), the frequency of the square wave signal VFsq_out output by the first trigger subunit 122 is relatively higher than that of the square wave signal VFsq_out in period T1, and the integral accumulation unit 21 integrates the square wave signal VFsq_out.

[0093] When the square wave signal VFsq_out is high, the primary detection signal VFTD integrates and accumulates the voltage value, and when the square wave signal VFsq_out is low, the voltage value of the primary detection signal VFTD remains unchanged, waiting for the next square wave signal VFsq_out to be high, and the primary detection signal VFTD continues to accumulate the voltage value. As shown in FIG. 1, the square wave signal VFsq_out has three output waveforms in the period T1, and the voltage value of the primary detection signal VFTD is accumulated three times. When the period T1 ends, the reset switch Reset controls the voltage of the capacitor C3 to be zero, and the accumulation is restarted. In the period T2, the square wave signal VFsq_out has nine output waveforms, and the primary detection signal VFTD is accumulated nine times. When the period T2 ends, the reset switch Reset controls the voltage of the capacitor C3 to be zero, and the accumulation is restarted. Figure 10 As can be seen from FIG. 1, because the number of integrations of the primary detection signal VFTD in the period T1 is small, the amplitude of the primary detection signal VFTD does not exceed the amplitude of the threshold voltage signal Vth in the entire period T1, so the first trigger unit 23 outputs the capacitor detection signal Dout at low level. Because the number of integrations of the primary detection signal VFTD in the period T2 is large, when the amplitude of the primary detection signal VFTD exceeds the amplitude of the threshold voltage signal Vth, the first trigger unit 23 outputs the capacitor detection signal Dout at high level. Figure 10 As can be seen from FIG. 1, because the number of integrations of the primary detection signal VFTD in the period T1 is small, the amplitude of the primary detection signal VFTD does not exceed the amplitude of the threshold voltage signal Vth in the entire period T1, so the first trigger unit 23 outputs the capacitor detection signal Dout at low level. Because the number of integrations of the primary detection signal VFTD in the period T2 is large, when the amplitude of the primary detection signal VFTD exceeds the amplitude of the threshold voltage signal Vth, the first trigger unit 23 outputs the capacitor detection signal Dout at high level.

[0094] In summary, the application realizes signal conversion and judgment through a hardware circuit, avoids the delay of ADC conversion and software algorithm in the traditional scheme, and can improve the response speed by several times. At the same time, due to the combination of differential processing, integration filtering and isolation design, the circuit can still maintain stable performance in a complex electromagnetic environment. In addition, the capacitor detection circuit of the application also reduces the participation of DSP / MCU, reduces the working frequency and operation load of the processor, and is conducive to reducing power consumption.

[0095] In one exemplary embodiment, the application provides a capacitor sensor comprising the capacitor detection circuit in any of the above embodiments.

[0096] In one exemplary embodiment, the application provides an electronic device comprising the capacitor sensor in the above embodiment.

[0097] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0098] Any combination of the technical features in the above embodiments can be made, and for the sake of brevity, not all possible combinations are described above, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0099] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A capacitance detection circuit, characterized by, The circuit comprises: an inductive capacitor configured to receive a driving signal and charge and discharge according to the driving signal; a capacitor frequency conversion module connected to the inductive capacitor and configured to receive at least the driving signal and detect a capacitance value of the inductive capacitor according to the driving signal to output a square wave signal; a frequency of the square wave signal is related to the capacitance value of the inductive capacitor; a frequency digital conversion module connected to the capacitor frequency conversion module and configured to receive a threshold voltage signal and output a capacitance detection signal according to the threshold voltage signal and the square wave signal; an amplitude of the capacitance detection signal is related to the frequency of the square wave signal.

2. The capacitance detection circuit according to claim 1, characterized by The capacitor frequency conversion module comprises: a capacitor induction unit connected to the inductive capacitor and configured to receive at least the driving signal and detect the capacitance value of the inductive capacitor according to the driving signal to output a capacitor induction signal; an amplitude of the capacitor induction signal is positively related to the capacitance value of the inductive capacitor; a capacitor frequency conversion unit connected to the capacitor induction unit and configured to receive a power signal and convert the capacitor induction signal into the square wave signal according to the power signal.

3. The capacitance detection circuit of claim 2, wherein, The capacitor induction unit comprises: a capacitor induction subunit connected to the inductive capacitor and configured to receive the driving signal and detect the capacitance value of the inductive capacitor according to the driving signal to output an initial induction signal; an amplitude of the initial induction signal is negatively related to the capacitance value of the inductive capacitor; a voltage adjustment subunit connected to the capacitor induction subunit and configured to receive a power signal and differentially process the initial induction signal according to the power signal to output the capacitor induction signal; an amplitude of the capacitor induction signal is negatively related to the amplitude of the initial induction signal.

4. The capacitance detection circuit of claim 2, wherein, The capacitor frequency conversion unit comprises: a first integration subunit connected to the capacitor induction unit and configured to integrate the capacitor induction signal to output a first ramp signal; a frequency of the first ramp signal is positively related to the amplitude of the capacitor induction signal; a first trigger subunit connected to the first integration subunit and the frequency digital conversion module respectively and configured to receive the power signal and convert the first ramp signal into the square wave signal according to the power signal; a frequency of the square wave signal is positively related to the frequency of the first ramp signal.

5. The capacitance detection circuit according to claim 4, wherein the first trigger subunit is further configured to output the square wave signal as a first level when the amplitude of the first ramp signal is greater than or equal to a first voltage threshold; the first trigger subunit is further configured to output the square wave signal as a second level when the amplitude of the first ramp signal is greater than or equal to a second voltage threshold or less than the first voltage threshold; the first voltage threshold and the second voltage threshold are respectively related to the power signal, and an amplitude of the first level is greater than an amplitude of the second level. The first trigger subunit is further configured to, in a case where the amplitude of the first ramp signal is greater than the second voltage threshold, perform a reset process on the first ramp signal, so that the amplitude of the first ramp signal is reduced to the first voltage threshold and the integration is started again. The integration time required for the amplitude of the first ramp signal to rise from the first voltage threshold to the second voltage threshold is positively correlated with the amplitude of the capacitive induction signal.

6. The capacitance detection circuit of claim 1, wherein, The frequency-to-digital conversion module comprises: An integration and accumulation unit connected with the capacitive frequency conversion module, configured to perform an integration process on the square wave signal to output a primary detection signal; A reset unit connected with the integration and accumulation unit, configured to perform a reset process on the primary detection signal according to a preset period; A first trigger unit connected with the integration and accumulation unit, configured to receive a threshold voltage signal and compare the threshold voltage signal with the primary detection signal to output a capacitive detection signal.

7. The capacitive detection circuit according to claim 6, wherein, in a case where the primary detection signal is greater than the threshold voltage signal, the capacitive detection signal is a valid level; in a case where the primary detection signal is less than or equal to the threshold voltage signal, the capacitive detection signal is an invalid level.

8. The capacitance detection circuit of claim 1, wherein, The circuit further comprises: An isolation module connected with the capacitive frequency conversion module and the frequency-to-digital conversion module respectively, configured to perform a buffering process on the square wave signal.

9. A capacitive sensor, characterized by The capacitive detection circuit according to any one of claims 1-8.

10. An electronic device, comprising: The capacitive sensor according to claim 9.

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