True random number generator based on volatile memristor and method for preparing memristor

Abstract

This invention belongs to the field of random number generator technology, and relates to a true random number generator based on volatile memristors and a method for fabricating memristors. The method includes an entropy generation unit and a bit extraction unit. The entropy generation unit includes two or more volatile memristors connected in parallel, one end of which is connected to the input voltage, and the other end is connected in series with a load resistor and then grounded. The entropy generation unit exhibits spontaneous bistable switching behavior under high input voltage. The bit extraction unit includes a T flip-flop connected between the load resistor and the parallel volatile memristors, used to sample oscillation signals and generate a usable random bit stream. Its advantages are that it simplifies the circuit structure of the true random number generator, achieves a high random bit generation rate, and achieves extremely high energy efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of random number generators, in particular to a true random number generator based on a volatile memristor and a memristor preparation method. BACKGROUND

[0002] With the wide deployment of Internet of Things devices in edge scenarios, information security has become a core concern in system design. Key generation, as a basic link of secure communication, is highly dependent on the randomness of the entropy source and the output quality, which directly affects the system's ability to resist attacks. In recent years, true random number generators based on physical noise sources have emerged, and their outputs are unpredictable, suitable for high-security scenarios. However, existing true random number generator designs mostly focus on optimizing peripheral circuits, such as eliminating post-processing requirements, reducing the number of logic gates, and using self-clocking architectures, aiming to reduce power consumption and area without changing the core structure. However, this "circuit-centric" optimization approach is gradually approaching the efficiency bottleneck, making it difficult to fundamentally solve the problems of low throughput and high energy consumption. Therefore, it is necessary to explore the potential for performance improvement of true random number generators from the device level. In addition, the performance of true random number generators is highly dependent on the entropy source devices used. Although the commonly used non-volatile memristor has good data retention capability, its output randomness is easily affected by factors such as reference drift and device aging, making it difficult to ensure stability during long-term operation. In true random number generator schemes based on volatile memristors, the high resistance state of the device has a high conductance level, and there is still a large leakage current in the off state, resulting in high static power consumption of the overall circuit, which limits the energy efficiency optimization of the system. SUMMARY

[0003] Technical problems to be solved

[0004] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present application provides a true random number generator based on a volatile memristor and a memristor preparation method, which solves the problem that existing true random number generators rely too much on circuit-level optimization and have large device leakage current, which has gradually approached the efficiency bottleneck, making it difficult to fundamentally solve the problems of low throughput and high energy consumption, limiting the energy efficiency optimization of the system, and unable to support the high energy efficiency and high randomness output requirements of security systems facing edge scenarios.

[0005] Technical solutions

[0006] In order to achieve the above-mentioned purposes, the main technical solutions adopted by the present application include:

[0007] In a first aspect, the present application provides a true random number generator based on a volatile memristor, comprising:

[0008] an entropy generation unit and a bit extraction unit;

[0009] The entropy generation unit comprises two or more parallel-connected volatile memristors, one end of which is connected to an input voltage and the other end of which is connected to a load resistor in series and then to ground; the entropy generation unit exhibits a spontaneous bistable switching behavior under an input high voltage;

[0010] The bit extraction unit comprises a T flip-flop connected between the load resistor and the parallel-connected volatile memristors, for sampling the oscillation signal and generating a usable random bit stream.

[0011] Optionally, in the entropy generation unit, in the case of two parallel-connected volatile memristors, the volatile memristors are initially in a high-resistance state, under an input high voltage, the two volatile memristors cannot be turned on at the same time, the device with a faster opening speed is first switched to a low-resistance state, the voltage drop on the parallel-connected volatile memristors is reduced to below the threshold opening voltage due to the voltage division change, the conduction of the other volatile memristor is inhibited, and when the voltage on the two devices is reduced to below the retention voltage, the previously turned-on device spontaneously returns to the initial state of the high-resistance state.

[0012] Optionally, the bit generation rate reaches hundreds of kb s -1 The energy consumption per bit is controlled in the order of picojoules.

[0013] In a second aspect, the present application provides a preparation method of a memristor, which is used for preparing the volatile memristor in the true random number generator based on a volatile memristor according to any one of the above technical solutions, the volatile memristor is a 1*2 array, and the preparation method comprises the following steps:

[0014] Pt or W inert metal is selected to deposit a bottom electrode by direct current magnetron sputtering;

[0015] A wide-bandgap semiconductor material is selected, and a dielectric layer is deposited in an argon environment by radio frequency magnetron sputtering;

[0016] After completing the definition of a photolithography pattern, an Ag or Cu active metal is deposited by a direct current sputtering method to form a top electrode.

[0017] Optionally, the preparation of the memristor adopts a standard CMOS compatible process.

[0018] Advantages

[0019] The beneficial effects of the present application are: the true random number generator based on the volatile memristor focuses on starting from the device level and the circuit architecture level at the same time, and breaks through the performance bottleneck of the traditional true random number generator in terms of energy consumption and throughput. The volatile memristor with wide bandgap semiconductor material as the dielectric layer has stable volatile switching behavior and sub-picoampere level ultra-low leakage current, and the structure gives the device excellent randomness and high entropy characteristics, which is suitable as the core entropy source of the true random number generator. At the circuit level, the present application designs a core unit composed of two parallel memristors and a load resistor. Under constant voltage driving, the switching speed of the two parallel devices is compared, and the faster one enters the low resistance state, forming a "natural competition" mechanism. The memristor that is turned on first causes the voltage distribution to be redistributed, suppressing the conduction behavior of the other device, thereby determining the high and low states of the output bits. This mechanism avoids the dependence on comparators or decision circuits in traditional designs, significantly simplifies the circuit structure, reduces the logic complexity and power consumption. Under the joint action of device optimization and circuit co-design, the present scheme can realize the energy consumption of a few joules per bit and high throughput output, showing excellent energy efficiency potential and being suitable for high security application requirements in resource limited scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A circuit structure schematic diagram of the true random number generator based on the volatile memristor provided for the embodiments of the present application is shown in the figure.

[0021] Figure 2 A working principle schematic diagram of the true random number generator circuit provided for the embodiments of the present application is shown in the figure.

[0022] Figure 3 A random conduction process schematic diagram of the two parallel memristors in the true random number generator circuit provided for the embodiments of the present application is shown in the figure.

[0023] Figure 4 A scanning electron microscope image of a 1x2 array provided for the embodiments of the present application is shown in the figure.

[0024] Figure 5 An array schematic diagram and a structure schematic diagram of the volatile memristor provided for the embodiments of the present application are shown in the figure.

[0025] Figure 6 An I-V curve of the memristor for 100 cycles provided for the embodiments of the present application is shown in the figure.

[0026] Figure 7 A probability density distribution of the holding voltage and a probability density distribution of the threshold opening voltage schematic diagram provided for the embodiments of the present application is shown in the figure.

[0027] Figure 8The schematic diagram of the change slope of the holding voltage of the device provided by the embodiment of the present application under a 2mV scanning step and the change slope of the threshold opening voltage of the device under a 2mV scanning step is shown in the figure;

[0028] Figure 9 The schematic diagram of the current change and switching speed of the memristor under a 1.5V pulse provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0029] In order to better explain the present application, so as to be understood, the present application is described in detail below by means of specific embodiments in combination with the drawings.

[0030] The true random number generator based on the volatile memristor provided by the embodiment of the present application directly compares the switching speed of the device by adopting the parallel circuit structure of the memristor, and significantly simplifies the circuit structure of the true random number generator. Through the innovation of the device level optimization and the oscillation period extraction mode, a high random bit generation rate can be achieved, which can reach the order of hundreds of kbs -1 The system realizes extremely high energy efficiency performance by using the ultra-low leakage current characteristic of the memristor, and the energy consumption per bit is as low as the order of fJ.

[0031] In order to better understand the above technical solutions, the exemplary embodiments of the present application will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided so that the present application can be more clearly, thoroughly understood, and the scope of the present application can be completely conveyed to those skilled in the art.

[0032] In a first aspect, with reference to Figure 1 The embodiment provides a true random number generator based on a volatile memristor, which comprises:

[0033] An entropy generation unit and a bit extraction unit.

[0034] The entropy generation unit comprises two or more parallel volatile memristors (R1 and R2, and more than two parallel volatile memristors are not shown in the figure), one end of which is connected with an input voltage VDC, and the other end is connected with a load resistor RL in series and then grounded; forming a complete conduction path. The entropy generation unit exhibits a spontaneous bistable switching behavior under a high input voltage;

[0035] The bit extraction unit comprises a T flip-flop connected between the load resistor RL and the parallel volatile memristor, which is used for sampling the oscillation signal and generating a usable random bit stream.

[0036] Optionally, as Figure 2As shown, in the entropy generation unit, in the case of parallel connection of two volatile memristors R1 and R2, the volatile memristor is initially in a high resistance state, under the input of a high voltage, the two volatile memristors will not conduct at the same time, the device with faster opening speed is switched to a low resistance state first, the voltage drop on the parallel volatile memristor caused by the voltage change is below the threshold opening voltage, which inhibits the conduction of the other volatile memristor, and when the voltage on the two devices is below the holding voltage, the previously conducting device spontaneously returns to the initial state of high resistance.

[0037] This parallel comparison mechanism ensures that only one device is randomly selected for switching in each oscillation period, enhancing the randomness of the output. This mechanism not only utilizes the volatility of the device itself during the period, but also utilizes the difference between the two devices, further enhancing the entropy strength of the system output. Figure 3 The random conduction process of the two volatile memristors in one oscillation period is shown, further verifying the randomness of the opening speed between different devices and different periods. This difference is the core source of the entropy source of the circuit. Figure 3 LRS is a low resistance state; HRS is a high resistance state. In addition, this mechanism has good scalability: by increasing the number of parallel devices, the randomness of the system can be further enhanced, and it is suitable for higher entropy demand true random number generator design.

[0038] Optionally, the bit generation rate reaches hundreds of kb s -1 The energy consumption per bit is controlled in the order of fJ.

[0039] The current design has a bit generation rate of hundreds of kb s -1 in the order of microseconds. In terms of energy efficiency, this scheme discards the traditional comparison module and relies on the natural competition mechanism formed by the parallel connection of memristors to realize random bit generation, significantly reducing the circuit complexity and power consumption. In addition, the memristor device has ultra-low leakage current characteristics, combined with the high impedance load resistance in the circuit, so that the system operating energy consumption is at a very low level, the energy consumption per bit is controlled in the order of fJ, and excellent energy efficiency is exhibited.

[0040] In a second aspect, the embodiment provides a preparation method of a memristor, for preparing a volatile memristor in a true random number generator based on a volatile memristor according to any one of the above embodiments, the volatile memristor is a 1x2 array, and the preparation method comprises:

[0041] Pt or W inert metal is selected to deposit the bottom electrode by direct current magnetron sputtering;

[0042] A wide bandgap semiconductor material is selected, and a medium layer is deposited in an argon environment by radio frequency magnetron sputtering;

[0043] After the definition of the lithography pattern, the active metal Ag or Cu is deposited by direct current sputtering method to form the top electrode.

[0044] The memristor is prepared by magnetron sputtering technology to form a three-layer structure, as shown in Figure 4 .

[0045] Optionally, the preparation of the memristor adopts a standard CMOS compatible process.

[0046] Figure 4 and Figure 5 The scanning electron microscope image of the prepared device and its stacking structure are shown. The 1x2 array memristor device used in the present study is prepared by a standard CMOS compatible process. Although the two devices are physically separated, they are arranged close to each other, which facilitates subsequent parallel connection in a true random number generator circuit. The analyzer in the present embodiment is an electrical characteristic parameter analyzer, which is used to accelerate the development of various materials, semiconductor devices and advanced processes, complete process control, reliability analysis and fault analysis, and provide synchronous current-voltage curve test, i.e. I-V curve test.

[0047] A series of electrical tests are performed on the device to verify its stable volatile switching behavior and ultra-low leakage current. The related test results show that the memristor exhibits typical volatile characteristics, has sub-picosecond level ultra-low leakage current, effectively suppresses the crosstalk current path, and ensures extremely low static power consumption, as shown in Figure 6 The randomness of the switching behavior of the device is evaluated, which is essential for high-entropy output. 100 scans are continuously performed on the memristor, Figure 7 showing the statistical distribution and fluctuation of the holding voltage and threshold voltage. It can be seen that the switching behavior of the device is stable while having high randomness, indicating that it has good volatile switching performance. The stability and reliability of the device under long-time operation are ensured. The device also has high-speed switching response, Figure 8 The switching voltage slope of the device is evaluated under direct current voltage scanning conditions; Figure 9 Pulse testing is used to analyze the dynamic switching characteristics of the device, and the turn-on and turn-off speeds are both within 200 ns. Considering that many true random number generator applications rely on the periodic switching behavior of the device as an entropy extraction source, the device combines ultra-low leakage current, high-speed switching capability, good durability and high randomness.

[0048] The true random number generator based on the volatile memristor and the memristor preparation method provided by the embodiment have high randomness and ultra-low leakage current based on the wide-bandgap semiconductor material as the medium layer of the memristor. The core principle of the random number generator circuit is that, compared with the opening speed of the parallel memristor, the faster one spontaneously inverts the state, and the additional comparison circuit is omitted. By means of device-level optimization and circuit innovation, the bit energy of the system is realized in the order of microjoule, and excellent energy efficiency is exhibited.

[0049] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application should also include these modifications and variations.

[0050] Although the embodiments of the present application have been shown and described above, it should be understood that the above-described embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A true random number generator based on a volatile memristor, characterized in that, The application relates to a volatile memristor-based true random number generator. The entropy generation unit comprises two or more parallel volatile memristors, one end of which is connected with an input voltage and the other end of which is connected with a load resistor in series and then grounded; the entropy generation unit exhibits a spontaneous bistable switching behavior under high input voltage. The bit extraction unit comprises a T flip-flop connected between the load resistor and the parallel volatile memristors, which is used for sampling the oscillation signal and generating a usable random bit stream. The spontaneous bistable switching behavior is as follows: in the case of two parallel volatile memristors, the volatile memristors are initially in a high resistance state; under high input voltage, the two volatile memristors cannot be turned on at the same time; the device with a faster opening speed is first switched to a low resistance state; the voltage drop on the parallel volatile memristors is reduced to below the threshold opening voltage due to the voltage drop change, thereby inhibiting the conduction of the other volatile memristor; and when the voltage on the two devices is reduced to below the retention voltage, the previously turned-on device spontaneously returns to the high resistance state initial state. The application further relates to a preparation method of a volatile memristor used for preparing a volatile memristor-based true random number generator as claimed in any one of claims 1-2, the volatile memristor being a 1*2 array, and the preparation method comprising the following steps:

2. A true random number generator based on volatile memristors according to claim 1, characterized in that, Bit generation rates reach hundreds of kbps -1 The energy consumption per bit is controlled in the order of femtojoule.

3. A method of manufacturing a memristor, characterized by, Pt or W inert metal is selected to deposit a bottom electrode through direct-current magnetron sputtering; a wide-band semiconductor material is selected to deposit a dielectric layer in an argon environment through radio frequency magnetron sputtering; after completing the definition of a photoetching pattern, Ag or Cu active metal is deposited to form a top electrode through direct-current sputtering. The preparation of the memristor adopts a standard CMOS compatible process.

4. The method of claim 3, wherein the method further comprises: ​

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