Single-stage fully-differential folding cascode operational amplifier and design method thereof

Abstract

The invention relates to the technical field of analog integrated circuit design, in particular to a single-stage fully-differential folding cascode operational amplifier and a design method thereof, the integrated circuit design is innovated by an artificial intelligence technology, and a mapping relation between design parameters and eight key performance indexes (such as gain and the like) is constructed by a neural network model. In combination with a particle swarm optimization (PSO) algorithm, multi-target optimization is realized, optimal parameters meeting targets such as high gain and the like can be quickly found, the area of a transistor is reduced, and the cost is reduced. The circuit adopts a traditional single-stage fully-differential folding type cascode structure, and the performance is improved through current path folding and the like. The core innovation of the method lies in applying artificial intelligence design, setting a fitness function and constraint conditions to clarify target performance, utilizing PSO efficient search, remarkably improving design efficiency and showing unique advantages.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, specifically to a single-stage fully differential folded cascode operational amplifier and its design method. Background Technology

[0002] The fully differential folded cascode operational amplifier is a high-performance analog integrated circuit that combines fully differential input / output with a folded cascode structure. Its design goals are to achieve high gain, high bandwidth, low noise, and strong anti-interference capabilities, making it widely applicable in high-speed, high-precision analog signal processing scenarios.

[0003] Existing technologies primarily determine the device parameters of single-stage fully differential folded cascode operational amplifiers (OCAs) through experience-based guidance and design rules. Engineers manually calculate the initial dimensions (W / L) and bias current of the input pair, cascode transistors, and load based on classical theoretical formulas. This is constrained by transistor models and design rules (such as minimum channel length) provided by process design kits (PDKs), and parameters are adjusted according to empirical rules. Monte Carlo analysis is also used to assess the impact of process deviations. While this method is mature and reliable, it has significant drawbacks: reliance on manual experience leads to long design cycles and a tendency to get trapped in local optima; process migration requires repeated parameter adjustments, resulting in high costs; and it hinders further breakthroughs in high-performance and low-power designs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a single-stage fully differential folded cascode operational amplifier and its design method, which addresses the shortcomings of the prior art and solves the technical problems of long device design cycle and low performance of the current single-stage fully differential folded cascode operational amplifier.

[0005] The objective of this invention is achieved through the following technical solutions: In a first aspect, the present invention provides a single-stage fully differential folded cascode operational amplifier, comprising: a folded input terminal, a cascode amplification module, a tail current source, and a common-mode feedback circuit; The foldable input terminal is used to connect to the common source cascode amplifier module to fold the differential input signal to the common source cascode amplifier module; The common-source cascode amplifier module is obtained by cascading several common-source transistors and several common-gate transistors; The source of the tail current source is used to connect to the power supply voltage, and the gate is used to connect to the tail current tube. The common-mode feedback circuit is used to connect to the cascode amplifier module, sample the cascode amplifier module, output the common-mode voltage, and adjust the gate voltage of the cascode amplifier module according to the common-mode voltage feedback.

[0006] As a further improvement of the present invention, the folded input terminal includes a first field-effect transistor, a second field-effect transistor, and a folded node; The source of the first field-effect transistor is used to connect to the tail current source, the gate is used to receive the differential input signal, and the drain is connected to the common source and common gate amplifier module through the folded node, and is also connected to the drain of the first tail current transistor. The source of the second effect transistor is used to connect to the tail current source, the gate is used to receive the differential input signal, and the drain is connected to the common source and common gate amplifier module through the folded node, and is also connected to the drain of the second tail current transistor.

[0007] As a further improvement of the present invention, the common-source common-gate amplifier module includes a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a ninth field-effect transistor, and a tenth field-effect transistor. The third field-effect transistor and the fifth field-effect transistor, the third field-effect transistor and the seventh field-effect transistor, and the seventh field-effect transistor and the ninth field-effect transistor respectively form a common source transistor; The third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth field-effect transistors respectively form a common-gate transistor for receiving bias voltage.

[0008] As a further improvement of the present invention, the operational amplifier further includes a bias circuit, which is connected to the common source cascode amplifier module and is used to provide a stable reference current or reference voltage for the common source cascode amplifier module.

[0009] As a further improvement of the present invention, the bias circuit includes several common-source cascode current mirrors.

[0010] Secondly, the present invention provides a design method for a single-stage fully differential folded cascode operational amplifier, comprising: Obtain simulation sample data for an initial single-stage fully differential folded cascode operational amplifier; the simulation sample data includes parameter data for each device in the operational amplifier; the operational amplifier is the single-stage fully differential folded cascode operational amplifier described above. The simulation sample data is input into a pre-trained neural network model to construct a mapping relationship between the performance indicators of each device and the corresponding design parameter data; the fitness function between the performance indicators of each device and the corresponding design parameter data is obtained based on the mapping relationship. Based on the set target performance indicators, the fitness function is searched and updated using the particle swarm optimization algorithm to obtain the optimal fitness. Based on the optimal design parameters corresponding to the optimal fitness, a single-stage fully differential folded cascode operational amplifier is simulated and designed.

[0011] As a further improvement of the present invention, the performance indicators include at least two of the following: voltage gain, unity-gain bandwidth, phase margin, slew rate, common-mode rejection ratio, power supply rejection ratio, current consumption, and noise.

[0012] As a further improvement of the present invention, the parameter data of each device in the operational amplifier includes device size data and physical parameter constraints.

[0013] As a further improvement of the present invention, the training steps of the neural network model are as follows: Acquire several sets of simulation sample data of the operational amplifier to generate a dataset; determine the target performance indicators of the operational amplifier; The simulation sample data in the dataset are normalized. Construct an initial neural network model, train the initial neural network model using the normalized dataset, and output the performance index results corresponding to the target fitting results; The neural network model is validated using untrained data in the dataset. Training stops when the validation result reaches the accuracy threshold; otherwise, the neural network model is updated using the particle swarm optimization algorithm and trained again until the validation result reaches the accuracy threshold.

[0014] As a further improvement of the present invention, the operation steps of the particle swarm optimization algorithm are as follows: Initialize the particle swarm and set the maximum number of iterations. Randomly distribute the particle swarm within the device size constraints corresponding to each device of the operational amplifier. Use the parameter data input to the neural network model as particles. The particle velocity is iteratively updated until the maximum number of iterations is reached, and an optimal fitness is obtained by the convergence of the particle swarm. The particle velocity update process includes: Each particle position is input into the neural network model to predict the corresponding performance index, and the weighted fitness is calculated based on the performance index. The particle's velocity and position are updated based on the computationally weighted fitness, and the local and global optimal solutions are also updated.

[0015] The beneficial effects of this invention are as follows: This invention provides a single-stage fully differential folded cascode operational amplifier, using a PMOS / NMOS differential pair as the input stage, connecting the differential signal to the cascode module through a folded structure. Compared to the sleeve-type cascode structure, the folded design allows the input common-mode voltage to be close to the power rail, avoiding the input range limitation problem caused by stacked transistors in the sleeve type. The cascode amplifier module consists of a cascaded common-source transistor and a common-gate transistor to form a cascode structure; it shields the drain voltage variation of the common-source transistor, reducing the gain drop caused by the λ effect. The tail current source provides a constant bias for the differential pair, ensuring that the cascode transistor operates in the saturation region and avoiding gain drop due to current fluctuations. The common-mode feedback circuit uses continuous-time common-mode feedback, providing a high rejection ratio for common-mode signals and enhancing the system's anti-interference capability.

[0016] This invention also provides a design method for a single-stage fully differential folded cascode operational amplifier (OPA), deeply integrating neural networks (NNs) with an improved particle swarm optimization (PSO) algorithm to propose an intelligent design framework for OPAs. This framework maps circuit design parameters to a performance space (open-loop gain, phase margin, chip area, etc.) by constructing a multi-level feedforward neural network. The target performance of the op-amp is set through a fitness function and constraints, and then the optimal fitness is searched using the particle swarm optimization algorithm. Using this method, we can quickly and accurately obtain the op-amp parameters that meet the design requirements. Compared with manual calculations, this significantly improves design efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a single-stage fully differential folded cascode operational amplifier design based on artificial intelligence algorithms provided in an embodiment of the present invention; Figure 2 A flowchart illustrating a multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms, provided in an embodiment of the present invention. Figure 3 A circuit diagram of a single-stage fully differential folded cascode operational amplifier provided in an embodiment of the present invention; Figure 4 The bias circuit diagram of a single-stage fully differential folded cascode operational amplifier provided in an embodiment of the present invention; Figure 5 A flowchart illustrating the neural network and particle swarm optimization algorithm in the multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms provided in this embodiment of the invention. Figure 6 A schematic diagram illustrating the fitness convergence of the particle swarm optimization algorithm in the multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms provided in this embodiment of the invention. Figure 7 This diagram illustrates the design parameters obtained from the particle swarm optimization algorithm in the multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms provided in this embodiment of the invention. Detailed Implementation

[0019] To make the objectives and technical solutions of this invention clearer and easier to understand, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. The described embodiments are only some embodiments of the present invention, and not all embodiments.

[0021] Example 1 This embodiment discloses a single-stage fully differential folded cascode operational amplifier. The folded input terminal optimizes the current path, and the cascode structure enhances gain and stability. Furthermore, common-mode feedback and bias circuitry ensure robust circuit performance. The components are described in detail below.

[0022] A single-stage fully differential folded cascode operational amplifier includes a folded input terminal, a cascode amplifier module, a tail current source, a common-mode feedback circuit, and a bias circuit. The folded input terminal connects to the cascode amplifier module, folding the differential input signal to the cascode amplifier module. The cascode amplifier module is formed by cascading several common-source transistors and several common-gate transistors. The source of the tail current source is connected to the supply voltage, and its gate is connected to the tail current transistor. The common-mode feedback circuit connects to the cascode amplifier module, samples the cascode amplifier module, outputs a common-mode voltage, and adjusts the gate voltage of the cascode amplifier module based on the common-mode voltage feedback. Specifically, the folded input terminal receives the differential input signal and implements the "folding" of the current path; the cascode amplifier module performs the core signal amplification; the tail current source provides a stable bias current; the common-mode feedback circuit stably outputs the common-mode level; and the bias circuit provides a stable bias voltage / current for the entire circuit.

[0023] The connection relationships between the modules are as follows: Figure 3As shown. The folded input terminal includes: a first field-effect transistor M P1 The second field-effect transistor M P2 And folded nodes; The first field-effect transistor M P1 With the second field-effect transistor M P2 The gate of the transistor is used to receive differential input signals (Vin+, Vin-); the first field-effect transistor M P1 Connect the source and tail current source of the second field-effect transistor; The first field-effect transistor M P1 The drain is connected to the third field-effect transistor M via a folded node. N3 The source is also connected to the drain of the first tail current transistor (the fifth field-effect transistor); The second field-effect transistor M P2 The drain is connected to the fourth field-effect transistor M via a folded node. N4 The source is connected to the drain of the second tail current transistor (sixth field-effect transistor).

[0024] The common-source cascode amplifier module is the core amplification unit of the circuit. Through the cascading of common-source and common-gate transistors, it significantly improves the open-loop gain and output impedance of the circuit. Its structure is as follows: The common-source cascode amplifier module includes a third field-effect transistor M. N3 The fourth field-effect transistor M N4 The fifth field-effect transistor M N5 The sixth field-effect transistor M N6 The seventh field-effect transistor M P7 The eighth field-effect transistor M P8 Ninth Field-Effect Transistor M P9 and the tenth field-effect transistor M P10 ; The third field-effect transistor M N3 and the fifth field-effect transistor M N5 The third field-effect transistor M N3 and the seventh field-effect transistor M P7 The seventh field-effect transistor M P7 and the ninth field-effect transistor M P9 They are respectively configured as common-source transistors; The third field-effect transistor M N3 and the fourth field-effect transistor M N4 The fifth field-effect transistor M N5 and the sixth field-effect transistor M N6 The seventh field-effect transistor M P7 and the eighth field-effect transistor M P8 Ninth Field-Effect Transistor MP9 and the tenth field-effect transistor M P10 They are respectively configured as common-gate transistors to receive bias voltage.

[0025] Specifically, the third field-effect transistor M N3 The source and the fifth field-effect transistor M N5 The drain connection, the third field-effect transistor M N3 The source and the fifth field-effect transistor M N5 Drain connection; Fourth field-effect transistor M N4 The source and the sixth field-effect transistor M N6 The drain connection, the fourth field-effect transistor M N4 The source and the sixth field-effect transistor M N6 Drain connection; The third field-effect transistor M N3 The gate and the fourth field-effect transistor M N4 The gate connection is used to receive the bias voltage (V). B4 ); Fifth field-effect transistor M N5 The source is grounded, and the drain is connected to the third field-effect transistor M. N3 The source connection, the sixth field-effect transistor M N6 The source is grounded, and the drain is connected to the fourth field-effect transistor M. N4 The source connection; Fifth field-effect transistor M N5 The gate and the sixth field-effect transistor M N6 The gate connection is used to receive the bias voltage; The seventh field-effect transistor M P7 The source and the ninth field-effect transistor M P9 The drain connection, the seventh field-effect transistor M P7 The drain and the third field-effect transistor M N3 Drain connection; Eighth field-effect transistor M P8 The source and the tenth field-effect transistor M P10 The drain connection, the eighth field-effect transistor M P8 The drain of the fourth field-effect transistor M N4 Drain connection; The seventh field-effect transistor M P7 The gate and the eighth field-effect transistor M P8 The gate connection is used to receive the bias voltage (V). B3 ); Ninth Field-Effect Transistor M P9 The source of the seventh field-effect transistor MP7 The source connection, the tenth field-effect transistor M P10 The gate of the eighth field-effect transistor M P8 Gate connection; Ninth Field-Effect Transistor M P9 And the source of the tenth field-effect transistor is used to connect to the power supply voltage; Ninth Field-Effect Transistor M P9 The gate and the tenth field-effect transistor M P10 The gate connection is used to receive the bias voltage (V). B2 ).

[0026] Tail current sources include: eleventh field-effect transistor M P11 ; The eleventh field-effect transistor M P11 The source of the eleventh field-effect transistor M is used to connect to the power supply voltage. P11 The drain of the first field-effect transistor M P1 and the second field-effect transistor M P2 The source connection.

[0027] Optionally, the common-mode feedback circuit and the fifth field-effect transistor M N5 And the sixth field-effect transistor M N6 The gate connection is used to determine the gate voltage of the tail current transistor; The operational amplifier also includes a bias circuit, which is connected to the cascode amplifier module and is used to provide a stable reference current or reference voltage for the cascode amplifier module. For example... Figure 4 As shown. The bias circuit includes several common-source cascode current mirrors. Specifically, the bias circuit includes: a twelfth field-effect transistor, a thirteenth field-effect transistor, a fourteenth field-effect transistor, a fifteenth field-effect transistor, a sixteenth field-effect transistor, a seventeenth field-effect transistor, an eighteenth field-effect transistor, a nineteenth field-effect transistor, a twentieth field-effect transistor, a twenty-first field-effect transistor, a twenty-second field-effect transistor, a twenty-third field-effect transistor, and a twenty-fourth field-effect transistor; these 12 transistors together form a common-source cascode current mirror. The sources of the twelfth, thirteenth, fourteenth, fifteenth, and sixteenth field-effect transistors are connected to the supply voltage; the gates of the twelfth, thirteenth, fourteenth, fifteenth, and sixteenth field-effect transistors are interconnected. The drain of the twelfth field-effect transistor is grounded and provides bias current; The gate and drain of the thirteenth field-effect transistor are connected, and the drain and gate of the seventeenth field-effect transistor are connected, generating a bias voltage at this point. The source of the seventeenth field-effect transistor is connected to the drain and gate of the twenty-first field-effect transistor, and the source of the twenty-first field-effect transistor is grounded. The gate and drain of the fourteenth field-effect transistor are connected, and the drain and gate of the eighteenth field-effect transistor are also connected, generating a bias voltage at this point. The source of the eighteenth field-effect transistor is connected to the drain and gate of the twenty-second field-effect transistor, and the source of the twenty-second field-effect transistor is grounded. The gate and drain of the fifteenth field-effect transistor are connected, and the drain and gate of the nineteenth field-effect transistor are also connected, generating a bias voltage at this point. The source of the nineteenth field-effect transistor is connected to the drain and gate of the twenty-third field-effect transistor, and the source of the twenty-third field-effect transistor is grounded. The gate and drain of the sixteenth field-effect transistor are connected, and the drain and gate of the twentieth field-effect transistor are also connected, generating a bias voltage at this point. The source of the twentieth field-effect transistor is connected to the drain and gate of the twenty-fourth field-effect transistor, and the source of the twenty-fourth field-effect transistor is grounded.

[0028] Example 2 This embodiment discloses a design method for a single-stage fully differential folded cascode operational amplifier. For example... Figure 1 , Figure 2 As shown, the steps of this method include: Obtain simulation sample data of the initial single-stage fully differential folded cascode operational amplifier; the simulation sample data includes parameter data of each device in the operational amplifier; the operational amplifier in this embodiment is the single-stage fully differential folded cascode operational amplifier in Embodiment 1; Simulation sample data is input into a pre-trained neural network model to construct a mapping relationship between the performance indicators of each device and the corresponding design parameter data; the fitness function between the performance indicators of each device and the corresponding design parameter data is obtained based on the mapping relationship. Based on the set target performance indicators, the fitness function is searched and updated using the particle swarm optimization algorithm to obtain the optimal fitness. Based on the optimal design parameters corresponding to the optimal fitness, a single-stage fully differential folded cascode operational amplifier is simulated and designed.

[0029] The performance indicators include at least two of the following: voltage gain, unity-gain bandwidth, phase margin, slew rate, common-mode rejection ratio, power supply rejection ratio, current consumption, and noise.

[0030] The parameter data of each component in an operational amplifier includes component size data and physical parameter constraints.

[0031] The training steps for a neural network model are as follows: Acquire several sets of simulation sample data of the operational amplifier to generate a dataset; determine the target performance indicators of the operational amplifier; Normalize the simulation sample data in the dataset; Construct an initial neural network model, train the initial neural network model using the normalized dataset, and output the performance index results corresponding to the target fitting results; The neural network model is validated using untrained data in the dataset. Training stops when the validation result reaches the accuracy threshold; otherwise, the neural network model is updated using the particle swarm optimization algorithm and trained again until the validation result reaches the accuracy threshold.

[0032] The operation steps of the particle swarm optimization algorithm are as follows: Initialize the particle swarm and set the maximum number of iterations. Randomly distribute the particle swarm within the device size constraints corresponding to each device of the operational amplifier. Use the parameter data input to the neural network model as particles. Iteratively update the particle velocity until the maximum number of iterations is reached, and an optimal fitness is obtained by the convergence of the particle swarm. The particle velocity update process includes: Each particle position is input into the neural network model to predict the corresponding performance index, and the weighted fitness is calculated based on the performance index. The particle's velocity and position are updated based on the computationally weighted fitness, and the local and global optimal solutions are also updated.

[0033] The design method of the above-mentioned single-stage fully differential folded cascode operational amplifier will be explained in detail below with specific examples.

[0034] This example addresses the problems of existing technologies, such as long design cycles due to reliance on human experience, susceptibility to local optima, and high costs associated with repeated parameter adjustments during process migration. It proposes a multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms. The method first determines the search range by defining basic design requirements, then performs simulations and uses the simulation data to train a neural network model, establishing a nonlinear mapping relationship between circuit parameters and performance indicators (gain, bandwidth, common-mode rejection ratio, etc.). Subsequently, a particle swarm optimization (PSO) algorithm is employed to globally optimize within the parameter space, dynamically adjusting particle positions to find the optimal solution for the objective function. This method avoids the high computational cost of traditional iterative simulations and significantly improves design efficiency by leveraging the swarm intelligence of PSO to escape local optima.

[0035] The following describes in detail the multi-objective design method of a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms provided in this application, with reference to several embodiments.

[0036] A multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms includes: S100, obtain the basic design requirements of the operational amplifier, and define the range of requirements for device size accordingly; S200 generates a dataset of device dimensions and performance indicators within the required range of device dimensions; S300 utilizes a neural network model to construct a mapping relationship between performance indicators and device size requirements; S400, taking into account various performance indicators, establishes a fitness function between device size and performance indicators; S500 integrates a trained neural network into the PSO algorithm, replacing the traditional fitness calculation function. The particle swarm adjusts its position and velocity based on the prediction results of the neural network, thereby finding the global optimum faster. The S600 is used to perform actual circuit simulations using the optimized parameters to verify the accuracy of the results. If deviations are found, the neural network is retrained or the parameters of the optimization algorithm are adjusted.

[0037] In an embodiment of the present invention, step S100 includes: S110, Define the device size variables to be optimized and their physical constraints; S120 defines target performance indicators (such as gain, bandwidth, power consumption, noise, common-mode rejection ratio, etc.) and sets reasonable quantification standards; The S130 uses Cadence simulation to sample combinations of circuit parameters and generate a dataset containing the correspondence between "input (device size) and output (performance)".

[0038] For example, in this embodiment 1, the dimensions of each transistor in the circuit are defined as shown in Table 1: Table 1 Design parameters of the op-amp

[0039] As shown in Table 1, there are 6 design parameters: transistor M P1 and M P2 Width W1, transistor M P9 and M P10 Width W2, transistor M P7 and M P8 Width W3, transistor M N3 and M N4 Width W4, transistor M N5 and M N6 Width W5, transistor M P11 Width W6.

[0040] The dimensions of each transistor in the circuit are defined as shown in Table 2: Table 2 Design parameters of op-amps

[0041] Eight target performance indicators and their set targets are defined, as shown in Table 3: Table 3. Eight performance indicators of operational amplifiers

[0042] There are a total of 8 performance indicators: voltage gain (A) V Unity-gain bandwidth (UGB), phase margin (PM), slew rate (SR), common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), and power consumption (current consumption, IL). C ) and noise.

[0043] In this embodiment of the application, step S300 includes: S310 normalizes the input (device size) and output (performance indicators) to eliminate dimensional differences and accelerate model convergence; S320, perform network structure design, and determine the number of neurons in the input layer, hidden layer and output layer; S330, perform model training and validation, divide the data into training set, validation set and test set, and calculate the coefficient of determination (R²). 2 The mean squared error (MSE) and the mean squared error reflect the accuracy of the prediction; For example, the MSE and R of 8 neural network models 2 As shown in Table 4: Table 4 shows the fitting performance of the neural network models for each indicator.

[0044] In this embodiment of the application, step S400 includes: For example, the input variables of the multi-objective optimization equation are: W=[ W 1, W 2, W 3, W 4, W 5, W 6] For example, the multi-objective optimization equation is:

[0045] Where, ω 1-9 This represents the weight of each metric. The first term of the fitness function is the sum of the dimensions of all devices, aiming to achieve the performance target while ensuring the minimum area. The variable with the subscript E is the expected value of that metric.

[0046] The preset constraints are expressed as follows: .

[0047] In this embodiment of the application, step S500 includes: S510, Initialization, randomly distributes the particle swarm within the device size constraints; S520: Each particle position is input into a neural network to predict gain, bandwidth, power consumption, and calculate weighted fitness. S530 updates the particle's velocity and position, and updates the local and global optimal solutions; S540, repeat this process repeatedly until the entire population converges to an optimal solution.

[0048] For example, in this operational amplifier, the PSO algorithm is configured as follows: initial group size of 100, maximum number of iterations of 150, and iteration stall limit of 15. Simultaneously, the range of inertia weights is adjusted to balance the algorithm's local and global search capabilities.

[0049] For example, the optimal design parameters are obtained as W=[263.33µm, 88.16µm, 153.55µm, 132.29µm, 47.16µm, 93.42µm], and the corresponding performance index A is... V =60.05dB, PM=75.46°, UGB=96.04MHz, SR=34.75 V / µs, all meeting the design requirements. The total area of ​​the transistors in the operational amplifier core circuit is 1129.005 µm. 2 .

[0050] Figure 5 This diagram illustrates the convergence of the particle swarm optimization algorithm in the multi-objective design method for a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithms provided in this application embodiment.

[0051] Figure 6 A schematic diagram of the design parameters obtained by the particle swarm optimization algorithm in the multi-objective design method of a single-stage fully differential folded cascode operational amplifier based on artificial intelligence algorithm provided in the embodiments of this application.

[0052] For example, the optimized parameters were used to perform actual circuit simulation to verify the accuracy of the results. The final simulation verification and comparison results with the intelligent algorithm are shown in Table 5. Table 5 Comparison of Cadence simulation verification results

[0053] Analyzing the simulation results from Cadence, we found that A VThe four indicators, PM, UGB, and SR, exceeded the design targets by 8.55%, 23.43%, 94.96%, and 132.07%, respectively. Furthermore, CMRR and PSRR are relatively high within the cutoff frequency, indicating good suppression of common-mode signals and power supply noise; flicker noise is more significant at lower frequencies; and noise is reduced to below 20nV / √Hz after the cutoff frequency.

Claims

1. A single-stage fully differential folded cascode operational amplifier, characterized in that, include: Folded input terminal, common source cascode amplifier module, tail current source, common mode feedback circuit; The foldable input terminal is used to connect to the common source cascode amplifier module to fold the differential input signal to the common source cascode amplifier module; The common-source, common-gate amplifier module is obtained by cascading several common-source transistors and several common-gate transistors; The source of the tail current source is used to connect to the power supply voltage, and the gate is used to connect to the tail current tube. The common-mode feedback circuit is used to connect to the cascode amplifier module, sample the cascode amplifier module, output the common-mode voltage, and adjust the gate voltage of the cascode amplifier module according to the common-mode voltage feedback.

2. The single-stage fully differential folded cascode operational amplifier according to claim 1, characterized in that, The folded input terminal includes a first field-effect transistor, a second field-effect transistor, and a folded node; The source of the first field-effect transistor is used to connect to the tail current source, the gate is used to receive the differential input signal, and the drain is connected to the common source and common gate amplifier module through the folded node, and is also connected to the drain of the first tail current transistor. The source of the second effect transistor is used to connect to the tail current source, the gate is used to receive the differential input signal, and the drain is connected to the common source and common gate amplifier module through the folded node, and is also connected to the drain of the second tail current transistor.

3. The single-stage fully differential folded cascode operational amplifier according to claim 1, characterized in that, The common-source cascode amplifier module includes a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a ninth field-effect transistor, and a tenth field-effect transistor; The third field-effect transistor and the fifth field-effect transistor, the third field-effect transistor and the seventh field-effect transistor, and the seventh field-effect transistor and the ninth field-effect transistor respectively form a common source transistor; The third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth field-effect transistors respectively form a common-gate transistor for receiving bias voltage.

4. The single-stage fully differential folded cascode operational amplifier according to claim 3, characterized in that, The operational amplifier also includes a bias circuit, which is connected to the cascode amplifier module and is used to provide a stable reference current or reference voltage for the cascode amplifier module.

5. The single-stage fully differential folded cascode operational amplifier according to claim 4, characterized in that, The bias circuit includes several common-source cascode current mirrors.

6. A design method for a single-stage fully differential folded cascode operational amplifier, characterized in that, include: Obtain simulation sample data of an initial single-stage fully differential folded cascode operational amplifier; the simulation sample data includes parameter data of each device in the operational amplifier; the operational amplifier is the single-stage fully differential folded cascode operational amplifier as described in any one of claims 1 to 5; The simulation sample data is input into a pre-trained neural network model to construct a mapping relationship between the performance indicators of each device and the corresponding design parameter data; the fitness function between the performance indicators of each device and the corresponding design parameter data is obtained based on the mapping relationship. Based on the set target performance indicators, the fitness function is searched and updated using the particle swarm optimization algorithm to obtain the optimal fitness. Based on the optimal design parameters corresponding to the optimal fitness, a single-stage fully differential folded cascode operational amplifier is simulated and designed.

7. The design method of the single-stage fully differential folded cascode operational amplifier according to claim 6, characterized in that, The performance metrics include at least two of the following: voltage gain, unity-gain bandwidth, phase margin, slew rate, common-mode rejection ratio, power supply rejection ratio, current consumption, and noise.

8. The design method of the single-stage fully differential folded cascode operational amplifier according to claim 6, characterized in that, The parameter data of each component in the operational amplifier includes component size data and physical parameter constraints.

9. The design method of the single-stage fully differential folded cascode operational amplifier according to claim 6, characterized in that, The training steps for the neural network model are as follows: Acquire several sets of simulation sample data of the operational amplifier to generate a dataset; determine the target performance indicators of the operational amplifier; The simulation sample data in the dataset are normalized. Construct an initial neural network model, train the initial neural network model using the normalized dataset, and output the performance index results corresponding to the target fitting results; The neural network model is validated using untrained data in the dataset. Training stops when the validation result reaches the accuracy threshold; otherwise, the neural network model is updated using the particle swarm optimization algorithm and trained again until the validation result reaches the accuracy threshold.

10. The design method of the single-stage fully differential folded cascode operational amplifier according to claim 9, characterized in that, The operation steps of the particle swarm optimization algorithm are as follows: Initialize the particle swarm and set the maximum number of iterations. Randomly distribute the particle swarm within the device size constraints corresponding to each device of the operational amplifier. Use the parameter data input to the neural network model as particles. The particle velocity is iteratively updated until the maximum number of iterations is reached, and an optimal fitness is obtained by the convergence of the particle swarm. The particle velocity update process includes: Each particle position is input into the neural network model to predict the corresponding performance index, and the weighted fitness is calculated based on the performance index. The particle's velocity and position are updated based on the computationally weighted fitness, and the local and global optimal solutions are also updated.

Images