Transmission system, tracker circuit, and amplification method

Abstract

A transmission system (7) is provided with an RFIC (4) configured so as to generate a first high-frequency signal, a power amplifier (2) configured so as to amplify the first high-frequency signal, and a tracker circuit (1) configured so as to selectively supply at least one of a plurality of discrete voltages to the power amplifier (2). The tracker circuit (1) is configured to receive the first high-frequency signal generated by the RFIC (4) and to select at least one voltage from a plurality of discrete voltages.

Description

Technical Field

[0001] This invention relates to a transmission system, a tracker circuit, and an amplification method. Background Technology

[0002] Patent Document 1 discloses Average Power Tracking (APT), which improves power efficiency by controlling the power amplifier's supply voltage based on the average output power. Patent Document 2 discloses Digital Envelope Tracking (D-ET), which further improves power-added efficiency.

[0003] Patent Document 1: US Patent No. 9041464

[0004] Patent Document 2: US Patent No. 8,829,993

[0005] However, in the transmission system disclosed in Patent Document 2, a circuit for generating control signals for voltage selection needs to be set up in the RFIC (Radio Frequency Integrated Circuit), which is difficult to implement in the RFIC for APT disclosed in Patent Document 1. Summary of the Invention

[0006] Therefore, the present invention provides a transmission system, tracker circuit, and amplification method for D-ET that can be implemented through a simple RFIC.

[0007] A transmission system according to one aspect of the present invention includes: a signal processing circuit configured to generate a first high-frequency signal; a first power amplifier configured to amplify the first high-frequency signal; and a tracker circuit configured to selectively supply at least one of a plurality of discrete voltages to the first power amplifier, the tracker circuit being configured to receive the first high-frequency signal generated by the signal processing circuit and select at least one voltage from the plurality of discrete voltages.

[0008] One aspect of the tracker circuit of the present invention includes: a voltage generation circuit configured to generate a plurality of discrete voltages; a power modulation circuit configured to selectively output at least one of the plurality of discrete voltages to a power amplifier; a first external connection terminal for inputting a first control signal based on a serial data transmission standard; and a second external connection terminal for inputting a high-frequency signal amplified by the power amplifier, wherein the voltage generation circuit is controlled based on the first control signal and the power modulation circuit is controlled based on the high-frequency signal.

[0009] One aspect of the present invention provides an amplification method for generating a high-frequency signal by generating multiple discrete voltages, detecting the envelope of the generated high-frequency signal, selecting at least one voltage from the multiple discrete voltages based on the detected envelope, and using the selected at least one voltage to amplify the high-frequency signal.

[0010] According to the present invention, D-ET can be implemented through a simple RFIC. Attached Figure Description

[0011] Figure 1A This is a graph showing an example of the power supply voltage shift in APT mode.

[0012] Figure 1B This is a graph showing an example of the shift in power supply voltage under A-ET (Analog Envelope Tracking) mode.

[0013] Figure 1C This is a graph illustrating an example of the shift in power supply voltage under D-ET mode.

[0014] Figure 2 This is a circuit diagram of the communication device according to Embodiment 1.

[0015] Figure 3 This is a circuit structure diagram of the pre-regulator circuit, switched capacitor circuit, and power modulation circuit in Implementation Method 1.

[0016] Figure 4 This is a circuit structure diagram of the envelope detection circuit, control circuit, and digital control circuit of Implementation Method 1.

[0017] Figure 5 This is a flowchart illustrating the scaling-up method of Implementation Method 1.

[0018] Figure 6 This is a component configuration diagram of the communication device according to Embodiment 1.

[0019] Figure 7 This is a circuit diagram of the communication device according to Embodiment 2.

[0020] Figure 8 This is a component configuration diagram of the communication device according to Embodiment 2. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments described below are all general or specific examples. The numerical values, shapes, materials, constituent elements, arrangements of constituent elements, and connection methods shown in the following embodiments are examples and do not limit the present invention.

[0022] Furthermore, the figures are schematic diagrams that have been appropriately emphasized, omitted, or proportionally adjusted for the purpose of illustrating the invention, and are not necessarily strictly illustrative, differing from actual shapes, positional relationships, and proportions. In the figures, substantially identical structures are sometimes given the same reference numerals, and repetitive descriptions are omitted or simplified.

[0023] In the following figures, the x-axis and y-axis are mutually orthogonal axes on a plane parallel to the main surface of the mother substrate. Specifically, when the mother substrate has a rectangular shape in a top view, the x-axis is parallel to the first side of the mother substrate, and the y-axis is parallel to the second side of the mother substrate that is orthogonal to the first side. Additionally, the z-axis is an axis perpendicular to the main surface of the mother substrate, with its positive direction representing the upward direction and its negative direction representing the downward direction.

[0024] In the following description, "connection" includes not only direct connections via connection terminals and / or wiring conductors, but also connections via other circuit elements. "Direct connection" refers to a direct connection via connection terminals and / or wiring conductors without the use of other circuit elements. "C connected between A and B" means that one end of C is connected to A, and the other end of C is connected to B; it means that C is connected in series in the path connecting A and B. "Path connecting A and B" refers to a conductor-based path that electrically connects A and B.

[0025] In the following explanation, "terminal" refers to the point where the conductor within an element ends. Furthermore, when the resistance of the conductors between elements is sufficiently low, a terminal can be interpreted not only as a single point, but also as any point on the conductor between elements or the entire conductor.

[0026] In addition, statements such as "parallel" and "perpendicular" that indicate the relationship between elements, and statements such as "rectangle" that indicate the shape of elements, and numerical ranges that do not only indicate a strict meaning, also include substantially equivalent ranges, such as an error of a few percent.

[0027] First, as a technique for efficiently amplifying high-frequency signals, a tracking mode is explained, which involves dynamically adjusting the power supply voltage supplied to the power amplifier based on the elapsed high-frequency signal. A tracking mode refers to a mode in which the power supply voltage applied to the power amplifier circuit is dynamically adjusted. There are several types of tracking modes; however, here, we will refer to... Figures 1A to 1C This section explains the APT, A-ET, and D-ET modes. Figures 1A to 1C In the diagram, the horizontal axis represents time, and the vertical axis represents voltage. Additionally, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation signal.

[0028] Figure 1AThis is a graph illustrating an example of power supply voltage shifts in APT mode. APT mode refers to a mode where the power supply voltage varies into multiple discrete voltage levels per frame, based on average power.

[0029] A frame is a unit that constitutes a high-frequency signal (modulated wave). For example, in 5G NR (5th Generation New Radio) and LTE (Long Term Evolution), a frame contains ten subframes, each subframe contains multiple time slots, and each time slot consists of multiple symbols. The subframe length is 1ms, and the frame length is 10ms.

[0030] Furthermore, the mode that varies the voltage level in units of one frame or larger based on the average power is called the APT mode, which is distinguished from the mode that varies the voltage level in units smaller than one frame (e.g., subframes, time slots, or symbol units).

[0031] Figure 1B This is a graph illustrating an example of power supply voltage shifts in A-ET mode. A-ET mode refers to a mode in which the power supply voltage continuously varies based on the envelope signal. In A-ET mode, the power supply voltage tracks the envelope of the modulated signal.

[0032] The envelope signal is the signal that represents the envelope of the modulated signal. The envelope value is, for example, derived from (I... 2 +Q 2 The square root of (I, Q) represents the constellation point. Here, (I, Q) represents the point on the constellation diagram that represents the digitally modulated signal. For example, (I, Q) is determined by the BBIC (Baseband Integrated Circuit) based on the transmitted information.

[0033] Figure 1C This is a graph illustrating an example of power supply voltage shifts in D-ET mode. D-ET mode refers to a mode where the power supply voltage varies into multiple discrete voltage levels within a frame, based on the envelope signal. In D-ET mode, the power supply voltage tracks the envelope of the modulated signal. In D-ET, the power supply voltage varies at time intervals shorter than APT.

[0034] (Implementation Method 1)

[0035] The following describes Embodiment 1. The communication device 6 of this embodiment can be used to provide wireless connectivity. For example, the communication device 6 can be installed in a user equipment (UE) within a cellular network (also called a mobile network) such as a mobile phone, smartphone, tablet computer, or wearable device. In other examples, by installing the communication device 6, wireless connectivity can be provided to IoT (Internet of Things) sensor devices, medical / healthcare devices, vehicles, unmanned aerial vehicles (UAVs), and automated guided vehicles (AGVs). In other examples, by installing the communication device 6, wireless connectivity can also be provided at wireless access points or wireless hotspots.

[0036] [1.1 Circuit structure of communication device 6]

[0037] Reference Figure 2 The circuit structure of the communication device 6 in this embodiment will be described. Figure 2 This is a circuit diagram of the communication device 6 in this embodiment.

[0038] also, Figure 2 The circuit structure shown is illustrative; the communication device 6 can be installed using a variety of circuit mounting methods and any of the circuit technologies employed. Therefore, the following description of the communication device 6 should not be interpreted in a restrictive manner.

[0039] The communication device 6 of this embodiment includes a transmission system 7 comprising a tracker circuit 1, a power amplifier 2, a DC power supply 3, and an RFIC 4, and an antenna 5.

[0040] Tracker circuit 1 can selectively supply at least one of a plurality of discrete voltages to power amplifier 2. In this case, tracker circuit 1 can select at least one voltage from the plurality of discrete voltages by receiving a high-frequency signal generated by RFIC4. Therefore, tracker circuit 1 can apply D-ET mode to power amplifier 2. Alternatively, tracker circuit 1 can also apply APT mode to power amplifier 2. The circuit structure of tracker circuit 1 will be described later.

[0041] Power amplifier 2, an example of a first power amplifier, is connected between RFIC 4 and antenna 5. Furthermore, power amplifier 2 is connected to tracker circuit 1. Power amplifier 2 is capable of amplifying high-frequency signals supplied from RFIC 4 using at least one of a plurality of discrete voltages selectively supplied from tracker circuit 1.

[0042] The DC power supply 3 can supply DC voltage to the tracker circuit 1. For example, a rechargeable battery can be used as the DC power supply 3, but it is not limited to this. Furthermore, the DC power supply 3 may not be included in the transmitting system 7 or the communication device 6.

[0043] RFIC4 is an example of a signal processing circuit configured to generate a high-frequency signal (an example of a first high-frequency signal). For example, RFIC4 can generate a high-frequency signal by receiving a digital IQ signal from a BBIC (not shown) and performing digital-to-analog conversion, quadrature modulation, and up-conversion on the digital IQ signal. Furthermore, RFIC4 can also generate digital control signals for controlling tracker circuit 1. Additionally, the functions of the control unit of RFIC4 can be partially or entirely installed externally (e.g., on tracker circuit 1).

[0044] Antenna 5 can transmit high-frequency signals amplified by power amplifier 2 to the outside. Alternatively, antenna 5 may not be included in communication device 6. Furthermore, communication device 6 may also include more than one antenna in addition to antenna 5.

[0045] also, Figure 2 The circuit structure of the communication device 6 shown is illustrative and is not limited thereto. For example, the communication device 6 may also include a baseband signal processing circuit that processes signals using a frequency band lower than that of high-frequency signals.

[0046] [1.2 Circuit structure of tracker circuit 1]

[0047] Next, refer to Figures 2-4 The circuit structure of tracker circuit 1 is described. Figure 3 This is a circuit diagram of the pre-regulator circuit 10, the switched capacitor circuit 20, and the power modulation circuit 30 in this embodiment. Figure 4 This is a circuit structure diagram of the envelope detection circuit 40, the switch control circuit 50, and the digital control circuit 60 in this embodiment.

[0048] also, Figures 2-4 The circuit structure shown below is an example. The tracker circuit 1, pre-regulator circuit 10, switched capacitor circuit 20, power modulation circuit 30, envelope detector circuit 40, switch control circuit 50, and digital control circuit 60 can be installed using a variety of circuit mounting methods and technologies. Therefore, the descriptions of the tracker circuit 1, pre-regulator circuit 10, switched capacitor circuit 20, power modulation circuit 30, envelope detector circuit 40, switch control circuit 50, and digital control circuit 60 provided below should not be interpreted in a restrictive manner.

[0049] The tracker circuit 1 includes a voltage generation circuit 25 comprising a pre-regulator circuit 10 and a switched capacitor circuit 20, a power modulation circuit 30, an envelope detector circuit 40, a switch control circuit 50, a digital control circuit 60, and external connection terminals 101 to 103.

[0050] The pre-regulator circuit 10 can also be referred to as a magnetic regulator or a DC (Direct Current) / DC converter. In this embodiment, the pre-regulator circuit 10 is a single-input single-output buck-boost converter capable of converting the input voltage (Vbat) from the DC power supply 3 into an output voltage (regulation voltage). Furthermore, the pre-regulator circuit 10 can also be a buck converter or a boost converter. The pre-regulator circuit 10 can, for example, vary the output voltage based on a digital control signal from RFIC4. Figure 3 The circuit structure of the pre-regulator circuit 10 will be described later.

[0051] The switched capacitor circuit 20 can generate multiple discrete voltages based on the adjustment voltage supplied from the pre-regulator circuit 10. Figure 3 The circuit structure of the switched capacitor circuit 20 will be described later.

[0052] Furthermore, the voltage generation circuit 25 may not include the pre-regulator circuit 10 and / or the switched capacitor circuit 20. For example, the pre-regulator circuit 10 may be configured outside the voltage generation circuit 25, or even outside the tracker circuit 1. Alternatively, the voltage generation circuit 25 may not include the switched capacitor circuit 20, but may include multiple pre-regulator circuits 10.

[0053] The power modulation circuit 30 is capable of selectively outputting at least one of a plurality of discrete voltages generated by the switched capacitor circuit 20 to the power amplifier 2. In other words, the power modulation circuit 30 is capable of selecting at least one voltage from a plurality of discrete voltages and supplying the selected voltage to the power amplifier 2. Figure 3 The circuit structure of the power modulation circuit 30 will be described later.

[0054] The envelope detection circuit 40 can accept the high-frequency signal generated by RFIC4 and detect the envelope of the high-frequency signal. Using... Figure 4 The circuit structure of the envelope detector circuit 40 will be described later.

[0055] The switch control circuit 50 is capable of generating control signals CS31 to CS33 (an example of a second control signal) for selecting at least one voltage from a plurality of discrete voltages based on the envelope detected by the envelope detector circuit 40. In other words, the switch control circuit 50 is capable of controlling the power modulation circuit 30 based on a high-frequency signal from the RFIC4. In other words, the power modulation circuit 30 is not controlled based on a digital control signal from the RFIC4. Figure 4 The circuit structure of the switch control circuit 50 will be described later.

[0056] The digital control circuit 60 is capable of controlling the pre-regulator circuit 10 and the switched capacitor circuit 20 based on digital control signals (an example of the first control signal) from RFIC4. Specifically, the digital control circuit 60 is capable of generating and outputting control signals for controlling the switches included in the pre-regulator circuit 10 and the switched capacitor circuit 20. Figure 4 The digital control circuit 60 will be described later. Alternatively, the digital control circuit 60 may not be included in the tracker circuit 1.

[0057] External connection terminal 101 is an example of a first external connection terminal, which receives a control signal (first control signal) based on a serial data transmission standard. External connection terminal 101 is externally connected to RFIC4 and internally connected to digital control circuit 60. The control signal based on the serial data transmission standard can be, for example, a source-synchronous control signal or a clock-embedded control signal, but is not limited to these control signals.

[0058] External connection terminal 102 is an example of a second external connection terminal, receiving a high-frequency signal amplified by power amplifier 2. External connection terminal 102 is externally connected to RFIC 4 and internally connected to envelope detection circuit 40.

[0059] External connection terminal 103 is an output terminal used to supply power voltage to power amplifier 2. External connection terminal 103 is externally connected to power amplifier 2 and internally connected to power modulation circuit 30.

[0060] [1.2.1 Circuit structure of pre-regulator circuit 10]

[0061] Next, refer to Figure 3 The circuit structure of the pre-regulator circuit 10 included in the tracker circuit 1 will be described.

[0062] The pre-regulator circuit 10 includes an input terminal T11, an output terminal T12, switches S11 to S14, a power inductor L11, and a capacitor C11.

[0063] Input terminal T11 is used to receive DC voltage (Vbat) from DC power supply 3. Input terminal T11 is externally connected to DC power supply 3 and internally connected to switch S11.

[0064] Output terminal T12 is used to supply an adjustment voltage to the switched capacitor circuit 20. Output terminal T12 is externally connected to input terminal T21 of the switched capacitor circuit 20 and internally connected to switch S13.

[0065] Power inductor L11 is used for boosting and bucking DC voltage (Vbat). One end of power inductor L11 is connected to switches S11 and S12, and the other end of power inductor L11 is connected to switches S13 and S14.

[0066] Switch S11 is connected between input terminal T11 and one end of power inductor L11. In this connection structure, switch S11 can switch the connection or disconnection between input terminal T11 and one end of power inductor L11 by switching it on and off.

[0067] Switch S12 is connected between one end of power inductor L11 and ground. In this connection structure, switch S12 can switch between the connection and non-connection of one end of power inductor L11 and ground by switching it on and off.

[0068] Switch S13 is connected between the other end of power inductor L11 and output terminal T12. In this connection structure, switch S13 can switch the connection or disconnection between the other end of power inductor L11 and output terminal T12 by switching it on and off.

[0069] Switch S14 is connected between the other end of the power inductor L11 and the ground wire. In this connection structure, switch S14 can switch the connection or disconnection between the other end of the power inductor L11 and the ground wire by switching it on and off.

[0070] Capacitor C11 is connected between the path between switch S13 and output terminal T12 and the ground wire. Specifically, one of the two electrodes of capacitor C11 is connected to switch S13 and output terminal T12, and the other of the two electrodes of capacitor C11 is connected to the ground wire.

[0071] also, Figure 3 The structure of the pre-regulator circuit 10 shown is an example and is not limited thereto. For example, a portion of switches S11 to S14 may be replaced with diodes. Alternatively, a portion or all of the pre-regulator circuit 10 may not be included in the tracker circuit 1.

[0072] [1.2.2 Circuit structure of switched capacitor circuit 20]

[0073] Next, refer to Figure 3 The circuit structure of the switched capacitor circuit 20 included in the tracker circuit 1 is described.

[0074] The switched capacitor circuit 20 has a ladder-shaped circuit structure. Specifically, the switched capacitor circuit 20 includes capacitors C21 to C27, switches S21 to S2C, input terminal T21, and output terminals T22 to T24. Energy and charge are input from the pre-regulator circuit 10 to node N3 via input terminal T21, and are led out from nodes N1 to N3 to power modulation circuit 30 via output terminals T22 to T24.

[0075] Input terminal T21 is used to receive the adjusted voltage from the pre-regulator circuit 10. Input terminal T21 is externally connected to the pre-regulator circuit 10 and internally connected to node N3.

[0076] Output terminal T22 is used to supply voltage (V1) from a plurality of discrete voltages to the power modulation circuit 30. Output terminal T22 is externally connected to the power modulation circuit 30 and internally connected to node N1.

[0077] Output terminal T23 is used to supply voltage (V2) from a plurality of discrete voltages to the power modulation circuit 30. Output terminal T23 is externally connected to the power modulation circuit 30 and internally connected to node N2.

[0078] Output terminal T24 is used to supply voltage (V3) from a plurality of discrete voltages to the power modulation circuit 30. Output terminal T24 is externally connected to the power modulation circuit 30 and internally connected to node N3. Alternatively, output terminal T24 can also be integrated with input terminal T21.

[0079] Capacitors C21 to C24 are flying capacitors (also sometimes called transfer capacitors) used to boost and / or buck the adjustment voltage (V1) supplied from the pre-regulator circuit 10. More specifically, capacitors C21 to C24 allow charge to move between capacitors C21 to C24 and nodes N1 to N3 and the ground wire, maintaining V1 to V3 at the three nodes N1 to N3 such that (V3 - V2):(V2 - V1):(V1 - VG) = 1:1:1 and V3 > V2 > V1 > VG. Here, VG represents the ground potential.

[0080] One of the two electrodes of capacitor C21 is connected to one end of switch S21 and one end of switch S22. The other two electrodes of capacitor C21 are connected to one end of switch S25 and one end of switch S26.

[0081] One of the two electrodes of capacitor C22 is connected to one end of switch S23 and one end of switch S24. The other two electrodes of capacitor C22 are connected to one end of switch S27 and one end of switch S28.

[0082] One of the two electrodes of capacitor C23 is connected to one end of switch S25 and one end of switch S26. The other two electrodes of capacitor C23 are connected to one end of switch S29 and one end of switch S2A.

[0083] One of the two electrodes of capacitor C24 is connected to one end of switch S27 and one end of switch S28. The other two electrodes of capacitor C24 are connected to one end of switch S2B and one end of switch S2C.

[0084] Capacitors C25 to C27 are smoothing capacitors used to maintain and smooth the voltage (V1 to V3) at nodes N1 to N3.

[0085] Capacitor C25 is connected between nodes N2 and N3. Specifically, one of the two electrodes of capacitor C25 is connected to node N3. On the other hand, the other two electrodes of capacitor C25 are connected to node N2.

[0086] Capacitor C26 is connected between nodes N1 and N2. Specifically, one of the two electrodes of capacitor C26 is connected to node N2. On the other hand, the other two electrodes of capacitor C26 are connected to node N1.

[0087] Capacitor C27 is connected between node N1 and ground. Specifically, one of the two electrodes of capacitor C27 is connected to node N1. On the other hand, the other electrode of capacitor C27 is connected to ground.

[0088] Switch S21 is connected between capacitor C21 and node N2. Specifically, one end of switch S21 is connected to one of the two electrodes of capacitor C21. On the other hand, the other end of switch S21 is connected to node N2.

[0089] Switch S22 is connected between capacitor C21 and node N3. Specifically, one end of switch S22 is connected to one of the two electrodes of capacitor C21. On the other hand, the other end of switch S22 is connected to node N3.

[0090] Switch S23 is connected between capacitor C22 and node N2. Specifically, one end of switch S23 is connected to one of the two electrodes of capacitor C22. On the other hand, the other end of switch S23 is connected to node N2.

[0091] Switch S24 is connected between capacitor C22 and node N3. Specifically, one end of switch S24 is connected to one of the two electrodes of capacitor C22. On the other hand, the other end of switch S24 is connected to node N3.

[0092] Switch S25 is connected between capacitors C21 and C23 and node N1. Specifically, one end of switch S25 is connected to the other two electrodes of capacitor C21 and one of the two electrodes of capacitor C23. On the other hand, the other end of switch S25 is connected to node N1.

[0093] Switch S26 is connected between capacitors C21 and C23 and node N2. Specifically, one end of switch S26 is connected to the other two electrodes of capacitor C21 and one of the two electrodes of capacitor C23. On the other hand, the other end of switch S26 is connected to node N2.

[0094] Switch S27 is connected between capacitors C22 and C24 and node N1. Specifically, one end of switch S27 is connected to the other side of the two electrodes of capacitor C22 and one side of the two electrodes of capacitor C24. On the other hand, the other end of switch S27 is connected to node N1.

[0095] Switch S28 is connected between capacitors C22 and C24 and node N2. Specifically, one end of switch S28 is connected to the other two electrodes of capacitor C22 and one of the two electrodes of capacitor C24. On the other hand, the other end of switch S28 is connected to node N2.

[0096] Switch S29 is connected between capacitor C23 and ground. Specifically, one end of switch S29 is connected to the other end of the two electrodes of capacitor C23. On the other hand, the other end of switch S29 is connected to ground.

[0097] Switch S2A is connected between capacitor C23 and node N1. Specifically, one end of switch S2A is connected to the other end of the two electrodes of capacitor C23. On the other hand, the other end of switch S2A is connected to node N1.

[0098] Switch S2B is connected between capacitor C24 and ground. Specifically, one end of switch S2B is connected to the other end of the two electrodes of capacitor C24. On the other hand, the other end of switch S2B is connected to ground.

[0099] Switch S2C is connected between capacitor C24 and node N1. Specifically, one end of switch S2C is connected to the other end of the two electrodes of capacitor C24. On the other hand, the other end of switch S2C is connected to node N1.

[0100] The first set of switches, including switches S22, S23, S26, S27, S2A and S2B, and the second set of switches, including switches S21, S24, S25, S28, S29 and S2C, switch on and off in opposite directions based on the control signal CS20 from the digital control circuit 60.

[0101] Specifically, in the first stage, the first set of switches is closed and the second set of switches is opened. As a result, one of the two electrodes of capacitor C21 is connected to node N3; the other two electrodes of capacitor C21, one of the two electrodes of capacitor C22, and one of the two electrodes of capacitor C23 are connected to node N2; the other two electrodes of capacitor C22, the other two electrodes of capacitor C23, and one of the two electrodes of capacitor C24 are connected to node N3; and the other two electrodes of capacitor C24 are connected to the ground wire.

[0102] Conversely, in the second stage, the first set of switches is opened and the second set of switches is closed. As a result, one of the two electrodes of capacitor C22 is connected to node N3; one of the two electrodes of capacitor C21, the other of the two electrodes of capacitor C22, and one of the two electrodes of capacitor C24 are connected to node N2; the other of the two electrodes of capacitor C21, one of the two electrodes of capacitor C23, and the other of the two electrodes of capacitor C24 are connected to node N3; and the other of the two electrodes of capacitor C23 is connected to ground.

[0103] By repeating this first and second stage, capacitors C21 to C24 can be charged and discharged complementaryly. For example, in one of the first and second stages, capacitors C25 to C27 are charged from capacitors C21 and C23, and in the other of the first and second stages, capacitors C25 to C27 are charged from capacitors C22 and C24. In other words, since capacitors C25 to C27 are always charged from any one of capacitors C21 to C24, even if current flows at high speed from nodes N1, N2, or N3 to the power modulation circuit 30, charge can be replenished at high speed at nodes N1, N2, or N3, suppressing potential fluctuations at nodes N1, N2, or N3.

[0104] By operating in this way, the switched capacitor circuit 20 can maintain approximately equal voltages across each of the capacitors C25 to C27. Specifically, at the three nodes N1 to N3 labeled with V1 to V3, V1 to V3 are maintained at a ratio of (V3-V2):(V2-V1):(V1-VG) = 1:1:1.

[0105] Furthermore, (V3-V2):(V2-V1):(V1-VG) is not limited to 1:1:1 and can be designed as any ratio (e.g., 1:2:3, 1:2:4, 3:2:1, 4:2:1, etc.).

[0106] [1.2.3 Circuit structure of power modulation circuit 30]

[0107] Next, refer to Figure 3 The circuit structure of the power modulation circuit 30 included in the tracker circuit 1 will be described.

[0108] The power modulation circuit 30 includes input terminals T31 to T33, switches S31 to S33, and output terminal T34.

[0109] Input terminals T31 to T33 are used to receive multiple discrete voltages (V1 to V3) generated by the switched capacitor circuit 20. Input terminals T31 to T33 are externally connected to the output terminals T22 to T24 of the switched capacitor circuit 20, and internally connected to switches S31 to S33, respectively.

[0110] Output terminal T34 is used to selectively supply at least one of a plurality of discrete voltages to power amplifier 2. Output terminal T34 is externally connected to power amplifier 2 and internally connected to switches S31 to S33.

[0111] Switch S31 is connected between input terminal T31 and output terminal T34. In this connection structure, switch S31 can switch the connection or non-connection between input terminal T31 and output terminal T34 by switching on and off according to the control signal CS31 from switch control circuit 50.

[0112] Switch S32 is connected between input terminal T32 and output terminal T34. In this connection structure, switch S32 can switch the connection or non-connection between input terminal T32 and output terminal T34 by switching on and off according to the control signal CS32 from switch control circuit 50.

[0113] Switch S33 is connected between input terminal T33 and output terminal T34. In this connection structure, switch S33 can switch the connection or non-connection between input terminal T33 and output terminal T34 by switching on and off according to the control signal CS33 from switch control circuit 50.

[0114] In this embodiment, these switches S31 to S33 are controlled to be exclusively turned on. In other words, they are controlled to close only one of switches S31 to S33, while opening all the remaining switches S31 to S33. As a result, the power modulation circuit 30 can supply a voltage selected from a plurality of discrete voltages (V1 to V3) to the power amplifier 2.

[0115] also, Figure 3 The structure of the power modulation circuit 30 shown is an example and is not limited thereto. In particular, switches S31 to S33 can be of any structure as long as they can selectively connect at least one of the three input terminals T31 to T33 to the output terminal T34, and can be controlled arbitrarily. For example, two of switches S31 to S33 can be closed and the remaining one of switches S31 to S33 can be opened.

[0116] [1.2.4 Circuit structure of envelope detector circuit 40]

[0117] Next, refer to Figure 4 The circuit structure of the envelope detection circuit 40 included in the tracker circuit 1 will be described. The envelope detection circuit 40 includes an input terminal T41, an output terminal T42, a diode D41, a capacitor C41, and a resistor R41.

[0118] Input terminal T41 is used to receive high-frequency signals. Input terminal T41 is externally connected to external connection terminal 102 and internally connected to the input terminal of diode D41.

[0119] Output terminal T42 is used to supply the envelope signal to the switch control circuit 50. Output terminal T42 is externally connected to the switch control circuit 50 and internally connected to the output terminal of diode D41.

[0120] Diode D41 is connected between input terminal T41 and output terminal T42.

[0121] Capacitor C41 is connected in parallel with resistor R41 between the path between the output terminal of diode D41 and the output terminal T42 and the ground line.

[0122] Resistor R41 is connected in parallel with capacitor C41 between the path between the output terminal of diode D41 and the output terminal T42 and the ground line.

[0123] In addition, Figure 4 The simplest circuit structure of the envelope detector circuit 40 is illustrated in the figure, but the circuit structure of the envelope detector circuit 40 is not limited to this.

[0124] [1.2.5 Circuit structure of switch control circuit 50]

[0125] Next, refer to Figure 4 The circuit structure of the switch control circuit 50 included in the tracker circuit 1 is described.

[0126] The switch control circuit 50 has an input terminal T51, output terminals T52 to T54, and comparators C51 to C54.

[0127] Input terminal T51 is used to receive envelope signals. Input terminal T51 is externally connected to envelope detection circuit 40 and internally connected to comparators C51 to C54.

[0128] Output terminals T52 to T54 are used to supply control signals CS31 to CS33 to the power modulation circuit 30, respectively. Output terminals T52 to T54 are connected to the power modulation circuit 30.

[0129] Control signals CS31 to CS33 are examples of the second control signals, used to select at least one voltage from a plurality of discrete voltages. Specifically, control signals CS31 to CS33 are used to control the opening and closing of switches S31 to S33 of the power modulation circuit 30, respectively.

[0130] In this embodiment, when the control signal CS31 has a high voltage level, switch S31 is closed; when the control signal CS31 has a low voltage level, switch S31 is opened. Similarly, when the control signal CS32 has a high voltage level, switch S32 is closed; when the control signal CS32 has a low voltage level, switch S32 is opened. Likewise, when the control signal CS33 has a high voltage level, switch S33 is closed; when the control signal CS33 has a low voltage level, switch S33 is opened.

[0131] Furthermore, the relationship between the voltage of control signals CS31 to CS33 and the opening and closing of switches S31 to S33 can also be reversed. In other words, the switches can be opened when the control signal has a high voltage level, or closed when the control signal has a low voltage level.

[0132] Comparator C51 compares the envelope signal with a reference voltage Vref1. The non-inverting input of comparator C51 is connected to the voltage source of the reference voltage Vref1. The inverting input of comparator C51 is connected to input terminal T51. The output of comparator C51 is connected to output terminal T52. Therefore, when the reference voltage Vref1 is higher than the envelope signal, comparator C51 outputs a high-level voltage to output terminal T52, providing a control signal CS31. Conversely, when the reference voltage Vref1 is lower than the envelope signal, comparator C51 outputs a low-level voltage to output terminal T52, providing the control signal CS31.

[0133] Comparator C52 compares the envelope signal with a reference voltage Vref1. The non-inverting input of comparator C52 is connected to input terminal T51. The inverting input of comparator C52 is connected to the voltage source Vref1. The output of comparator C52 is connected to output terminal T53.

[0134] Comparator C53 compares the envelope signal with a reference voltage Vref2. The non-inverting input of comparator C53 is connected to the voltage source of the reference voltage Vref2. The inverting input of comparator C53 is connected to input terminal T51. The output of comparator C53 is connected to output terminal T53. Furthermore, the reference voltage Vref2 is higher than the reference voltage Vref1.

[0135] Comparators C52 and C53 constitute a window comparator circuit. The window comparator circuit can output a high-level voltage to the output terminal T53 when the envelope signal is within the range of the reference voltages Vref1 and Vref2, and output a low-level voltage to the output terminal T53 when the envelope signal is not within the range of the reference voltages Vref1 and Vref2.

[0136] Comparator C54 compares the envelope signal with a reference voltage Vref2. The non-inverting input of comparator C54 is connected to input terminal T51. The inverting input of comparator C54 is connected to the voltage source of the reference voltage Vref2. The output of comparator C54 is connected to output terminal T54. Therefore, comparator C54 can output a high-level voltage to output terminal T54 when the envelope signal is higher than the reference voltage Vref2, and output a low-level voltage to output terminal T54 when the envelope signal is lower than the reference voltage Vref2.

[0137] As described above, when the envelope signal is lower than the reference voltage Vref1, the switch control circuit 50 can generate a control signal CS31 for selecting a first voltage (V1) from multiple discrete voltages. Furthermore, when the envelope signal is higher than the reference voltage Vref1 and lower than the reference voltage Vref2, the switch control circuit 50 can generate a control signal CS32 for selecting a second voltage (V2) from multiple discrete voltages. And when the envelope signal is higher than the reference voltage Vref2, the switch control circuit 50 can generate a control signal CS33 for selecting a third voltage (V3) from multiple discrete voltages.

[0138] also, Figure 4 The circuit structure of the switch control circuit 50 shown is illustrative and is not limited thereto. For example, the switch control circuit 50 may also be configured to output digital control line (DCL) signals to the digital control circuit 60 instead of control signals CS31 to CS33. In this case, the digital control circuit 60 may also generate control signals CS31 to CS33 for switches S31 to S33 based on the DCL signals.

[0139] [1.2.6 Circuit structure of digital control circuit 60]

[0140] Next, refer to Figure 4 The circuit structure of the digital control circuit 60 included in the tracker circuit 1 is described.

[0141] The digital control circuit 60 can accept digital control signals (an example of a first control signal) based on a serial data transmission standard via an external connection terminal 101. Figure 4 In this circuit, the digital control signal, which is based on the serial data transmission standard, uses a source-synchronous digital control signal. Therefore, the digital control circuit 60 can receive the clock signal (CLK) and the data signal (DATA) via two external connection terminals 101.

[0142] The digital control circuit 60 processes the clock signal (CLK) and the data signal (DATA) to generate control signals CS10 and CS20, respectively, for controlling the pre-conditioner circuit 10 and the switched capacitor circuit 20. Control signal CS10 controls the opening and closing of switches S11 to S14 in the pre-conditioner circuit 10, and control signal CS20 controls switches S21 to S2C in the switched capacitor circuit 20.

[0143] [1.3 Magnification Method]

[0144] Next, refer to Figure 5 The scaling-up method of this embodiment will be described. Figure 5 This is a flowchart illustrating the scaling-up method of this embodiment.

[0145] First, RFIC4 generates a high-frequency signal (S101). Pre-conditioner circuit 10 and switched capacitor circuit 20 generate multiple discrete voltages (V1 to V3) (S102). Envelope detection circuit 40 detects the envelope of the high-frequency signal generated by RFIC4 (S103). Power modulation circuit 30 selects at least one voltage from the multiple discrete voltages (V1 to V3) based on the envelope detected by envelope detection circuit 40 (S104). Power amplifier 2 amplifies the high-frequency signal generated by RFIC4 using the selected at least one voltage (S105).

[0146] [1.4 Installation example of communication device 6]

[0147] Next, refer to Figure 6 An example of the installation of communication device 6 will be described. Figure 6 This is a component configuration diagram of the communication device 6 according to this embodiment. Furthermore, in Figure 6 In order to easily understand the configuration relationship of each component, each component is given an abbreviation indicating its function ("ANT", etc.), but the actual components may not be given this abbreviation. Additionally, in... Figure 6 In this context, simple lines represent conductors that electrically connect components.

[0148] The mother substrate 8 is equipped with a tracker module (DET), a PA module (PA1), and an RFIC4.

[0149] Tracker circuit 1 is mounted on the tracker module (DET). The tracker module (DET) is positioned adjacent to the PA module (PA1) when viewed from above the motherboard 8. External connection terminal 101 of the tracker module (DET) is connected to RFIC 4, from which clock signal (CLK) and data signal (DATA) are supplied. External connection terminal 102 of the tracker module (DET) is connected to RFIC 4, from which high-frequency signal (RF) is supplied. Here, the conductor connecting RFIC 4 and the tracker module (DET) branches off from the conductor connecting RFIC 4 and the PA module (PA1). External connection terminal 103 of the tracker module (DET) is connected to the PA module (PA1), supplying power supply voltage (Vcc).

[0150] Power amplifier 2 is installed in PA module (PA1). PA module (PA1) is located near antenna 5.

[0151] Antenna 5 (ANT) is located on the upper side of the mother substrate 8, near the PA module (PA1).

[0152] [1.5 Effects, etc.]

[0153] As described above, the transmission system 7 of this embodiment includes an RFIC 4 configured to generate a first high-frequency signal, a power amplifier 2 configured to amplify the first high-frequency signal, and a tracker circuit 1 configured to selectively supply at least one of a plurality of discrete voltages to the power amplifier 2. The tracker circuit 1 is configured to receive the first high-frequency signal generated by the RFIC 4 and select at least one voltage from the plurality of discrete voltages.

[0154] Therefore, since RFIC4 receives high-frequency signals and selects at least one voltage from multiple discrete voltages, it is not necessary to generate a digital control signal for voltage selection. In D-ET, voltage switching is required at high speed based on the envelope, making it difficult to control voltage selection using digital control signals based on conventional serial data transmission standards. Therefore, conventionally, when using digital control signals based on parallel data transmission standards (e.g., digital control level signals), a circuit for generating such signals needs to be set up in RFIC4. In contrast, in the transmission system 7 of this embodiment, since the tracker circuit 1 receives high-frequency signals and selects voltage, a circuit for generating digital control signals based on parallel data transmission standards does not need to be set up in RFIC4, and D-ET can be implemented with a simple RFIC4.

[0155] Alternatively, in the transmission system 7 of this embodiment, the tracker circuit 1 may include an envelope detection circuit 40 configured to receive a first high-frequency signal generated by RFIC4 and detect the envelope of the first high-frequency signal, and a switch control circuit 50 configured to generate a control signal for selecting at least one voltage from a plurality of discrete voltages based on the envelope detected by the envelope detection circuit 40.

[0156] Accordingly, the voltage selection can be controlled based on the envelope detected by the envelope detection circuit 40, and the voltage can be switched at high speed with a relatively simple circuit.

[0157] Alternatively, for example, in the transmission system 7 of this embodiment, the multiple discrete voltages may include a first voltage and a second voltage that is higher than the first voltage. The switch control circuit 50 may also be configured to generate a control signal for selecting the first voltage from the multiple discrete voltages when the envelope is lower than the reference voltage, or to generate a control signal for selecting the second voltage from the multiple discrete voltages when the envelope is higher than the reference voltage.

[0158] Therefore, control signals can be generated by comparing the envelope with a reference voltage, and control signals can be generated at high speed using relatively simple circuits such as comparators.

[0159] Alternatively, in the transmission system 7 of this embodiment, the switch control circuit 50 may be configured to generate a digital control level signal as a control signal.

[0160] Accordingly, the DCL signal can be generated by the switch control circuit 50 instead of RFIC4, and the digital control circuit that selects the control voltage based on the DCL signal can be used in the tracker circuit 1.

[0161] Furthermore, the tracker circuit 1 of this embodiment includes a voltage generation circuit 25 configured to generate multiple discrete voltages, a power modulation circuit 30 configured to selectively output at least one of the multiple discrete voltages to a power amplifier 2, an external connection terminal 101 for inputting a first control signal (CLK, DATA) based on a serial data transmission standard, and an external connection terminal 102 for inputting a high-frequency signal amplified by the power amplifier 2. The voltage generation circuit 25 is controlled based on the first control signal, and the power modulation circuit 30 is controlled based on the high-frequency signal.

[0162] Therefore, since the power modulation circuit 30 is controlled by a high-frequency signal, the tracker circuit 1 does not need to receive digital control signals for voltage selection from RFIC4. Thus, it is not necessary to include a circuit in RFIC4 to generate digital control signals based on parallel data transmission standards; D-ET can be implemented using a simple RFIC4.

[0163] Alternatively, for example, the tracker circuit 1 of this embodiment may further include an envelope detection circuit 40 configured to detect the envelope of a high-frequency signal input via an external connection terminal 102, and a switch control circuit 50 configured to generate a second control signal (CS31 to CS33) for selecting at least one voltage from a plurality of discrete voltages based on the envelope detected by the envelope detection circuit 40.

[0164] Accordingly, the voltage selection can be controlled based on the envelope detected by the envelope detection circuit 40, and the voltage can be switched at high speed with a relatively simple circuit.

[0165] Alternatively, for example, in the tracker circuit 1 of this embodiment, the switch control circuit 50 may include comparators C51 to C54 that compare the envelope with a reference voltage.

[0166] Therefore, a relatively simple circuit such as comparators C51 to C54 can be used to construct a switch control circuit 50.

[0167] Alternatively, for example, in the transmission system 7 of this embodiment, the switch control circuit 50 may be configured to generate a digital control level signal as a second control signal.

[0168] Accordingly, the DCL signal can be generated by the switch control circuit 50 instead of RFIC4, and the digital control circuit that selects the control voltage based on the DCL signal can be used in the tracker circuit 1.

[0169] In addition, the amplification method of this embodiment generates a high-frequency signal (S101), generates a plurality of discrete voltages (S102), detects the envelope of the generated high-frequency signal (S103), selects at least one voltage from the plurality of generated discrete voltages based on the detected envelope (S104), and amplifies the high-frequency signal using the selected at least one voltage (S105).

[0170] Therefore, since the voltage is selected based on the envelope detected by the high-frequency signal, the RFIC4 does not need to generate a digital control signal for voltage selection. Thus, it is not necessary to include a circuit in the RFIC4 to generate a digital control signal based on the parallel data transmission standard, and D-ET can be implemented with a simple RFIC4.

[0171] (Implementation Method 2)

[0172] Next, Embodiment 2 will be described. The main difference from Embodiment 1 is that the communication device includes a power amplifier that uses APT mode instead of D-ET mode. Hereinafter, this embodiment will be described with reference to the accompanying drawings, focusing on the differences from Embodiment 1.

[0173] [2.1 Circuit structure of communication device 6A]

[0174] Reference Figure 7 The circuit structure of the communication device 6A in this embodiment will be described. Figure 7 This is a circuit diagram of the communication device 6A according to this embodiment.

[0175] also, Figure 7 The circuit structure shown is illustrative; the communication device 6A can be installed using a variety of circuit mounting methods and any of the circuit technologies employed. Therefore, the following description of the communication device 6A should not be interpreted in a restrictive manner.

[0176] The communication device 6A of this embodiment includes a transmission system 7A and an antenna 5. The transmission system 7A includes a tracker circuit 1, a power amplifier 2, a DC power supply 3, an RFIC 4A, a DC / DC converter circuit 10A, and a power amplifier 2A.

[0177] In addition to supplying the first high-frequency signal to power amplifier 2A, RFIC4A can also generate a second high-frequency signal to power amplifier 2A.

[0178] DC / DC converter circuit 10A converts the input voltage (Vbat) from DC power supply 3 into a supply voltage (Vcc) for power amplifier 2A. DC / DC converter circuit 10A can vary the supply voltage (Vcc) to power amplifier 2A based on the average power of the second high-frequency signal supplied to power amplifier 2A. Therefore, DC / DC converter circuit 10A can apply APT mode to power amplifier 2A. DC / DC converter circuit 10A has the same circuit structure as pre-regulator circuit 10, so its diagram and description are omitted.

[0179] Power amplifier 2A is connected between RFIC 4A and antenna 5. Furthermore, power amplifier 2A is connected to DC / DC converter circuit 10A. Power amplifier 2A can amplify the second high-frequency signal supplied from RFIC 4A using the voltage supplied from DC / DC converter circuit 10A.

[0180] [2.2 Installation Example of Communication Device 6A]

[0181] Next, refer to Figure 8 An installation example of the communication device 6A will be described. Figure 8 This is a component configuration diagram of the communication device 6A according to this embodiment. Furthermore, in Figure 8 In order to easily understand the configuration relationship of each component, each component is given an abbreviation indicating its function ("ANT", etc.), but the actual components may not be given this abbreviation. Additionally, in... Figure 8 In this context, simple lines represent conductors that electrically connect components.

[0182] The motherboard 8 is equipped with a tracker module (DET), a PA module (PA1, PA2), an RFIC4A, and a converter module (DC / DC).

[0183] A DC / DC converter circuit 10A is mounted in the converter module (DC / DC). The converter module (DC / DC) is configured adjacent to the PA module (PA2) when viewed from above the motherboard 8.

[0184] A power amplifier 2A is installed in the PA module (PA2). The PA module (PA2) is positioned near the antenna 5.

[0185] [2.3 Effects, etc.]

[0186] As described above, in the transmission system 7A of this embodiment, the RFIC 4A may also be configured to further generate a second high-frequency signal, and the transmission system 7A may also include a DC / DC converter circuit 10A configured to convert the input voltage into a supply voltage, and a power amplifier 2A configured to amplify the second high-frequency signal using the supply voltage from the DC / DC converter circuit 10A.

[0187] Therefore, D-ET and APT can be implemented using a simple RFIC4A.

[0188] (Other implementation methods)

[0189] The above description, based on embodiments, outlines the transmitting system, tracker circuit, and amplification method of the present invention. However, the transmitting system, tracker circuit, and amplification method of the present invention are not limited to the above embodiments. Other embodiments implemented by combining any of the constituent elements in the above embodiments, variations of the above embodiments that can be conceived by those skilled in the art without departing from the spirit of the present invention, and various devices that incorporate the above transmitting system or the above tracker circuit are also included in the present invention.

[0190] For example, in the circuit structures of the various circuits in the above embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the figures. For example, a filter and / or impedance matching circuit may be inserted between the power amplifier 2 and the antenna 5.

[0191] Alternatively, in the embodiments described above, the number of discrete voltages generated by the switched capacitor circuit 20 may be two or more. In this case, the number of cascaded stages of the switched capacitor circuit 20 may also be increased.

[0192] Alternatively, for example, the tracker circuit 1 can also supply voltage to multiple power amplifiers. In this case, the tracker circuit 1 can also include multiple power modulation circuits 30.

[0193] The following describes the features of the transmission system, tracker circuit, and amplification method described based on the above embodiments.

[0194] <1> A transmission system, comprising:

[0195] The signal processing circuit is configured to generate a first high-frequency signal;

[0196] A first power amplifier is configured to amplify the aforementioned first high-frequency signal; and

[0197] The tracker circuit is configured to selectively supply at least one of a plurality of discrete voltages to the aforementioned first power amplifier.

[0198] The tracker circuit described above is configured to receive the first high-frequency signal generated by the signal processing circuit described above and select at least one voltage from the plurality of discrete voltages described above.

[0199] <2> According to the transmission system described in <1>,

[0200] The above tracker circuit includes:

[0201] An envelope detection circuit is configured to receive the first high-frequency signal generated by the signal processing circuit described above, and to detect the envelope of the first high-frequency signal; and

[0202] The switching control circuit is configured to generate a control signal for selecting at least one voltage from the plurality of discrete voltages based on the envelope detected by the envelope detection circuit.

[0203] <3> According to the sending system described in <2>,

[0204] The aforementioned discrete voltages include a first voltage and a second voltage that is higher than the first voltage.

[0205] The aforementioned switch control circuit is configured to generate a control signal for selecting the first voltage from the plurality of discrete voltages when the envelope is lower than the reference voltage, and to generate a control signal for selecting the second voltage from the plurality of discrete voltages when the envelope is higher than the reference voltage.

[0206] <4> According to the transmission system described in <2> or <3>,

[0207] The aforementioned switch control circuit is configured to generate a digital control level signal, which serves as the aforementioned control signal.

[0208] <5> According to any one of the transmission systems described in <1> to <4>,

[0209] The aforementioned signal processing circuit is configured to further generate a second high-frequency signal.

[0210] The aforementioned sending system also has:

[0211] A converter circuit is configured to convert an input voltage into a supply voltage; and

[0212] The second power amplifier is configured to amplify the second high-frequency signal using the supply voltage from the converter circuit described above.

[0213] <6> A tracker circuit, comprising:

[0214] The voltage generation circuit is configured to generate multiple discrete voltages;

[0215] The power supply modulation circuit is configured to selectively output at least one of the aforementioned discrete voltages to a power amplifier.

[0216] The first external connection terminal receives a first control signal based on a serial data transmission standard; and

[0217] The second external connection terminal receives the high-frequency signal amplified by the aforementioned power amplifier.

[0218] The voltage generation circuit is controlled based on the first control signal mentioned above.

[0219] The power modulation circuit is controlled based on the aforementioned high-frequency signal.

[0220] <7> Based on the tracker circuit described in <6>,

[0221] The tracker circuit described above also features:

[0222] The envelope detection circuit is configured to detect the envelope of the high-frequency signal input via the second external connection terminal; and

[0223] The switching control circuit is configured to generate a second control signal for selecting at least one voltage from the plurality of discrete voltages based on the envelope detected by the envelope detection circuit.

[0224] <8> Based on the tracker circuit described in <7>,

[0225] The aforementioned switch control circuit includes a comparator that compares the envelope with a reference voltage.

[0226] <9> Based on the tracker circuit described in <7> or <8>,

[0227] The aforementioned switch control circuit is configured to generate a digital control level signal, which serves as the second control signal.

[0228] <10> A method of magnification,

[0229] Generate high-frequency signals,

[0230] Generate multiple discrete voltages,

[0231] Detect the envelope of the generated high-frequency signal.

[0232] Based on the detected envelope, at least one voltage is selected from the generated plurality of discrete voltages.

[0233] The high-frequency signal is amplified using at least one of the selected voltages.

[0234] This invention can be used as a transmission system for high-frequency signals and can be widely applied to communication devices such as mobile phones.

[0235] Explanation of reference numerals in the attached figures

[0236] 1… Tracker circuit, 2, 2A… Power amplifier, 3… DC power supply, 4, 4A… RFIC, 5… Antenna, 6, 6A… Communication device, 7, 7A… Transmission system, 8… Mother substrate, 10… Pre-conditioner circuit, 10A… DC / DC converter circuit, 20… Switched capacitor circuit, 25… Voltage generation circuit, 30… Power modulation circuit, 40… Envelope detector circuit, 50… Switch control circuit, 60… Digital control circuit, 101, 102, 103… External connection terminals.

Claims

1. A transmission system, wherein, have: The signal processing circuit is configured to generate a first high-frequency signal; A first power amplifier is configured to amplify the aforementioned first high-frequency signal; and The tracker circuit is configured to selectively supply at least one of a plurality of discrete voltages to the aforementioned first power amplifier. The tracker circuit described above is configured to receive the first high-frequency signal generated by the signal processing circuit described above and select at least one voltage from the plurality of discrete voltages described above.

2. The sending system according to claim 1, wherein, The above tracker circuit includes: An envelope detection circuit is configured to receive the first high-frequency signal generated by the signal processing circuit described above, and to detect the envelope of the first high-frequency signal; and The switching control circuit is configured to generate a control signal for selecting at least one voltage from the plurality of discrete voltages based on the envelope detected by the envelope detection circuit.

3. The sending system according to claim 2, wherein, The aforementioned discrete voltages include a first voltage and a second voltage that is higher than the first voltage. The aforementioned switch control circuit is configured to generate a control signal for selecting the first voltage from the plurality of discrete voltages when the envelope is lower than the reference voltage, and to generate a control signal for selecting the second voltage from the plurality of discrete voltages when the envelope is higher than the reference voltage.

4. The sending system according to claim 2 or 3, wherein, The aforementioned switch control circuit is configured to generate a digital control level signal, which serves as the aforementioned control signal.

5. The transmission system according to any one of claims 1 to 4, wherein, The aforementioned signal processing circuit is configured to further generate a second high-frequency signal. The aforementioned sending system also has: A converter circuit is configured to convert an input voltage into a supply voltage; and The second power amplifier is configured to amplify the second high-frequency signal using the supply voltage from the converter circuit described above.

6. A tracker circuit, wherein, have: The voltage generation circuit is configured to generate multiple discrete voltages; The power supply modulation circuit is configured to selectively output at least one of the aforementioned discrete voltages to a power amplifier. The first external connection terminal receives a first control signal based on a serial data transmission standard. as well as The second external connection terminal receives the high-frequency signal amplified by the aforementioned power amplifier. The voltage generation circuit is controlled based on the first control signal mentioned above. The power modulation circuit is controlled based on the aforementioned high-frequency signal.

7. The tracker circuit according to claim 6, wherein, The tracker circuit described above also features: The envelope detection circuit is configured to detect the envelope of the high-frequency signal input via the second external connection terminal; and The switching control circuit is configured to generate a second control signal for selecting at least one voltage from the plurality of discrete voltages based on the envelope detected by the envelope detection circuit.

8. The tracker circuit according to claim 7, wherein, The aforementioned switch control circuit includes a comparator that compares the envelope with a reference voltage.

9. The tracker circuit according to claim 7 or 8, wherein, The aforementioned switch control circuit is configured to generate a digital control level signal, which serves as the second control signal.

10. A magnification method, wherein, Generate high-frequency signals, Generate multiple discrete voltages, Detect the envelope of the generated high-frequency signal. Based on the detected envelope, at least one voltage is selected from the generated plurality of discrete voltages. The high-frequency signal is amplified using at least one of the selected voltages.

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