Multi-threshold voltage integration scheme for complementary field effect transistors

Abstract

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices (e.g., complementary field effect transistors (CFETs)) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multiple Vt), and have improved device performance and reliability. Some embodiments of the method include conventional dipole engineering techniques, such as dipole pre-processing and / or dipole post-processing, without the need to repair the interface layer after processing (in dipole pre-processing) or repair the high dielectric constant dielectric layer after annealing processing (in dipole post-processing).

Description

Technical Field

[0001] The embodiments of this disclosure pertain to the field of electronic device manufacturing, and more specifically, to transistors. More specifically, the embodiments of this disclosure relate to complementary field-effect transistors (CFETs) and methods for manufacturing CFETs. Background Technology

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single wafer. In the development of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) has typically increased while geometric dimensions (i.e., the smallest components (or lines) that can be produced using manufacturing processes) have decreased.

[0003] Transistors are circuit components or elements that are frequently formed on semiconductor devices. Depending on the circuit design, many types of transistors can be formed on semiconductor devices, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other components. Integrated circuits integrate planar field-effect transistors (FETs), in which current flows through a semiconductor channel between the source and drain in response to a voltage applied to the control gate.

[0004] Since the drive current and thus speed of a transistor are proportional to its gate width, faster transistors typically require larger gate widths. Therefore, a trade-off exists between transistor size and speed, and "fin field-effect transistors" (finFETs) have been developed to resolve this conflict between maximizing drive current and minimizing size. FinFETs are characterized by a fin-shaped channel region that significantly increases transistor size without substantially increasing its footprint, and finFETs are currently used in numerous integrated circuits. However, finFETs have their own inherent drawbacks.

[0005] As transistor device feature sizes continue to shrink to achieve greater circuit density and higher efficiency, there is a need to improve transistor device structures to improve electrostatic coupling and reduce side effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, finFET structures, and gate-all-around (GAA) structures. A GAA device structure consists of several lattice-matched channels suspended in a stacked configuration and connected through source / drain regions. GAA structures offer good electrostatic control and are widely used in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0006] An example of GAA technology is the Complementary Field-Effect Transistor (CFET), in which nFET and pFET nanowires / nanofashelves are stacked vertically on top of each other. Compared to GAA transistors, CFET transistors increase on-chip device density and reduce area consumption. When nFETs and pFETs are stacked in a bulk manner, the n and p superlattices are sequentially deposited using an intermediate sacrificial layer, which is selectively removed during processing and replaced with a middle dielectric isolation (MDI) layer. The MDI layer is used to electrically isolate the lower GAA from the upper GAA.

[0007] Each n or p superlattice of a CFET comprises alternating layers of a channel layer and a release layer. The channel layer typically contains silicon (Si). The release layer typically contains silicon germanium (SiGe) with a low concentration of germanium (Ge). To achieve etch contrast between the intermediate dielectric isolation (MDI) layer and the channel and release layers, the intermediate dielectric isolation (MDI) layer contains SiGe with a high concentration of Ge.

[0008] Shrinking the materials currently used in nFETs and pFETs has become a challenge due to changes in fundamental properties such as threshold voltage (Vt). As device dimensions shrink further, the Vt tuning range will be limited by variations in film thickness.

[0009] There are also challenges associated with conventional dipole engineering techniques. To achieve the desired dipole effect, the desired element is driven from the deposited film using spike annealing and then removed after driving. Spike annealing can potentially lead to equivalent oxide thickness (EOT) loss and a high thermal budget, as free oxygen atoms in the gate dielectric layer and the dipole stack above diffuse downwards to oxidize the underlying silicon layer.

[0010] Furthermore, precise control of the amount of dipole material is crucial for achieving the desired threshold voltage Vt (or multiple threshold voltages (multiple Vt)) of the transistor. Conventional dipole engineering techniques include "dipole-first" and "dipole-after" processing. Typically, dipole-first processing involves flowing a metal-containing precursor and reactants over an interface layer to deposit metal atoms on the interface layer (forming a treated interface layer) to achieve the desired dipole effect, followed by depositing a high-dielectric-constant dielectric layer on the treated interface layer. Conventional dipole-first processing also includes repairing the interface layer after processing.

[0011] Dipole post-processing typically involves forming an interface layer on a substrate, forming a high-k dielectric layer on the interface layer, flowing a metal-containing precursor and reactants over the high-k dielectric layer to deposit metal atoms on the high-k dielectric layer, and annealing the substrate to drive the metal atoms into the interface between the interface layer and the high-k dielectric layer to achieve the desired dipole effect. In dipole post-processing, instead of forming an ultrathin surface adsorption layer, atomic layer deposition (ALD) is performed to deposit a dipole layer with a thickness ranging from 3 Å to 20 Å, containing metal atoms, typically in the form of oxides or nitrides. A capping material is usually required on top of the dipole oxide / nitride layer to prevent silicon oxide regrowth during annealing. Conventional dipole post-processing also includes repairing the high-k dielectric layer after annealing.

[0012] In conventional dipole-after processing, multiple annealing steps are required to achieve the increased Vt, as is the case with conventional dipole-first processing. Furthermore, particularly in dipole-first processing, there are challenges associated with Vt offset and leakage. Tuning Vt is even more challenging in CFETs compared to GAA transistors, due to the increased on-chip device density and reduced area consumption.

[0013] Therefore, there is a need for improved methods of manufacturing CFETs that meet the requirements of reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multiple Vt), and have minimal (if any) EOT loss. Summary of the Invention

[0014] One or more embodiments of this disclosure relate to a method of forming a complementary field-effect transistor (CFET). The method includes depositing an interface layer on a vertically stacked superlattice structure on a semiconductor substrate. The vertically stacked superlattice structure includes a first horizontal gate all-around (hGAA) structure on the top surface of the semiconductor substrate, an intermediate dielectric isolation (MDI) layer on the top surface of the first hGAA structure, and a second hGAA structure on the top surface of the intermediate dielectric isolation (MDI) layer. The interface layer is formed on the first hGAA structure, the intermediate dielectric isolation (MDI) layer, and the second hGAA structure. Next, the method includes: depositing a high-k dielectric layer on the interface layer; depositing a first p-type dipole layer on the high-k dielectric layer; depositing a first p-type capping layer on the first p-type dipole layer; depositing a first protective layer on a first portion of the semiconductor substrate to protect a first portion of the first p-type capping layer; etching the vertically stacked superlattice structure to remove the first protective layer from the first portion; and removing a portion of the first p-type capping layer and a portion of the first p-type dipole layer from a second portion of the semiconductor substrate. The first part has a first threshold voltage (Vt) and the second part has a second Vt.After etching a vertically stacked superlattice structure to remove a first protective layer from a first portion and a portion of a first p-type capping layer and a first p-type dipole layer from a second portion of a semiconductor substrate, the method includes: depositing a second p-type dipole layer on the first and second portions, the second p-type dipole layer being formed on a first hGAA structure, an intermediate dielectric isolation (MDI) layer, and a second hGAA structure; depositing a second p-type capping layer on the second p-type dipole layer; depositing a second protective layer on the first and second portions of the semiconductor substrate to protect the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, and the second p-type capping layer; and etching the vertically stacked superlattice structure to remove a first protective layer from a first portion and a portion of a first p-type dipole layer from a second portion of the semiconductor substrate. The second part removes the second protective layer, and removes a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer from the third part of the semiconductor substrate; etches the vertically stacked superlattice structure to remove the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer, and the second p-type dipole layer to expose a high-dielectric-constant dielectric layer on the second hGAA structure; deposits a first n-type dipole layer on the exposed high-dielectric-constant dielectric layer on the second hGAA structure; deposits a first n-type capping layer on the first n-type dipole layer; deposits a third protective layer on the first part of the semiconductor substrate to protect the first portion of the first n-type capping layer; etches the vertically stacked superlattice structure. The stacked superlattice structure is used to remove a third protective layer from the first portion and a portion of the first n-type capping layer and a portion of the first n-type dipole layer from the second portion of the semiconductor substrate; a second n-type dipole layer is deposited on the first and second portions, and the second n-type dipole layer is formed on the second hGAA structure; a second n-type capping layer is deposited on the second n-type dipole layer; a fourth protective layer is deposited on the first and second portions of the semiconductor substrate to protect the second n-type capping layer; the vertically stacked superlattice structure is etched to remove the fourth protective layer from the first and second portions, and a portion of the first p-type capping layer, a portion of the first p-type dipole layer, and a portion of the second p-type capping layer are removed from the third portion of the semiconductor substrate. A portion of a second p-type dipole layer, a portion of a first n-type capping layer, a portion of a first n-type dipole layer, a portion of a second n-type capping layer, and a portion of a second n-type dipole layer; annealing a semiconductor substrate at a temperature less than or equal to 1000°C to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer into a high-dielectric-constant dielectric layer to form an annealed high-dielectric-constant dielectric layer; and etching a vertically stacked superlattice structure to remove each of the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer. Attached Figure Description

[0015] To gain a more detailed understanding of the manner in which the features of this disclosure are described above, a more specific description of the disclosure, which has been briefly summarized above, can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it will be noted that the drawings illustrate only common embodiments of this disclosure and are not intended to limit its scope, as this disclosure may allow for other equivalent embodiments. The embodiments described herein are shown by way of example and are not intended to be limiting in the drawings, in which like references indicate similar elements.

[0016] Figure 1A A process flow diagram of a method for manufacturing a complementary field-effect transistor (CFET) according to one or more embodiments is shown;

[0017] Figure 1B A schematic cross-sectional view of a vertically stacked superlattice structure on a semiconductor substrate according to one or more embodiments is shown;

[0018] Figure 2A Two cross-sectional views of a vertically stacked superlattice structure on a semiconductor substrate according to one or more embodiments are shown, illustrating a first cross-sectional view through the gate (across the fin) and a second cross-sectional view through the fin (across the gate);

[0019] Figure 2B The diagram illustrates the deposition of an interface layer on a vertically stacked superlattice structure according to one or more embodiments, and the subsequent deposition of a high-dielectric-constant dielectric layer on the interface layer. Figure 2A Two cross-sectional views of the semiconductor substrate;

[0020] Figure 2C The diagram illustrates the process following the deposition of a first p-type dipole layer on a high-dielectric-constant dielectric layer, according to one or more embodiments. Figure 2B Two cross-sectional views of the semiconductor substrate;

[0021] Figure 2D The following is illustrated after depositing a first p-type capping layer on a first p-type dipole layer according to one or more embodiments. Figure 2C Two cross-sectional views of the semiconductor substrate;

[0022] Figure 2E This illustrates the process following the deposition of a first protective layer on a first portion of a semiconductor substrate, according to one or more embodiments. Figure 2D Two cross-sectional views of the semiconductor substrate;

[0023] Figure 2F The diagram illustrates the process of etching a vertically stacked superlattice structure to remove a first protective layer from a first portion of a semiconductor substrate, according to one or more embodiments. Figure 2E Two cross-sectional views of the semiconductor substrate;

[0024] Figure 2GThis illustrates the process after depositing a second p-type dipole layer on a first portion and a second portion of a semiconductor substrate according to one or more embodiments. Figure 2F Two cross-sectional views of the semiconductor substrate;

[0025] Figure 2H The following is illustrated after depositing a second p-type capping layer on a second p-type dipole layer according to one or more embodiments. Figure 2G Two cross-sectional views of the semiconductor substrate;

[0026] Figure 2I The diagram illustrates the deposition of a second protective layer on a first portion and a second portion of a semiconductor substrate according to one or more embodiments. Figure 2H Two cross-sectional views of the semiconductor substrate;

[0027] Figure 2J The diagram illustrates the process of etching a vertically stacked superlattice structure to remove a second protective layer from the first and second portions, according to one or more embodiments. Figure 2I Two cross-sectional views of the semiconductor substrate;

[0028] Figure 2K The illustration shows the process after performing a gap-filling process to fill a trench with a p-type dipole gap-filling material, according to one or more embodiments. Figure 2J Two cross-sectional views of the semiconductor substrate;

[0029] Figure 2L The illustration shows, according to one or more embodiments, the etching of a vertically stacked superlattice structure to remove a first p-type capping layer, a first p-type dipole layer, a second p-type capping layer, and a second p-type dipole layer to expose a high-dielectric-constant dielectric layer. Figure 2K Two cross-sectional views of the semiconductor substrate;

[0030] Figure 2M The following is illustrated after depositing a first n-type dipole layer on an exposed high-dielectric-constant dielectric layer, according to one or more embodiments. Figure 2L Two cross-sectional views of the semiconductor substrate;

[0031] Figure 2N The following is illustrated after depositing a first n-type capping layer on a first n-type dipole layer according to one or more embodiments. Figure 2M Two cross-sectional views of the semiconductor substrate;

[0032] Figure 2O This illustrates the process after depositing a third protective layer on a first portion of a semiconductor substrate, according to one or more embodiments. Figure 2N Two cross-sectional views of the semiconductor substrate;

[0033] Figure 2PThe diagram illustrates the process of etching a vertically stacked superlattice structure to remove a third protective layer from a first portion of a semiconductor substrate, according to one or more embodiments. Figure 2O Two cross-sectional views of the semiconductor substrate;

[0034] Figure 2Q The following is illustrated after depositing a second n-type dipole layer on the first and second portions according to one or more embodiments. Figure 2P Two cross-sectional views of the semiconductor substrate;

[0035] Figure 2R The following is illustrated after depositing a second n-type capping layer on a second n-type dipole layer according to one or more embodiments. Figure 2Q Two cross-sectional views of the semiconductor substrate;

[0036] Figure 2S The diagram illustrates the deposition of a fourth protective layer on a first and second portion of a semiconductor substrate according to one or more embodiments. Figure 2R Two cross-sectional views of the semiconductor substrate;

[0037] Figure 2T The illustration shows, according to one or more embodiments, the etching of a vertically stacked superlattice structure to remove a fourth protective layer from a first and second portion of a semiconductor, followed by annealing to form an annealed high-dielectric-constant dielectric layer. Figure 2S Two cross-sectional views of the semiconductor substrate;

[0038] Figure 2U The illustration shows, according to one or more embodiments, the etching of a vertically stacked superlattice structure to remove each of a first p-type dipole layer, a first p-type capping layer, a second p-type dipole layer, a second p-type capping layer, a first n-type dipole layer, a first n-type capping layer, a second n-type dipole layer, and a second p-type capping layer. Figure 2T Two cross-sectional views of the semiconductor substrate. Detailed Implementation

[0039] Before describing several exemplary embodiments of this disclosure, it will be understood that this disclosure is not limited to the details of the construction or processing steps set forth in the following description. This disclosure can have other embodiments and can be practiced or carried out in various ways.

[0040] As used herein, the term “about” means approximately or nearly, and in the context of the numerical value or range described, it means a variation of ±15% or less of the value. For example, values ​​of ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of about.

[0041] As used in this specification and claims, the terms "substrate" or "wafer" refer to the surface on which the processing takes place, or a portion thereof. As will be understood by those skilled in the art, unless the context clearly indicates otherwise, reference to substrate may refer to only a portion of the substrate. Furthermore, reference to deposition on a substrate may mean a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0042] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to treating the film directly on the surface of the substrate itself, any film treatment steps disclosed herein, as disclosed in more detail below, may also be performed on an underlying layer formed on the substrate, and the term “substrate surface” is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film / layer or a portion of a film / layer has already been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0043] The term "on" indicates that there is direct contact between components. The term "directly on" indicates that there is direct contact between components without any intermediate components.

[0044] As used in this specification and claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0045] As used herein, “atomic layer deposition” or “cyclic deposition” refers to the successive exposure of two or more reactive compounds to deposit a material layer on a substrate surface. The substrate, or portions thereof, is individually exposed to two or more reactive compounds introduced into the reaction zone of a processing chamber. In time-domain ALD processing, exposure to each reactive compound is temporally delayed to allow each compound to adhere to and / or react on the substrate surface and subsequently be desorbed from the processing chamber. These reactive compounds are considered to be exposed to the substrate sequentially. In spatial ALD processing, different portions of the substrate surface, or material on the substrate surface, are simultaneously exposed to two or more reactive compounds such that at any given point on the substrate, there is substantially no simultaneous exposure to more than one reactive compound. As used in this specification and claims, and as will be understood by those skilled in the art, the term “substantially” as used in this context means the possibility that a small portion of the substrate may be attributably exposed to multiple reactive gases simultaneously, and that such simultaneous exposure is unintentional.

[0046] In one aspect of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed alternately until the desired film or film thickness is formed on the substrate surface. In either case, the ALD processing of pulsed compound A, purge gas, compound B, and purge gas is a cycle. The cycle may begin with compound A or compound B and continue in the corresponding order until a film with a predetermined thickness is obtained.

[0047] One or more layers deposited on a substrate or substrate surface are continuous. As used herein, the term "continuous" means a layer that covers the entire exposed surface without any gaps or exposed areas of material beneath the deposited layer. A continuous layer may have gaps or exposed areas with a surface area less than about 15% or less than 10% of the total surface area of ​​the layer.

[0048] In one embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are simultaneously delivered to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery device such that any given point on the substrate is exposed to both the first and second reactive gases.

[0049] A transistor is a circuit component or element that is frequently formed on a semiconductor device. Depending on the circuit design, transistors are formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between source and drain regions. In one or more embodiments, the source and drain regions include doped regions of a substrate (such as a semiconductor substrate) and exhibit a doping profile suitable for a particular application. The gate is positioned over the channel region and includes a gate dielectric that is inserted between the gate electrode and the channel region in the semiconductor substrate.

[0050] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field-effect transistor is a voltage-controlled device whose current-carrying capacity is altered by an applied electric field. Field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the device, generated by the voltage difference between the body and the gate. The three terminals of an FET are: the source (S) through which charge carriers enter the channel; the drain (D) through which charge carriers exit the channel; and the gate (G), the terminal that modulates the channel conductivity. Typically, the current entering the channel at the source (S) is designated as I. S And the current entering the channel at the drain (D) is specified as I. D The drain-to-source voltage is specified as V. DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., Id) can be controlled. D ).

[0051] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate whose voltage determines the device's conductivity. This ability to change conductivity using the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitor between the host electrode and a gate electrode located above the host and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated from the host region. These regions can be p-type or n-type, but are of the same type and have a type opposite to the host region. The source and drain (different from the host) are highly doped, as indicated by a "+" symbol after the doping type.

[0052] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the main body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the main body is an n-type substrate region. The source is so named because it is the origin of charge carriers (electrons for n-channel and holes for p-channel) flowing through the channel; similarly, the drain is where charge carriers leave the channel.

[0053] An nMOS FET consists of an n-type source and drain, and a p-type substrate. When a voltage is applied to the gate, holes in the bulk (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and electrons carry current through the induced n-type channel from the source to the drain. Logic gates and other digital devices implemented using NMOS are considered to have NMOS logic. There are three operating modes in NMOS, called cutoff, transistor, and saturation. When the circuit is idle, circuits with NMOS logic gates dissipate quiescent power because DC current flows through the logic gate when the output is low.

[0054] A pMOS FET consists of a p-type source and drain, and an n-type substrate. When a positive voltage is applied between the source and gate (or a negative voltage between the gate and source), a p-type channel of opposite polarity is formed between the source and drain. Holes carry current through the induced p-type channel from the source to the drain. A high voltage on the gate will cause the PMOS to be non-conductive, while a low voltage on the gate will cause it to be conductive. Logic gates and other digital devices implemented using PMOS are considered to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0055] In NMOS, the charge carriers are electrons, while in PMOS, the charge carriers are holes. When a high voltage is applied to the gate, an NMOS will conduct, while a PMOS will not. Furthermore, when a low voltage is applied to the gate, an NMOS will not conduct, and a PMOS will conduct. NMOS is considered faster than PMOS because electrons travel twice as fast in NMOS as holes in PMOS. However, PMOS devices are less susceptible to noise than NMOS devices. Additionally, an NMOS IC will be smaller than a PMOS IC (for the same functionality) because an NMOS can provide half the impedance of a PMOS (with the same geometry and operating conditions).

[0056] As used herein, the term "FinFET" refers to a MOSFET transistor built on a substrate in which the gate is placed on two, three, or four sides of the channel or wrapped around the channel to form a dual-gate structure. The generic name FinFET is given because the source / drain regions form "fins" on the substrate. FinFET devices feature fast switching times and high current densities.

[0057] As used herein, the term "gate-all-around (GAA)" refers to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires or nanoplates or nanosheets, strip channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal strips, thereby making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0058] As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked on top of each other. Each of the NMOS FET devices and PMOS FET devices forming a CFET is a GAA transistor or an hGAA transistor.

[0059] As used herein, the term "nanowire" refers to a wire with a diameter in the nanometer (10⁻⁶) range. -9 Nanowires are nanostructures on the order of meters. A nanowire can also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness varying on a scale ranging from about 0.1 nm to about 1000 nm, or from 0.5 nm to 500 nm, or from 0.5 nm to 100 nm, or from 1 nm to 500 nm, or from 1 nm to 100 nm, or from 1 nm to 50 nm.

[0060] Without being bound by theory, it is assumed that relaxation in a vertically stacked superlattice structure containing one or more hGAAs results in defects in the nanosheet channel layer within the structure. Embodiments of this disclosure advantageously provide transistors comprising a fully strained vertically stacked superlattice structure having a nanosheet channel layer that is defect-free or substantially defect-free. In some embodiments, the presence of defects in the nanosheet channel layer is determined by a reciprocal space mapping (RSM) method. Without being bound by theory, the RSM method is an X-ray diffraction method for collecting diffraction data of a vertically stacked superlattice structure, in which the presence of defects can be observed. As used herein, the term "substantially free" means that the nanosheet channel layer substantially does not contain defects determined by the RSM method.

[0061] Embodiments of this disclosure are illustrated in the accompanying drawings, which show devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of this disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0062] The embodiments of this disclosure are generally related to the field of electronic device manufacturing, and more specifically, to transistors. More specifically, embodiments of this disclosure relate to CFETs and methods of manufacturing CFETs. Devices and processes are described using this background, although those skilled in the art will recognize that the disclosed devices and processes are not limited to the applications shown.

[0063] Figure 1A A process flow diagram of a method 100 for manufacturing a CFET is shown. Figures 2A to 2U A double cross-sectional view of an electronic device (e.g., a transistor, such as a CFET 200) according to one or more embodiments is shown. Figure 1A Method 100 is shown across two pages in the accompanying drawings. Figures 2A to 2U The CFET 200 shown can be derived from Figure 1A The method 100 shown in the figure is used for manufacturing.

[0064] Figure 1BA schematic cross-sectional view of a CFET 200 having a vertically stacked superlattice structure 260 on a semiconductor substrate 202 is shown. The semiconductor substrate 202 has a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Although several examples of materials that can form substrate 202 are described herein, any material that can serve as the basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) falls within the spirit and scope of this disclosure.

[0065] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor produced during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to an n-type semiconductor, a p-type semiconductor has a larger hole concentration compared to the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0066] In one or more embodiments, the vertically stacked superlattice structure 260 includes one or more horizontal gate surround (hGAA) structures 215, 255 on the substrate 202. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate surround (hGAA) structure 215 on the substrate 202. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate surround (hGAA) structure 215 on the top surface 203 of the substrate 202. In some embodiments, the vertically stacked superlattice structure includes a second or upper horizontal gate surround (hGAA) structure 255. Without being bound by any particular operating theory, the first or lower hGAA 215 and the second or upper hGAA 255 may independently comprise the same structure having the same layer. In one or more of the illustrated embodiments, the vertically stacked superlattice structure 260 includes a first hGAA structure 215 on the top surface 203 of the substrate 202, an intermediate dielectric isolation (MDI) layer 240 on the top surface 225 of the first hGAA structure 215, and a second hGAA structure 255 on the top surface 245 of the intermediate dielectric isolation (MDI) layer 240.

[0067] In some embodiments, each of the first hGAA 215 and the second hGAA 255 comprises alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In some embodiments, the plurality of nanosheet release layers 220 and the plurality of nanosheet channel layers 230 may comprise any number of lattice-matched material pairs suitable for forming a vertically stacked superlattice structure 260. In some embodiments, each of the first hGAA 215 and the second hGAA 255 has alternating layers of nanosheet channel layers 230 and nanosheet release layers 220 in the range of 1 to 5 pairs.

[0068] The nanosheet release layer 220 may have any suitable thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness in the range of 5 nm to 15 nm. The nanosheet channel layer 230 may have any suitable thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness in the range of 5 nm to 15 nm.

[0069] In some embodiments, each of the nanosheet channel layers 230 independently comprises silicon (Si). In some embodiments, each of the nanosheet release layers 220 independently comprises silicon germanium (SiGe).

[0070] In one or more embodiments, an intermediate dielectric isolation (MDI) layer 240 is formed between a first or lower hGAA 215 and a second or upper hGAA 255. In one or more embodiments, the intermediate dielectric isolation (MDI) layer 240 is illustrated after selective removal of the intermediate sacrificial layer and replacement of the intermediate sacrificial layer with the intermediate dielectric isolation (MDI) layer 240.

[0071] Selective removal of the sacrificial layer can be performed by any suitable means known to those skilled in the art. In some embodiments, selective removal of the sacrificial layer comprises an etching process that removes the sacrificial layer without removing the nanosheet release layer 220. In some embodiments, the etching process comprises one or more of a wet etching process or a dry etching process. In some embodiments, the etching process is directional etching.

[0072] Intermediate dielectric isolation (MDI) layer 240 is used to electrically isolate the source / drain regions of the lower GAA from the source / drain regions of the upper GAA. In one or more embodiments, intermediate dielectric isolation (MDI) layer 240 comprises silicon germanium (SiGe). In one or more embodiments, intermediate dielectric isolation (MDI) layer 240 comprises SiGe having a higher concentration of germanium (Ge) compared to silicon germanium (SiGe) of nanosheet release layer 220.

[0073] In one or more embodiments, the intermediate dielectric isolation (MDI) layer 240 may have any suitable thickness. In some embodiments, the intermediate dielectric isolation (MDI) layer 240 has a thickness ranging from 15 nm to 90 nm, including the ranges from 15 nm to 80 nm, from 20 nm to 75 nm, from 15 nm to 60 nm, from 15 nm to 50 nm, from 15 nm to 75 nm, and from 20 nm to 50 nm. In some embodiments, increasing the thickness of the intermediate dielectric isolation (MDI) layer 240 to greater than 40 nm increases the etch selectivity between the intermediate dielectric isolation (MDI) layer 240 and the nanosheet release layer 220.

[0074] Embodiments of this disclosure advantageously provide methods for manufacturing electronic devices (e.g., CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multiple Vt), and have improved device performance and reliability. Embodiments of this disclosure advantageously provide improved integration schemes that allow for increased Vt and improved multiple Vt tuning capabilities. Embodiments of this disclosure significantly improve Vt without EOT loss. Some embodiments advantageously provide integration schemes that eliminate the requirement to deposit a liner on top of the CFET (e.g., on top of an nFET or pFET), reduce the number of etching steps, and eliminate the requirement for carbon filling steps. It has been found that reducing the number of etching steps using the processes described herein advantageously eliminates Vt variations in the CFET. Embodiments of this disclosure advantageously provide improved processes that reduce the number of annealing steps used to drive metal atoms from the p-type dipole layer and the n-type dipole layer.

[0075] Embodiments of this disclosure advantageously provide improved integration schemes that include conventional dipole engineering techniques, such as dipole-first processing and / or dipole-post processing. Advantageously, the integration schemes described herein allow the inclusion of conventional dipole engineering techniques without the need to repair the interface layer after processing (in dipole-first processing) or repair the high-dielectric-constant dielectric layer after annealing (in dipole-post processing).

[0076] Figure 1AA process flow diagram of method 100 for fabricating a complementary field-effect transistor (CFET) is shown. In operation 10, method 100 includes depositing an interface layer on the top surface of a vertically stacked superlattice structure on a semiconductor substrate. In operation 12, method 100 includes depositing a high-k dielectric layer on the interface layer. In operation 14, method 100 includes depositing a first p-type dipole layer on the high-k dielectric layer. In operation 16, method 100 includes depositing a first p-type capping layer on the first p-type dipole layer. In operation 18, the method includes depositing a first protective layer on a first portion of the semiconductor substrate. In operation 20, method 100 may include etching the vertically stacked superlattice structure to remove the first protective layer from the first portion, and removing a portion of the first p-type capping layer and a portion of the first p-type dipole layer from a second portion of the semiconductor substrate. In operation 22, method 100 includes depositing a second p-type dipole layer on the first p-type capping layer in the first portion and on the high-k dielectric layer. In operation 24, method 100 includes depositing a second p-type capping layer on the second p-type dipole layer. In operation 26, method 100 includes depositing a second protective layer on a first portion and a second portion of the semiconductor substrate. In operation 28, method 100 may include performing a gap-filling process to fill trenches using a p-type dipole gap-filling material. In operation 30, method 100 includes etching a vertically stacked superlattice structure to remove the second protective layer from the first and second portions, and removing a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer from a third portion of the semiconductor substrate. In operation 32, method 100 may include etching a vertically stacked superlattice structure to remove the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer, and the second p-type dipole layer to expose a high-dielectric-constant dielectric layer on the second hGAA structure. In operation 34, method 100 includes depositing a first n-type dipole layer on a high-dielectric-constant dielectric layer exposed on the second hGAA structure. In operation 36, method 100 includes depositing a first n-type capping layer on the first n-type dipole layer. In operation 38, method 100 includes depositing a third protective layer on a first portion of the semiconductor substrate. In operation 40, method 100 may include etching a vertically stacked superlattice structure to remove the third protective layer from the first portion, and removing a portion of the first n-type capping layer and a portion of the first n-type dipole layer from a second portion of the semiconductor substrate. In operation 42, method 100 includes depositing a second n-type dipole layer on the first portion (on the first n-type capping layer) and on the high-dielectric-constant dielectric layer. In operation 44, method 100 includes depositing a second n-type capping layer on the second n-type dipole layer. In operation 46, method 100 includes depositing a fourth protective layer on both the first and second portions of the semiconductor substrate.In operation 48, method 100 may include etching the vertically stacked superlattice structure to remove the fourth protective layer from the first and second portions, and removing a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, a portion of the second p-type dipole layer, a portion of the first n-type capping layer, a portion of the first n-type dipole layer, a portion of the second n-type capping layer, and a portion of the second n-type dipole layer from the third portion of the semiconductor substrate. In operation 50, method 100 includes annealing the semiconductor substrate at a temperature less than or equal to 1000°C to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer into a high-dielectric-constant dielectric layer to form an annealed high-dielectric-constant dielectric layer. In operation 52, method 100 includes etching a vertically stacked superlattice structure to remove each of a first p-type dipole layer, a first p-type capping layer, a second p-type dipole layer, a second p-type capping layer, a first n-type dipole layer, a first n-type capping layer, a second n-type dipole layer, and a second p-type capping layer.

[0077] For example, if the work function is offset in the P-dip or N-dip band edge after dipole engineering, the method described herein can be used to offset the band edge in the opposite manner. For example, the method described herein can offset the band edge from ultra-low Vt (ULVt), which are the maximum P-dip and / or N-dip band edges, respectively, to low Vt (LVt) or standard Vt (SVt), or intermediate gap: high Vt (HVt).

[0078] Without being bound by theory, it is believed that selectively etching dipole layers (e.g., a first p-type dipole layer, a second p-type dipole layer, a first n-type dipole layer, and / or a second n-type dipole layer) and increasing the thickness of the dipole layers forms a CFET with multiple threshold voltages (multiple Vt). In other words, when one dipole layer has a first thickness (e.g., a first p-type dipole layer) and another dipole layer has a second thickness (e.g., a second p-type dipole layer) and the first thickness is different from the second thickness, multiple threshold voltages (multiple Vt) are formed.

[0079] Figures 2A to 2U Two cross-sectional views of an electronic device (e.g., a transistor, such as a complementary field-effect transistor (CFET)) according to one or more embodiments are shown. Figures 2A to 2U The CFET shown can be derived from Figure 1A The method 100 shown in the figure is used for manufacturing.

[0080] In some embodiments, during operation 10, an interface layer 270 is deposited on the top surface of the vertically stacked superlattice structure 260 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 10, the interface layer 270 is deposited on the first hGAA structure 215, the intermediate dielectric isolation (MDI) layer 240, and the second hGAA structure 255. In one or more embodiments, the interface layer 270 comprises silicon oxide (SiOx). In one or more embodiments, the interface layer 270 may be formed by etching and forming an oxide on a surface (e.g., the top surface of the vertically stacked superlattice structure 260).

[0081] In some embodiments, during operation 10, a wet chemical process is performed to form interface layer 270. The wet chemical process can be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical process includes a pre-cleaning treatment. In some embodiments, the pre-cleaning treatment includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning treatment includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning treatment includes using diluted hydrofluoric acid (diluted HF), including a dilution greater than 100:1, such as 130:1, to etch away the native oxides on the substrate to form a hydrophobic surface (i.e., interface layer 270).

[0082] In some embodiments, during operation 10, rapid thermal processing (RTP) is used to form interface layer 270. RTP can be any suitable method known to those skilled in the art. In some embodiments, during operation 10, RTP is a thermal oxidation process in which a silicon oxide (SiOx) layer (e.g., interface layer 270) is grown on the top surface of a vertically stacked superlattice structure.

[0083] See Figure 1A and Figure 2B In some embodiments, during operation 12, a high-dielectric-constant dielectric layer 272 is deposited on the interface layer 270 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 12, the high-dielectric-constant dielectric layer 272 is conformally deposited on the interface layer 270 by ALD.

[0084] In some embodiments, the high dielectric constant dielectric layer 272 comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx). In some embodiments, the high dielectric constant dielectric layer 272 comprises hafnium oxide (HfOx).

[0085] See Figure 1A and Figure 2C In some embodiments, during operation 14, a first p-type dipole layer 274 is deposited on the high dielectric constant dielectric layer 272 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, the first p-type dipole layer 274 comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof.

[0086] In some embodiments, during operation 14, depositing the first p-type dipole layer 274 includes pulses of exposing the semiconductor substrate 202 (e.g., the top surface of the high-dielectric-constant dielectric layer 272) to an aluminum-containing precursor and pulses of an oxygen-containing reactant through atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, during operation 14, depositing the first p-type dipole layer 274 includes pulses of exposing the top surface of the high-dielectric-constant dielectric layer 272 to an aluminum-containing precursor and pulses of a nitrogen-containing reactant through atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the semiconductor substrate 202 is cleaned after each pulse.

[0087] In some embodiments, the oxygen-containing reactants include one or more of oxygen (O2), ozone (O3), or water (H2O).

[0088] In some embodiments, the nitrogen-containing reactants include the co-flow of nitrogen gas (N2), ammonia (NH3), hydrazine (N2H4), nitrogen free radicals (N2*) and hydrogen free radicals (H*), the co-flow of nitrogen free radicals (N2*) and hydrogen (H2) gas, or nitrogen free radicals (N2*) and deuterium (H*). 2 One or more of the H) gases in a co-flow.

[0089] In some embodiments, the nitrogen-containing reactant comprises a substituted or unsubstituted alkyl hydrazine. In some embodiments, the alkyl hydrazine comprises a number of carbon atoms ranging from 1 to 6. In one or more embodiments, the alkyl hydrazine is a tertiary butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0090] The first p-type dipole layer 274 can be deposited as a single layer or multiple layers. The first p-type dipole layer 274 can be deposited to a predetermined thickness. In some embodiments, the first p-type dipole layer 274 has a thickness in the range of 3 angstroms to 25 angstroms.

[0091] See Figure 1A and Figure 2D In some embodiments, during operation 16, a first p-type capping layer 276 is deposited on the first p-type dipole layer 274 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 16, the first p-type capping layer 276 is conformally deposited on the first p-type dipole layer 274 by ALD. In some embodiments, the first p-type capping layer 276 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the first p-type capping layer 276 has a thickness ranging from 10 angstroms to 30 angstroms.

[0092] See Figure 1A and Figure 2E In some embodiments, during operation 18, a first protective layer 278 is deposited on a first portion 202-1 of a semiconductor substrate using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, the first protective layer 278 protects a portion of a first p-type capping layer 276 on the first portion 202-1 of the semiconductor substrate. The first protective layer 278 may comprise any suitable material known to those skilled in the art. In some embodiments, the first protective layer 278 comprises a hard mask material. In some embodiments, the first protective layer 278 comprises carbon (C). In some embodiments, the first protective layer 278 comprises spin-coated carbon (C).

[0093] In operation 20, method 100 may include selectively etching the vertically stacked superlattice structure 260 to remove the first protective layer 278 from a first portion 202-1 of the semiconductor substrate, and to remove a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 from a second portion 202-2 of the semiconductor substrate. In one or more embodiments, in operation 20, method 100 includes selective etching to form multiple threshold voltages (multiple Vts) in the CFET. Figure 2F This shows the result after operation 20 etched the vertically stacked superlattice structure 260. Figure 2E A double cross-sectional view of the semiconductor substrate 202.

[0094] The etching process of operation 20 can be any suitable etching process known to those skilled in the art. In some embodiments, the etching process comprises a wet etching process or a dry etching process. In some embodiments, the etching process comprises a wet etching process. In some embodiments, the wet etching process includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, the water (H2O) is deionized water (DI). In some embodiments, the pre-cleaning process includes using a DI:NH4OH ratio in the range of 100:1 (DI:NH4OH) to 5:1 (DI:NH4OH).

[0095] In some embodiments, the pre-cleaning process includes using an SC-1 solution or an SC-2 solution. In one or more embodiments, the SC-1 solution contains one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, the SC-2 solution contains one or more of hydrochloric acid or hydrogen peroxide. It has been advantageously found that using the SC-1 solution or the SC-2 solution in operation 22 selectively etches the first p-type dipole layer (and other layers thereon) without etching a portion of the interface layer.

[0096] It has been found that selectively etching the vertically stacked superlattice structure 260 in operation 20 to remove the first protective layer 278 from the first portion 202-1 of the semiconductor substrate, and removing a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 from the second portion 202-2 of the semiconductor substrate, and increasing the thickness of the dipole layer (e.g., by depositing a second p-type dipole layer 280 in operation 24), advantageously provides a CFET 200 with multiple Vt.

[0097] See Figure 1A and Figure 2G In some embodiments, during operation 22, a second p-type dipole layer 280 is deposited on the first p-type capping layer 276 in the first portion 202-1 and on the high-dielectric-constant dielectric layer 272 using deposition techniques (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 22, the second p-type dipole layer 280 is formed on the first hGAA structure 215, the intermediate dielectric isolation (MDI) layer 240, and the second hGAA structure 255. In one or more embodiments, depositing the second p-type dipole layer 280 during operation 22 comprises the same process as depositing the first p-type dipole layer 274 during operation 14.

[0098] In some embodiments, the second p-type dipole layer 280 comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof. The second p-type dipole layer 280 may be deposited as a single layer or multiple layers. The second p-type dipole layer 280 may be deposited to a predetermined thickness. In some embodiments, the second p-type dipole layer 280 has a thickness ranging from 3 angstroms to 25 angstroms.

[0099] See Figure 1A and Figure 2H In some embodiments, during operation 24, a second p-type capping layer 282 is deposited on the second p-type dipole layer 280 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 24, the second p-type capping layer 282 is conformally deposited on the second p-type dipole layer 280 by ALD. In some embodiments, the second p-type capping layer 282 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the second p-type capping layer 282 has a thickness ranging from 10 angstroms to 30 angstroms.

[0100] See Figure 1A and Figure 2I In some embodiments, during operation 26, a second protective layer 284 is deposited on a first portion 202-1 and a second portion 202-2 of a semiconductor substrate using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, the second protective layer 284 protects a first p-type dipole layer 274, a first p-type capping layer 276, a second p-type dipole layer 280, and a second p-type capping layer 282. The second protective layer 284 may comprise any suitable material known to those skilled in the art. In some embodiments, the second protective layer 284 comprises a hard mask material. In some embodiments, the second protective layer 284 comprises carbon (C). In some embodiments, the second protective layer 284 comprises spin-coated carbon (C).

[0101] See Figure 1A and Figure 2KIn some embodiments, during operation 28, method 100 may include performing a gap-filling process to fill the trench with p-type dipole gap-fill material 286. It has been advantageously found that filling the trench with p-type gap-fill material 286 forms multiple Vts in the same gate trench. In some embodiments, when multiple Vts in the same gate trench are not desired, method 100 does not include performing the gap-filling process of operation 28. In one or more embodiments, each of the p-type dipole gap material 286, the second p-type capping layer 282, and the first p-type capping layer 276 independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In one or more embodiments, each of the p-type dipole gap material 286, the second p-type capping layer 282, and the first p-type capping layer 276 independently comprises the same material.

[0102] In some embodiments, in operation 30, method 100 includes etching the vertically stacked superlattice structure 260 to remove the second protective layer 284 from the first portion 202-1 and the second portion 202-2, and removing a portion of the first p-type capping layer 276, a portion of the first p-type dipole layer 274, a portion of the second p-type capping layer 282, and a portion of the second p-type dipole layer 280 from the third portion 202-3 of the semiconductor substrate. In some embodiments, operation 30 includes the same processing as operation 20.

[0103] See Figure 1A and Figure 2L In some embodiments, at operation 32, method 100 includes selectively etching the vertically stacked superlattice structure 260 to remove the first p-type capping layer 276, the first p-type dipole layer 274, the second p-type capping layer 282, and the second p-type dipole layer 280 to expose a high-dielectric-constant dielectric layer 272 on the second hGAA structure 255. In some embodiments, operation 32 includes the same processing as operation 20 and / or operation 30. In one or more embodiments, method 100 includes selective etching of operation 32 to form multiple threshold voltages (multiple Vt) in the CFET.

[0104] See Figure 1A and Figure 2M In some embodiments, during operation 34, a first n-type dipole layer 290 is deposited on the high-dielectric-constant dielectric layer 272 exposed on the second hGAA structure 255 using deposition techniques (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, the first n-type dipole layer 290 comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

[0105] In some embodiments, during operation 34, depositing the first n-type dipole layer 290 includes pulses of exposing the semiconductor substrate 202 (e.g., the top surface of the exposed high-dielectric-constant dielectric layer 272) to a lanthanum-containing precursor and pulses of an oxygen-containing reactant through atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, during operation 34, depositing the first n-type dipole layer 290 includes pulses of exposing the top surface of the exposed high-dielectric-constant dielectric layer 272 to a lanthanum-containing precursor and pulses of a nitrogen-containing reactant through atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the semiconductor substrate 202 is cleaned after each pulse.

[0106] In some embodiments, the oxygen-containing reactants include one or more of oxygen (O2), ozone (O3), or water (H2O).

[0107] In some embodiments, the nitrogen-containing reactants include the co-flow of nitrogen gas (N2), ammonia (NH3), hydrazine (N2H4), nitrogen free radicals (N2*) and hydrogen free radicals (H*), the co-flow of nitrogen free radicals (N2*) and hydrogen (H2) gas, or nitrogen free radicals (N2*) and deuterium (H*). 2 One or more of the H) gases in a co-flow.

[0108] In some embodiments, the nitrogen-containing reactant comprises a substituted or unsubstituted alkyl hydrazine. In some embodiments, the alkyl hydrazine comprises a number of carbon atoms ranging from 1 to 6. In one or more embodiments, the alkyl hydrazine is a tertiary butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0109] The first n-type dipole layer 290 can be deposited as a single layer or a multilayer film. The first n-type dipole layer 290 can be deposited to a predetermined thickness. In some embodiments, the first n-type dipole layer 290 has a thickness in the range of 3 angstroms to 25 angstroms.

[0110] See Figure 1A and Figure 2NIn some embodiments, at operation 36, a first n-type capping layer 292 is deposited on the first n-type dipole layer 290 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, at operation 36, the first n-type capping layer 292 is conformally deposited on the first n-type dipole layer 290 (on the second hGAA structure 255) by ALD. In some embodiments, the first n-type capping layer 292 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the first n-type capping layer 292 has a thickness in the range of 10 angstroms to 30 angstroms.

[0111] See Figure 1A and Figure 2O In some embodiments, during operation 38, a third protective layer 294 is deposited on a first portion 202-1 of the semiconductor substrate using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, the third protective layer 294 protects a first portion of the first n-type capping layer 292 (and the layer beneath the first n-type capping layer 292). The third protective layer 294 may comprise any suitable material known to those skilled in the art. In some embodiments, the third protective layer 294 comprises a hard mask material. In some embodiments, the third protective layer 294 comprises carbon (C). In some embodiments, the third protective layer 294 comprises spin-coated carbon (C).

[0112] In operation 40, method 100 may include selectively etching the vertically stacked superlattice structure 260 to remove the third protective layer 294 from the first portion 202-1, and removing a portion of the first n-type capping layer 292 and a portion of the first n-type dipole layer 290 from the second portion 202-2 of the semiconductor substrate. In one or more embodiments, method 100 includes selective etching of operation 40 to form multiple threshold voltages (multiple Vts) in the CFET 200. Figure 2P This is shown after operation 40 etching of the vertically stacked superlattice structure 260. Figure 2O A double cross-sectional view of the semiconductor substrate 202.

[0113] See Figure 1A and Figure 2QIn some embodiments, during operation 42, a second n-type dipole layer 296 is deposited on the first portion 202-1 (on the first n-type capping layer 292) and on the high-dielectric-constant dielectric layer 272 using deposition techniques (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 42, the second n-type dipole layer 296 is conformally deposited on the second hGAA structure 255 by ALD. In one or more embodiments, depositing the second n-type dipole layer 296 during operation 42 comprises the same process as depositing the first n-type dipole layer 290 during operation 34.

[0114] In some embodiments, the second n-type dipole layer 296 comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof. The second n-type dipole layer 296 may be deposited as a single layer or multiple layers. The second n-type dipole layer 296 may be deposited to a predetermined thickness. In some embodiments, the second n-type dipole layer 296 has a thickness ranging from 3 angstroms to 25 angstroms.

[0115] See Figure 1A and Figure 2R In some embodiments, during operation 44, a second n-type capping layer 298 is deposited on the second n-type dipole layer 296 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, during operation 44, the second n-type capping layer 298 is conformally deposited on the second n-type dipole layer 296 by ALD. In some embodiments, the second n-type capping layer 298 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the second n-type capping layer 298 has a thickness ranging from 10 angstroms to 30 angstroms.

[0116] See Figure 1A and Figure 2SIn some embodiments, during operation 46, a fourth protective layer 300 is deposited on the first portion 202-1 and the second portion 202-2 of the semiconductor substrate 202 using a deposition technique (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art). In some embodiments, the fourth protective layer 300 protects the second n-type capping layer 298 (and the layer beneath the second n-type capping layer 298). The fourth protective layer 300 may comprise any suitable material known to those skilled in the art. In some embodiments, the fourth protective layer 300 comprises a hard mask material. In some embodiments, the fourth protective layer 300 comprises carbon (C). In some embodiments, the fourth protective layer 300 comprises spin-coated carbon (C).

[0117] See Figure 1A and Figure 2T In operation 48, method 100 may include etching the vertically stacked superlattice structure 260 to remove the fourth protective layer 300 from the first portion 202-1 and the second portion 202-2, and removing a portion of the first p-type capping layer 276, a portion of the first p-type dipole layer 274, a portion of the second p-type capping layer 282, a portion of the second p-type dipole layer 280, a portion of the first n-type capping layer 292, a portion of the first n-type dipole layer 290, a portion of the second n-type capping layer 298, and a portion of the second n-type dipole layer 296 from the third portion 202-3 of the semiconductor substrate. In one or more embodiments, method 100 includes selective etching of operation 48 to form multiple threshold voltages (multiple Vts) in the CFET.

[0118] See also Figure 1A and Figure 2T In some embodiments, during operation 50, method 100 includes annealing the semiconductor substrate 202 (indicated by arrow 302) at a temperature less than or equal to 1000°C to drive atoms from each of the first p-type dipole layer 274, the second p-type dipole layer 280, the first n-type dipole layer 290, and the second n-type dipole layer 296 into the high-dielectric-constant dielectric layer 272 to form the annealed high-dielectric-constant dielectric layer 272' (in Figure 2U (See diagram in Chinese).

[0119] In some embodiments, during operation 50, method 100 includes annealing the semiconductor substrate 202 at a temperature less than or equal to 950°C. In some embodiments, the temperature is in the range of 500°C to 1000°C, including the range of 600°C to 1000°C, the range of 700°C to 1000°C, the range of 750°C to 950°C, or the range of 800°C to 900°C.

[0120] Without being bound by theory, it is considered that annealing the semiconductor substrate 202 in operation 50 drives an increased number of atoms from the dipole layers (e.g., the first p-type dipole layer 274, the second p-type dipole layer 280, the first n-type dipole layer 290, and / or the second n-type dipole layer 296) into the interface between the interface layer 270 and the high-dielectric-constant dielectric layer 272, compared to methods in which annealing does not occur. In one or more embodiments, annealing the semiconductor substrate 202 in operation 50 includes rapid thermal processing (RTP). RTP can be any suitable method known to those skilled in the art. Without being bound by theory, when in operation 50, method 100 includes annealing the semiconductor substrate 202 at a temperature less than or equal to 1000°C to drive atoms from the dipole layers into the interface between the interface layer 270 and the high-dielectric-constant dielectric layer 272, such that the interface between the interface layer 270 and the high-dielectric-constant dielectric layer 272 contains the properties of a dipole layer.

[0121] See Figure 1A and Figure 2U In some embodiments, at operation 52, method 100 includes etching the vertically stacked superlattice structure 260 to remove each of the first p-type dipole layer 274, the first p-type capping layer 276, the second p-type dipole layer 280, the second p-type capping layer 282, the first n-type dipole layer 290, the first n-type capping layer 292, the second n-type dipole layer 296, and the second n-type capping layer 298.

[0122] After operation 52, method 100 may include any post-processing operations known to those skilled in the art for semiconductor manufacturing.

[0123] In one or more embodiments, the CFET may include any suitable number of different dipole layer thicknesses and multiple threshold voltages (multiple Vts). In one or more embodiments, the CFET includes two different dipole layer thicknesses and two multiple threshold voltages (multiple Vts). In one or more embodiments, the CFET includes three different dipole layer thicknesses and three multiple threshold voltages (multiple Vts). In one or more embodiments, the CFET includes four different dipole layer thicknesses and four multiple threshold voltages (multiple Vts).

[0124] Further embodiments of this disclosure relate to electronic devices having multiple CFET regions. In one or more embodiments, the electronic device includes a CFET 200 formed by method 100.

[0125] In some embodiments, electronic devices (e.g., CFETs) 200) comprises: a first complementary field-effect transistor (CFET) region having a first threshold voltage (Vt); a second CFET region having a second Vt; and a third CFET region having a third Vt, each of the first CFET region, the second CFET region, and the third CFET region being formed on a vertically stacked superlattice structure 260 on a semiconductor substrate 202, the vertically stacked superlattice structure 260 comprising a first horizontal gate all-around (hGAA) structure 215 comprising a positive metal-oxide-semiconductor (pMOS) transistor on a top surface 203 of the semiconductor substrate 202; an intermediate dielectric isolation (MDI) layer 240 on a top surface 225 of the first hGAA structure 215; and a second hGAA structure 255 comprising a negative metal-oxide-semiconductor (nMOS) transistor on a top surface 245 of the intermediate dielectric isolation (MDI) layer 240; and an interface layer 270 on each of the first hGAA structure 215, the intermediate dielectric isolation (MDI) layer 240, and the second hGAA structure 255.

[0126] In some embodiments, the first CFET region includes a hafnium oxide (HfOx) layer 272 on the interface layer 270, a first p-type dipole layer 274 on the hafnium oxide (HfOx) layer 272, and a first p-type capping layer 276 on the first p-type dipole layer 274.

[0127] In some embodiments, the second CFET region includes a hafnium oxide (HfOx) layer 272 on the interface layer 270, a first p-type dipole layer 274 on the hafnium oxide (HfOx) layer 272, a first p-type capping layer 276 on the first p-type dipole layer 274, a second p-type dipole layer 280 on a first exposed portion of the hafnium oxide (HfOx) layer 272, and a second p-type capping layer 282 on the second p-type dipole layer 280.

[0128] In some embodiments, the third CFET region includes a hafnium oxide (HfOx) layer 272 on the interface layer 270, a first p-type dipole layer 274 on the hafnium oxide (HfOx) layer 272, a first p-type capping layer 276 on the first p-type dipole layer 274, a second p-type dipole layer 280 on a first exposed portion of the hafnium oxide (HfOx) layer 272, a second p-type capping layer 282 on the second p-type dipole layer 280, a first n-type dipole layer 290 on a high dielectric constant dielectric layer 272 exposed on the second hGAA structure 255, a first n-type capping layer 292 on the first n-type dipole layer 290, a second n-type dipole layer 296 on the second hGAA structure 255, and a second n-type capping layer 298 on the second n-type dipole layer 296.

[0129] In one or more embodiments, each of the first p-type dipole layer 274 and the second p-type dipole layer 280 independently comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof. In some embodiments, each of the first n-type dipole layer 290 and the second n-type dipole layer 296 independently comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

[0130] In some embodiments, each of the first p-type capping layer 276, the second p-type capping layer 282, the first n-type capping layer 292, and the second n-type capping layer 298 independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

[0131] Additional embodiments of this disclosure relate to processing tools (i.e., clustering tools) for forming a CFET and the described methods. In one or more embodiments, the clustering tool includes an integrated processing system such that operation of method 100 is performed without a vacuum interruption. In one or more embodiments, a vacuum interruption exists between at least one operation of method 100.

[0132] The specific arrangement of the processing chambers and components may vary depending on the clustering tools and should not be considered as limiting the scope of this disclosure.

[0133] Embodiments of this disclosure relate to a non-transitory computer-readable medium. In one or more embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform any of the methods described herein. In one or more embodiments, the controller causes the processing chamber to perform the operation of method 100.

[0134] For ease of description, this document uses spatially relative terms (such as "below," "under," "lower," "above," "upper," and the like) to describe the relationship between one element or feature shown in the figures and another element or feature. It will be understood that, in addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of elements in use or operation. For example, if an element in a figure is flipped, an element described as "below" or "under" another element or feature will be oriented "above" that other element or feature. Thus, the exemplary term "below" can encompass both below and above orientations. Elements may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0135] Unless otherwise indicated herein or explicitly denied by the context, the use of the terms “a”, “an”, “the”, and similar references in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) shall be construed as covering both the singular and the plural. Unless otherwise indicated herein, the description of value ranges herein is intended merely as a simplified method independently referring to each individual value falling within that range, and each individual value is incorporated into the specification as if it were independently described herein. Unless otherwise indicated herein or explicitly denied by the context, all methods described herein may be performed in any suitable order. The use of any and all instances or exemplary language (e.g., “such as”) provided herein is merely intended to better illustrate the materials and methods and does not impose any limitation on the scope unless otherwise claimed. The language in the specification should not be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0136] Throughout this specification, references to "an embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic is combined in any suitable manner.

[0137] Although this disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the claims and their equivalents.

Claims

1. A method for forming a complementary field-effect transistor (CFET), the method comprising the steps of: An interface layer is deposited on a vertically stacked superlattice structure on a semiconductor substrate, the vertically stacked superlattice structure comprising a first horizontal gate all-around (hGAA) structure on the top surface of the semiconductor substrate, an intermediate dielectric isolation (MDI) layer on the top surface of the first hGAA structure, and a second hGAA structure on the top surface of the intermediate dielectric isolation (MDI) layer, the interface layer being formed on the first hGAA structure, the intermediate dielectric isolation (MDI) layer, and the second hGAA structure; A high dielectric constant dielectric layer is deposited on the interface layer; A first p-type dipole layer is deposited on the high dielectric constant dielectric layer; A first p-type capping layer is deposited on the first p-type dipole layer; A first protective layer is deposited on a first portion of the semiconductor substrate to protect the first portion of the first p-type capping layer; The vertically stacked superlattice structure is etched to remove the first protective layer from the first portion and a portion of the first p-type capping layer and a portion of the first p-type dipole layer from the second portion of the semiconductor substrate, the first portion having a first threshold voltage (Vt) and the second portion having a second Vt; A second p-type dipole layer is deposited on the first portion and the second portion, the second p-type dipole layer being formed on the first hGAA structure, the intermediate dielectric isolation (MDI) layer, and the second hGAA structure; A second p-type capping layer is deposited on the second p-type dipole layer; A second protective layer is deposited on the first portion and the second portion of the semiconductor substrate to protect the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, and the second p-type capping layer. The vertically stacked superlattice structure is etched to remove the second protective layer from the first and second portions, and a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer are removed from the third portion of the semiconductor substrate. Etch the vertically stacked superlattice structure to remove the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer, and the second p-type dipole layer to expose the high dielectric constant dielectric layer on the second hGAA structure; A first n-type dipole layer is deposited on the high dielectric constant layer exposed on the second hGAA structure; A first n-type capping layer is deposited on the first n-type dipole layer; A third protective layer is deposited on the first portion of the semiconductor substrate to protect the first portion of the first n-type capping layer; The vertically stacked superlattice structure is etched to remove the third protective layer from the first portion, and a portion of the first n-type capping layer and a portion of the first n-type dipole layer are removed from the second portion of the semiconductor substrate; A second n-type dipole layer is deposited on the first portion and the second portion, the second n-type dipole layer being formed on the second hGAA structure; A second n-type capping layer is deposited on the second n-type dipole layer; A fourth protective layer is deposited on the first and second portions of the semiconductor substrate to protect the second n-type capping layer. The vertically stacked superlattice structure is etched to remove the fourth protective layer from the first and second portions, and a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, a portion of the second p-type dipole layer, a portion of the first n-type capping layer, a portion of the first n-type dipole layer, a portion of the second n-type capping layer, and a portion of the second n-type dipole layer are removed from the third portion of the semiconductor substrate. The semiconductor substrate is annealed at a temperature less than or equal to 1000°C to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer into the high dielectric constant layer to form an annealed high dielectric constant layer. as well as The vertically stacked superlattice structure is etched to remove each of the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer.

2. The method according to claim 1, wherein the first hGAA structure is a positive metal-oxide-semiconductor (pMOS) transistor and the second hGAA structure is a negative metal-oxide-semiconductor (nMOS) transistor.

3. The method of claim 1, wherein the intermediate dielectric isolation (MDI) layer has a thickness in the range of 15 nm to 90 nm.

4. The method of claim 1, wherein each of the first hGAA structure and the second hGAA structure independently comprises alternating layers of nanosheet channel layers and nanosheet release layers in the range of 1 to 5 pairs.

5. The method of claim 4, wherein the vertically stacked superlattice structure is fully strained and the nanosheet channel layer is substantially free of defects.

6. The method of claim 1, further comprising the step of: performing a gap-filling process to fill the trenches in the vertically stacked superlattice structure with a p-type dipole filling material before etching the vertically stacked superlattice structure to remove the first p-type capping layer, the first p-type dipole layer, the second p-type capping layer, and the second p-type dipole layer to expose the high-dielectric-constant dielectric layer on the second hGAA structure.

7. The method of claim 1, wherein the interface layer comprises silicon oxide (SiOx).

8. The method according to claim 1, wherein the high dielectric constant dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx).

9. The method of claim 1, wherein one or more of the following operations involve atomic layer deposition (ALD) processes: The interface layer is deposited on the top surface of the vertically stacked superlattice structure; The high dielectric constant dielectric layer is deposited on the interface layer; The first p-type dipole layer is deposited on the high dielectric constant dielectric layer; Deposit the first p-type capping layer on the first p-type dipole layer; The second p-type dipole layer is deposited on the first portion and the second portion; Deposit the second p-type capping layer on the second p-type dipole layer; The first n-type dipole layer is deposited on the exposed top surface of the second hGAA structure; Deposit the first n-type capping layer on the first n-type dipole layer; Deposit the second n-type dipole layer on the first portion and the second portion; or The second n-type capping layer is deposited on the second n-type dipole layer.

10. The method of claim 1, wherein each of the first p-type dipole layer and the second p-type dipole layer independently comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof.

11. The method of claim 10, wherein each of the first p-type dipole layer and the second p-type dipole layer independently has a thickness in the range of 3 angstroms to 25 angstroms.

12. The method of claim 1, wherein each of the first p-type capping layer and the second p-type capping layer independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

13. The method of claim 12, wherein each of the first p-type cover layer and the second p-type cover layer independently has a thickness in the range of 10 angstroms to 30 angstroms.

14. The method of claim 1, wherein each of the first n-type dipole layer and the second n-type dipole layer independently comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

15. The method of claim 14, wherein each of the first n-type dipole layer and the second n-type dipole layer independently has a thickness ranging from 3 angstroms to 25 angstroms.

16. The method of claim 1, wherein each of the first n-type capping layer and the second n-type capping layer independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

17. The method of claim 16, wherein each of the first n-type cover layer and the second n-type cover layer independently has a thickness in the range of 10 angstroms to 30 angstroms.

18. The method of claim 1, wherein each of the first protective layer, the second protective layer, the third protective layer, and the fourth protective layer independently comprises a hard mask material.

19. An electronic device comprising: A first complementary field-effect transistor (CFET) region has a first threshold voltage (Vt); a second CFET region has a second Vt; and a third CFET region has a third Vt. Each of the first CFET region, the second CFET region, and the third CFET region is formed on a vertically stacked superlattice structure on a semiconductor substrate. The vertically stacked superlattice structure includes a first horizontal gate-all-around (hGAA) structure containing a positive metal-oxide-semiconductor (pMOS) transistor on the top surface of the semiconductor substrate; an intermediate dielectric isolation (MDI) layer on the top surface of the first hGAA structure; and a second hGAA structure containing a negative metal-oxide-semiconductor (nMOS) transistor on the top surface of the intermediate dielectric isolation (MDI) layer; and an interface layer on each of the first hGAA structure, the intermediate dielectric isolation (MDI) layer, and the second hGAA structure. The first CFET region includes a hafnium oxide (HfOx) layer on the interface layer, a first p-type dipole layer on the hafnium oxide (HfOx) layer, and a first p-type capping layer on the first p-type dipole layer. The second CFET region includes the hafnium oxide (HfOx) layer on the interface layer, the first p-type dipole layer on the hafnium oxide (HfOx) layer, the first p-type capping layer on the first p-type dipole layer, the second p-type dipole layer, and the second p-type capping layer on the second p-type dipole layer. The third CFET region includes the hafnium oxide (HfOx) layer on the interface layer, the first p-type dipole layer on the hafnium oxide (HfOx) layer, the first p-type capping layer on the first p-type dipole layer, the second p-type dipole layer, the second p-type capping layer on the second p-type dipole layer, the first n-type dipole layer on the high dielectric constant dielectric layer exposed on the second hGAA structure, the first n-type capping layer on the first n-type dipole layer, the second n-type dipole layer on the second hGAA structure, and the second n-type capping layer on the second n-type dipole layer. Each of the first p-type dipole layer and the second p-type dipole layer independently comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof, and each of the first n-type dipole layer and the second n-type dipole layer independently comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

20. The electronic device of claim 19, wherein each of the first p-type capping layer, the second p-type capping layer, the first n-type capping layer, and the second n-type capping layer independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

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