Memory and operation method thereof, memory system and electronic equipment

Abstract

The embodiment of the invention discloses a memory and an operation method thereof, a memory system and electronic equipment, and relates to the technical field of semiconductors. The memory includes a peripheral circuit and a plurality of memory arrays. The peripheral circuit comprises a memory array controller and a first gate, and the memory array controller is connected with the first gate. The plurality of storage arrays are stacked along the thickness direction of the peripheral circuit, and the plurality of storage arrays are respectively connected with the first gate. The plurality of memory arrays includes a first memory array. The memory array controller is used for controlling the first gate to select the first memory array so as to output a driving signal to the selected first memory array. By stacking a plurality of storage arrays, the storage density and the storage capacity of the memory can be greatly increased. By additionally arranging the storage array controller and the first gating device, the multiple storage arrays are independently connected with the first gating device, and selection, independent control management and independent operation of the multiple storage arrays can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a memory and an operating method thereof, a storage system, and an electronic device. BACKGROUND

[0002] Three-dimensional memory, which is usually formed by vertically stacking multiple layers of memory cells, solves the limitations of two-dimensional or planar memory to support higher storage capacity in a smaller space.

[0003] With the continuous evolution of integrated circuit technology, the demand for storage capacity of memory is increasing, and the number of stacked layers of memory cells in three-dimensional memory is also increasing. However, due to the limitations of process etching capability and channel current transmission capability, there is an upper limit to the number of stacked layers of memory cells in three-dimensional memory, which also limits the growth of storage capacity. SUMMARY

[0004] Embodiments of the present application provide a memory and an operating method thereof, a storage system, and an electronic device, which are used to improve the storage capacity of the memory.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a memory is provided, which includes a peripheral circuit and a plurality of memory arrays. The peripheral circuit includes a memory array controller and a first gate, and the memory array controller is connected to the first gate. The plurality of memory arrays are stacked along the thickness direction of the peripheral circuit, and the plurality of memory arrays are respectively connected to the first gate. The plurality of memory arrays includes a first memory array. The memory array controller is configured to control the first gate to select the first memory array to output a driving signal to the selected first memory array.

[0007] The memory provided by some embodiments of the present application can greatly increase the number of vertically stacked memory cells and the storage density and storage capacity of the memory by stacking the plurality of memory arrays along the thickness direction of the peripheral circuit to form a multi-memory array wafer stacking architecture, thereby removing the limitation on the number of stacked gate layers in the stacked structure of the memory array, and further removing the limitations of process etching capability and channel current transmission capability.

[0008] Moreover, the embodiment of the application can realize independent selection and operation of the plurality of memory arrays by adding a memory array controller and a first gate in the peripheral circuit and connecting the plurality of memory arrays to the first gate independently, so as to realize separate control management and driving operation of each memory array. In addition, the transmission path between the driving signal and the selected first memory array can be shortened, and the time delay of the memory and the storage system to which the memory is applied can be reduced.

[0009] In a possible implementation of the first aspect, the number of peripheral circuits is a plurality, and the plurality of peripheral circuits are located on the same side of the plurality of memory arrays. In this way, on the one hand, the arrangement regularity of the peripheral circuits and the memory arrays in the memory can be improved, and the internal space of the memory can be reasonably designed; on the other hand, the memory array controllers of the plurality of peripheral circuits can be provided with a coordination mechanism, so as to facilitate coordinated control, management and driving of the plurality of memory arrays, and improve the performance of the memory.

[0010] In a possible implementation of the first aspect, the two adjacent peripheral circuits are a first peripheral circuit and a second peripheral circuit, and the first peripheral circuit is located between the second peripheral circuit and the plurality of memory arrays. The memory further includes a conductive channel, the conductive channel penetrating through the first peripheral circuit and connecting the output end of the first gate in the first peripheral circuit and the output end of the first gate in the second peripheral circuit. In this way, the connection between the second peripheral circuit and each memory array can also be realized through the conductive channel; and the second peripheral circuit and the first peripheral circuit can share the same set of interconnection structures (including the word line interconnection conductive pillars, the bit line interconnection conductive pillars and the source line interconnection conductive pillars mentioned below), so as to simplify the structure of the memory.

[0011] In a possible implementation of the first aspect, the number of peripheral circuits is a plurality, and the plurality of peripheral circuits are located on opposite sides of the plurality of memory arrays. In this way, on the one hand, the connection between each peripheral circuit and the memory array can be realized, and the reliability and yield of the memory can be improved; on the other hand, the memory array controllers of the plurality of peripheral circuits can be provided with a coordination mechanism, so as to facilitate coordinated control, management and driving of the plurality of memory arrays, and improve the performance of the memory.

[0012] In a possible implementation of the first aspect, the plurality of peripheral circuits comprises: a first peripheral circuit and a second peripheral circuit located at opposite sides of the plurality of memory arrays respectively. The memory further comprises an interconnection via connecting the first memory array and the first gate. The interconnection via connecting the first peripheral circuit and the first memory array of the first gate is connected with the interconnection via connecting the second peripheral circuit and the first memory array of the first gate. In this way, the interconnection via connecting the first peripheral circuit and the first memory array of the first gate and the interconnection via connecting the second peripheral circuit and the first memory array of the first gate can share various types of contacts and various types of interconnection lines in the memory array, which is beneficial to simplify the structure of the memory array.

[0013] In a possible implementation of the first aspect, the number of the first memory arrays is a plurality, and the plurality of peripheral circuits comprises a first peripheral circuit and a second peripheral circuit. The memory array controller of the first peripheral circuit is configured to control the first gate of the first peripheral circuit to select a part of the plurality of first memory arrays to output a driving signal to the selected part of the plurality of first memory arrays. The memory array controller of the second peripheral circuit is configured to control the first gate of the second peripheral circuit to select another part of the plurality of first memory arrays to output a driving signal to the selected another part of the plurality of first memory arrays. In this way, on the one hand, the plurality of types of commands can be supported and executed synchronously in the case that the plurality of types of commands are received by the peripheral circuit; on the other hand, a better command execution path can be selected preferentially according to actual conditions; and on the other hand, the operability of the memory can be ensured in the case that a part of the peripheral circuit fails.

[0014] In a possible implementation of the first aspect, the first memory array comprises: a laminated structure, a word line contact and a word line interconnection line. The laminated structure comprises a plurality of gate layers and a plurality of gate dielectric layers alternately laminated along a thickness direction of the peripheral circuit. The word line contact extends along the thickness direction of the peripheral circuit and is connected with the gate layer. The word line interconnection line extends along a direction perpendicular to the thickness direction of the peripheral circuit and is connected with the word line contact. The memory further comprises a word line interconnection via extending along the thickness direction of the peripheral circuit. The word line interconnection via connects the first gate and the word line interconnection line. In this way, the memory array controller can be used to select and independently operate at least one gate layer in the first memory array.

[0015] In a possible implementation of the first aspect, the first memory array further includes a channel structure, a bit line contact and a bit line interconnection line. The channel structure extends through the stack structure. The bit line contact extends along a thickness direction of the peripheral circuit and is connected with the channel structure. The bit line interconnection line extends along a direction perpendicular to the thickness direction of the peripheral circuit and is connected with the bit line contact. The memory further includes a bit line interconnection via extending along the thickness direction of the peripheral circuit. The bit line interconnection via is connected with the first selector and the bit line interconnection line. In this way, the selection and independent operation of at least one channel structure in the first memory array can be implemented by using the memory array controller.

[0016] In a possible implementation of the first aspect, the first memory array further includes a common source structure, a source line contact and a source line interconnection line. The common source structure is located at one side of the stack structure along the thickness direction of the peripheral circuit. The source line contact extends along the thickness direction of the peripheral circuit and is connected with the common source structure. The source line interconnection line extends along a direction perpendicular to the thickness direction of the peripheral circuit and is connected with the source line contact. The memory further includes a source line interconnection via extending along the thickness direction of the peripheral circuit. The source line interconnection via is connected with the first selector and the source line interconnection line. In this way, the selection and independent operation of the common source structure in the first memory array can be implemented by using the memory array controller.

[0017] In a possible implementation of the first aspect, the word line interconnection via, the bit line interconnection via and the source line interconnection via are arranged staggered with the first memory array. In this way, the word line interconnection via, the bit line interconnection via and the source line interconnection via can be prepared without damaging the memory array, thereby improving the yield of the memory.

[0018] In a possible implementation of the first aspect, the memory further includes a second selector connected between the first selector and the plurality of memory arrays. The second selector is configured to select at least one memory page in the selected first memory array and output a driving signal to the selected at least one memory page. That is, by arranging the first selector, the at least one memory page can be selected from the first memory array for operation after the first memory array is selected, without passing through all the memory arrays, and without synchronously performing the same operation on all the memory arrays, thereby effectively reducing the time delay of the memory and the storage system to which the memory is applied.

[0019] In a second aspect, an operating method of a memory is provided. The operating method is applied to the memory. The memory includes a peripheral circuit and a plurality of memory arrays. The peripheral circuit includes a memory array controller and a first gate. The memory array controller is connected to the first gate. The plurality of memory arrays are stacked along a thickness direction of the peripheral circuit. The plurality of memory arrays are respectively connected to the first gate. The plurality of memory arrays include a first memory array. The operating method includes: receiving, by the peripheral circuit, a data address; controlling, by the memory array controller, the first gate to select the first memory array according to the data address; and outputting, by the first gate, a driving signal to the selected first memory array.

[0020] In a possible implementation of the second aspect, the memory further includes a second gate connected between the first gate and the plurality of memory arrays. Before the first gate outputs the driving signal to the selected first memory array, the operating method further includes: selecting, by the second gate, at least one memory page in the selected first memory array; and receiving, by the second gate, the driving signal and outputting the driving signal to the selected at least one memory page.

[0021] In a possible implementation of the second aspect, the number of the first memory arrays is a plurality, and the number of the peripheral circuits is a plurality. The plurality of peripheral circuits include a first peripheral circuit and a second peripheral circuit. The memory array controller controls the first gate to select the first memory array according to the data address, including: a memory array controller of the first peripheral circuit controls the first gate of the first peripheral circuit to select a part of the plurality of first memory arrays; and a memory array controller of the second peripheral circuit controls the first gate of the second peripheral circuit to select another part of the plurality of first memory arrays.

[0022] In a third aspect, a storage system is provided. The storage system includes a plurality of memories and a memory controller. The memory controller is connected to the plurality of memories. The plurality of memories include a first memory. The first memory includes the memory as described in the different implementations of the first aspect.

[0023] In a possible implementation manner of the third aspect, the plurality of memories further include a second memory, and the second memory includes: a plurality of peripheral circuits and a plurality of memory arrays. The plurality of peripheral circuits are stacked along a thickness direction of the peripheral circuits, and the peripheral circuits include a memory array controller and a first gate. The memory array controller is connected with the first gate. The plurality of peripheral circuits include a first peripheral circuit and a second peripheral circuit adjacent to each other. The plurality of memory arrays are stacked along the thickness direction of the peripheral circuits, and the plurality of memory arrays are located between the first peripheral circuit and the second peripheral circuit. Part of the plurality of memory arrays are respectively connected with the first gate of the first peripheral circuit, and another part of the plurality of memory arrays are respectively connected with the first gate of the second peripheral circuit. The memory array controller of the first peripheral circuit is configured to control the first gate of the first peripheral circuit to select a first memory array from the part of the plurality of memory arrays, so as to output a driving signal to the selected first memory array. The memory array controller of the second peripheral circuit is configured to control the first gate of the second peripheral circuit to select a first memory array from the another part of the plurality of memory arrays, so as to output a driving signal to the selected first memory array.

[0024] In a fourth aspect, an electronic device is provided, and the electronic device includes: a memory system and a circuit board, the memory system being connected with the circuit board. The memory system is the memory system in any of the different implementation manners of the third aspect.

[0025] In a fifth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores computer executable instructions. When the computer executable instructions are executed, the operation method in any of the different implementation manners of the second aspect can be implemented.

[0026] In a sixth aspect, a computer program product is provided, and when the computer program product is run on a computer, the computer is caused to execute the operation method in any of the different implementation manners of the second aspect.

[0027] The technical effects brought by any of the implementation manners of the second aspect to the sixth aspect can refer to the technical effects brought by the different implementation manners of the first aspect, and will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 An architecture diagram of an electronic device provided for an embodiment of the present application;

[0029] Figure 2 Another architecture diagram of an electronic device provided for an embodiment of the present application;

[0030] Figure 3 An architecture diagram of a memory system provided for an embodiment of the present application;

[0031] Figure 4Another architecture diagram of a storage system provided for embodiments of the present application;

[0032] Figure 5 An equivalent circuit diagram of a memory provided for embodiments of the present application;

[0033] Figure 6 A partial structure diagram of a memory provided for embodiments of the present application;

[0034] Figure 7 A structure diagram of a memory array provided for embodiments of the present application;

[0035] Figure 8a A structure diagram of a memory provided for embodiments of the present application;

[0036] Figure 8b Another structure diagram of a memory provided for embodiments of the present application;

[0037] Figure 9 Yet another structure diagram of a memory provided for embodiments of the present application;

[0038] Figure 10 Yet another structure diagram of a memory provided for embodiments of the present application;

[0039] Figure 11 Yet another structure diagram of a memory provided for embodiments of the present application;

[0040] Figure 12a Yet another structure diagram of a memory provided for embodiments of the present application;

[0041] Figure 12b Yet another structure diagram of a memory provided for embodiments of the present application;

[0042] Figure 13 A flow chart of an operation method of a memory array provided for embodiments of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0044] In the description of the present application, "a plurality of" means two or more than two, unless otherwise specified. "At least one" or similar expressions mean any combination of these items, including any combination of single or multiple. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0045] In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", etc. are used to distinguish the same or similar items with basically the same function and role. Those skilled in the art can understand that the terms of "first", "second", etc. do not limit the quantity and execution order, and the terms of "first", "second", etc. also do not mean that they must be different. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. In fact, the words "exemplary" or "for example" are intended to present the relevant concept in a specific manner, for understanding.

[0046] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" can mean that two or more components have direct physical contact or electrical contact. The term "coupling" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other.

[0047] In the embodiments of the present application, "vertical", "parallel" are described respectively to mean approximately vertical and approximately parallel within a certain error range, which can be a range of deviation angle less than or equal to 5°, 8° or 10° respectively relative to absolute vertical and absolute parallel, which is not limited here.

[0048] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in the shape of the drawings relative to the shape of the drawings can be caused by, for example, manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the regions shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, etched regions shown as rectangular will generally have curved features. Therefore, the regions shown in the drawings are essentially schematic, and their shape is not intended to show the actual shape of the regions of the device, and is not intended to limit the scope of the exemplary embodiments.

[0049] In addition, the architecture and scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, as the architecture evolves and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0050] Embodiments of the present application provide an electronic device. The electronic device can be applied to various communication systems or communication protocols, for example, Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0051] The electronic device in embodiments of the present application can be a mobile phone, a pad, a notebook computer, a smart home, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, and the like. The electronic device can also be a handheld device, a computing device, or other processing device connected to a wireless modem having a wireless communication function, a vehicle-mounted device, an electronic device in a 5G network, or an electronic device in a future evolved public land mobile network (PLMN), and the like, and embodiments of the present application are not limited thereto.

[0052] Figure 1 and Figure 2 respectively, are an architecture diagram of an electronic device provided by embodiments of the present application.

[0053] In some examples, as Figure 1As shown, the electronic device 1000 can include a circuit board 100, a bus 200, and a processor 300. The bus 200 is located on and connected with the circuit board 100. The processor 300 is located on the circuit board 100 and connected with the bus 200. The circuit board 100 is, for example, a printed circuit board (PCB), and the processor 300 is, for example, a central processing unit (CPU) or a system on chip (SoC), which can be used to process data, such as processing data of an application program, processing image data, and buffering temporary data. Optionally, the processor 300 can include an application processor (AP) 310 for processing an application program, a graphics processing unit (GPU) 320 for processing image data, and a first RAM 330 for buffering high-speed data. The first RAM 330 can be a static random access memory (SRAM) or an embedded flash (eFlash), etc. The above-mentioned application processor 300, graphics processing unit 320, and first RAM 330 can be integrated in one die or can be respectively arranged in multiple dies.

[0054] With reference to the above Figure 1 , the electronic device 1000 can further include a second RAM 400, which can be connected with the processor 300 through the bus 200. The second RAM 400 can be a DRAM. The second RAM 400 can be used to save volatile data, such as temporary data generated by the above-mentioned system on chip. The storage capacity of the second RAM 400 can be generally larger than that of the first RAM 330, but the reading speed of the second RAM 400 is generally slower than that of the first RAM 330.

[0055] In addition, the electronic device 1000 may also include a communication chip 500 and a power management chip 600, both of which are connected to the processor 300 via a bus 200. The communication chip 500 can be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 600 can be used to supply power to other chips. For example, the processor 300 and the second RAM 400 can be packaged in the same package structure, such as using 2.5D (dimensional) or 3D (three-dimensional) packaging to achieve a faster inter-chip data transfer rate.

[0056] This application also provides a storage system applied to the aforementioned electronic device. In some embodiments, the storage system can serve as... Figure 1 The first RAM330 in the memory can also be used as Figure 1 The second RAM 400 is described above. This application does not limit the application scenarios of the above-described storage system.

[0057] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, the storage system 700 may include a memory 710 and a memory controller 720. The memory controller 720 is connected to the memory 710 and to the processor 300. The memory controller 720 can control the memory 710 and communicate with the processor 300.

[0058] Optionally, the memory controller 720 is used to operate in a low duty cycle environment, such as with a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Optionally, the memory controller 720 can also be used to operate in a high duty cycle environment, such as with a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), where the SSD or eMMC is used, for example, as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays.

[0059] For example, memory controller 720 can be configured to control the operation of memory 710, such as read, erase, and program operations. Memory controller 720 can also be configured to manage various functions related to data stored or to be stored in memory 710, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. Furthermore, memory controller 720 can be configured to process error correction codes (ECC) regarding data read from or written to memory 710. Memory controller 720 can also perform other suitable functions, such as formatting memory 710.

[0060] The memory controller 720 described above can communicate with external devices (e.g., processor 300) according to a specific communication protocol. For example, the memory controller 720 can communicate with external devices through at least one of various interface protocols. These interface protocols include, but are not limited to, USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESD I) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewall protocol, etc.

[0061] The number of the aforementioned memory 710 is one, two, three, or even more. Figure 2 The diagram shows three memory modules 710. Figure 3 and Figure 4 Four memory modules 710 are shown. The memory modules 710 and the memory controller 710 can be integrated into the SSD, which may also include a connector for connecting the SSD to the processor 300.

[0062] For example, such as Figure 3 As shown, in the aforementioned storage system 700, the memory 710 and the memory controller 720 can be two independent chips. The memory 710 and the memory controller 720 can be respectively disposed on a carrier board (e.g., a packaged transistor chain or an adapter board), and the memory 710 and the memory controller 720 are respectively connected to the carrier board. In this way, the memory 710 and the memory controller 720 can transmit signals through metal traces within the carrier board. Based on this, the storage system 700 with the aforementioned memory 710 can be called a stand-a-lone storage system.

[0063] Alternatively, as shown in FIG. 7, the memory 710 and the memory controller 720 can be two independent chips, and the memory 710 and the memory controller 720 can be stacked on the carrier board. The memory 710 and the memory controller 720 can be connected through a through silicon via (TSV) or a redistribution layer (RDL), so that the memory 710 and the memory controller 720 can transmit signals with the carrier board. Similarly, the memory system 700 with the memory 710 can be referred to as a stand-alone memory system.

[0064] Alternatively, as shown in FIG. 7, the memory 710 and the memory controller 720 can be two independent chips, and the memory 710 and the memory controller 720 can be stacked on the carrier board. The memory 710 and the memory controller 720 can be connected through a through silicon via (TSV) or a redistribution layer (RDL), so that the memory 710 and the memory controller 720 can transmit signals with the carrier board. Similarly, the memory system 700 with the memory 710 can be referred to as a stand-alone memory system. Figure 4 Alternatively, as shown in FIG. 7, the memory 710 and the memory controller 720 can be two independent chips, and the memory 710 and the memory controller 720 can be stacked on the carrier board. The memory 710 and the memory controller 720 can be connected through a through silicon via (TSV) or a redistribution layer (RDL), so that the memory 710 and the memory controller 720 can transmit signals with the carrier board. Similarly, the memory system 700 with the memory 710 can be referred to as a stand-alone memory system.

[0065] Alternatively, the memory 710 can be a three-dimensional memory, in which the storage units are vertically stacked to increase the storage density per unit area and accommodate a higher storage capacity in a smaller space. The memory 710 can be of various types, and can include, but is not limited to, a 3D NAND flash memory, a ferroelectric random access memory (FRAM), and the like. In the following, the memory 710 is taken as an example of a 3D NAND flash memory.

[0066] Figure 5 An equivalent circuit diagram of the memory is provided in an embodiment of the present application. As shown in FIG. 8, the memory 710 includes a storage array 1 and a peripheral circuit 2, and the storage array 1 is connected to the peripheral circuit 2. The storage array 1 includes a plurality of storage units MC, each of which can be programmed and store one or more bits of data. At least two storage units MC are connected in series and vertically stacked to form a storage unit string 112; a plurality of storage unit strings 112 can form a storage block 11; and a plurality of storage blocks 11 can form a storage plane. Figure 5 Continuing to refer to FIG. 8, the storage unit MC includes a memory cell 10 and a select gate 20. The memory cell 10 includes a charge storage unit 11 and a control gate 12. The charge storage unit 11 can be a charge trap layer, and the control gate 12 can be a conductive layer. The select gate 20 includes a control gate 21 and a charge storage unit 22. The control gate 21 can be a conductive layer, and the charge storage unit 22 can be a charge trap layer.

[0067] Continuing to refer to FIG. 8, the storage unit MC includes a memory cell 10 and a select gate 20. The memory cell 10 includes a charge storage unit 11 and a control gate 12. The charge storage unit 11 can be a charge trap layer, and the control gate 12 can be a conductive layer. The select gate 20 includes a control gate 21 and a charge storage unit 22. The control gate 21 can be a conductive layer, and the charge storage unit 22 can be a charge trap layer. Figure 5In each memory cell string 112, a first select transistor Q1 is further connected at a source end, and a second select transistor Q2 is further connected at a drain end. The first select transistor Q1 and the second select transistor Q2 can be configured to activate a selected memory cell string 112 during read and program operations. The first select transistors Q1 of a plurality of memory cell strings 112 in a same memory block 11 can be connected with a same source line SL; in other words, the memory block 11 has a common source structure connecting the first select transistors Q1 of the plurality of memory cell strings 112. The second select transistors Q2 of the memory cell strings 112 are respectively connected with corresponding bit lines BL; via the bit lines BL, data can be read or written.

[0068] For example, the memory cell string 112 is further connected with a plurality of word lines WL. Among the plurality of word lines WL, a word line WL connected with each memory page 111 can be referred to as a control gate line, a word line WL connected with each first select transistor Q1 can be referred to as a source side select gate (SSG), and a word line WL connected with each second select transistor Q2 can be referred to as a drain side select gate (DSG).

[0069] Figure 6 A partial structure diagram of a memory is provided for embodiments of the present application. As shown in Figure 6 The channel structure 12 penetrates the stack structure 13 and extends to the source layer 14. The channel structure 12 includes, for example, a channel layer 121 and a storage function layer 122, which can include, in sequence, a tunneling layer 1221, a charge trapping layer 1222, and a blocking layer 1223. The storage function layer 122 is located above the source layer 14, the channel layer 121 extends out of the storage function layer 122, extends to the source layer 14, and contacts the source layer 14 to form a connection. The material of the source layer 14 includes, but is not limited to, polysilicon, and the source layer 14 can be used as the above-mentioned source line, for example.

[0070] The above-mentioned stack structure 13 can include a plurality of gate layers 131 and a plurality of gate dielectric layers 132 alternately stacked along the thickness direction of the source layer 14. In combination Figure 5 and Figure 6 Each gate layer 131 can be used as a word line WL. The portion of the gate layer 131 surrounding the channel structure 12 and the portion of the channel structure 12 opposite the gate layer 131 can constitute a transistor. Specifically, the gate layer 131 closest to the source layer 14 can be used as a source side select gate to constitute a first select transistor Q1; the gate layer 131 farthest from the source layer 14 can be used as a drain side select gate to constitute a second select transistor Q2; and the remaining gate layers 131 can be used as control gate lines to constitute storage transistors (i.e., memory cells MC). In other words, the memory cell string 112 can include the channel structure 12 and the portion of the stack structure 13 surrounding the channel structure 12.

[0071] The peripheral circuit 2 can include any suitable analog, digital, and mixed signal circuitry for implementing operations on the memory array 1 by applying and sensing voltage and / or current signals to and from target memory cells via bit lines BL, word lines WL, source lines SL, etc.

[0072] It can be appreciated that as the number of gate layers 131 in the stack structure 13 increases, the number of memory cells MC included in the memory cell string 112 also increases, which can increase the storage density by multi-value storage and increase the storage capacity of the memory 710. However, in the process of manufacturing the memory array 1, the stack structure 13 needs to be etched to form a deep hole, and then the channel structure 12 is formed in the deep hole. However, due to the limitation of etching capability and channel current transmission capability, there is an upper limit to the number of gate layers 131 in the stack structure 13, i.e., there is an upper limit to the number of stacked memory cells MC, which makes it difficult to further increase the storage density and storage capacity of the memory 710.

[0073] Based on this, some embodiments of the present application provide a memory which can be applied to the above-mentioned storage system 700. Optionally, the memory can be used as the memory 710 in Figure 2 、 Figure 3 or Figure 4 . The application embodiments do not limit the application scenarios of the above-mentioned memory. Among them, Figure 8a 、 Figure 8b 、 Figure 9 、 Figure 10 and Figure 11 respectively illustrate the structure of a memory provided by the application embodiments. In addition, Figure 7 illustrates the structure of a memory array provided by the application embodiments, Figure 8a 、 Figure 8b 、 Figure 9 、 Figure 10 and Figure 11 illustrate the memory array shown in Figure 7 , for example, a cross-sectional structure of the memory array, the cross-sectional line of the cross-sectional structure is parallel to the direction X and parallel to the direction Z.

[0074] As shown in Figure 8a and Figure 8b , the memory 730 includes a peripheral circuit 3 and a memory array 4, and the peripheral circuit 3 and the memory array 4 are connected.

[0075] In some examples, as shown in Figure 8a and Figure 8bAs shown, the peripheral circuit 3 includes a memory array controller 31 and a first selector 32, with the memory array controller 31 connected to the first selector 32. The memory array controller 31 and the first selector 32 can be electrically connected or communicatively coupled (that is, the memory array controller 31 and the first selector 32 cooperate or interact with each other).

[0076] For example, such as Figure 9 As shown, the peripheral circuit 3 also includes a driver 33, which is connected to the memory array controller 31 and to the first selector 32. Optionally, the memory array controller 31 and the driver 33 can be electrically connected or communicatively coupled; the first selector 32 and the driver 33 are, for example, electrically connected. The first selector 32 is, for example, located within the driver 33 and connected to a portion of the circuitry within the driver 33. The number of drivers 33 can be, for example, multiple. For example, there may be two drivers 33; one of these drivers 33 may include, for example, a row decoder or other circuitry, and the other driver 33 may include, for example, a column decoder or other circuitry.

[0077] Furthermore, the peripheral circuit 3 may also include input / output (I / O) circuits, timing controllers, and other circuit structures. Of course, the peripheral circuit 3 may also include more or fewer circuit structures, and this embodiment does not limit this.

[0078] In some instances, such as Figure 7 , Figure 8a and Figure 8b As shown, the above-mentioned memory array 4 includes a stacked structure 41, multiple channel structures 42 and a common source structure 43.

[0079] The stack structure 41 includes a plurality of gate layers 411 and a plurality of gate dielectric layers 412, which are alternately stacked along the thickness direction of the peripheral circuit 3. The thickness direction of the peripheral circuit 3 is, for example, the direction Z shown in the drawings, which can also be referred to as the vertical (or perpendicular) direction. That is, one gate dielectric layer 412 is arranged between two adjacent gate layers 411, and one gate layer 411 is arranged between two adjacent gate dielectric layers 412. The common source structure 43 is located on one side of the stack structure 41 along the thickness direction of the peripheral circuit 3. The common source structure 43 is, for example, used for grounding. The common source structure 43 is insulated from the gate layers 411. For example, one gate dielectric layer 412 is arranged between the common source structure 43 and the gate layer 411 closest to it. The common source structure 43 can be arranged in various ways. For example, the common source structure 43 includes a substrate, and the stack structure 41 is formed on the substrate. For another example, the common source structure 43 is a polysilicon film layer, which can also be referred to as a source layer. The source layer is formed by depositing a polysilicon material on the stack structure 41 after removing the substrate. The plurality of channel structures 42 penetrate the stack structure 41, and the channel layers of the channel structures 42 are in contact with the common source structure 43 to form an electrical connection. The relationship between the gate layers 411, the channel structures 42, and the storage units is described above and will not be repeated here.

[0080] For example, the number of the storage arrays 4 is multiple. Optionally, the number of the storage arrays 4 is two, three, four, or even more. For another example, Figure 8a and Figure 8b The plurality of storage arrays 4 are stacked along the thickness direction of the peripheral circuit 3.

[0081] The plurality of storage arrays 4 are insulated from each other and not directly electrically connected. Different storage arrays 4 in the plurality of storage arrays 4 are independent of each other. For example, the plurality of storage arrays 4 are independently prepared on a plurality of wafer substrates. For another example, at least two storage arrays 4 are synchronously prepared on the same wafer substrate and then formed after cutting. Further, different storage arrays 4 are also independent of each other in operation. For example, during the operation of the peripheral circuit 3 on each storage array 4, the data reading or writing of different storage arrays 4 can be independently performed. Optionally, during the data writing of at least one storage array 4 in the plurality of storage arrays 4, other storage arrays 4 can perform data reading or different data writing.

[0082] The plurality of storage arrays 4 can be bonded to each other by a suitable bonding technique or by a suitable intermediate layer (e.g. an adhesive layer) between adjacent two storage arrays 4. Here, the plurality of storage arrays 4 can have various arrangements, which can be selected according to actual needs.

[0083] Optionally, as shown in Figure 8a and Figure 8b , the storage array 4 has opposite front surface 4a and back surface 4b along the thickness direction of the peripheral circuit 3. The front surface 4a, for example, refers to the lower surface of the storage array 4 shown in Figure 8a and Figure 8b , that is, the side surface of the laminated structure 41 away from the common source structure 43; and the back surface 4b, for example, refers to the upper surface of the storage array 4 shown in Figure 8a and Figure 8b , that is, the side surface of the common source structure 43 away from the laminated structure 41. The adjacent two storage arrays 4 are one of the storage arrays and the second storage array, and the front surface 4a of the one of the storage arrays is bonded to the back surface 4b of the second storage array. That is, the plurality of storage arrays 4 have a unified orientation. For example, in Figure 8a and Figure 8b , the front surface 4a of each storage array 4 is uniformly downward. For another example, the front surface 4a of each storage array 4 is uniformly upward.

[0084] This can improve the regularity of the stacking of the storage arrays 4, facilitate the preparation of the subsequent interconnection conductive pillars, and facilitate the interconnection between the storage arrays 4 and the peripheral circuit 3.

[0085] Optionally, the plurality of storage arrays 4 can also have different orientations. That is, the front surface 4a of at least one of the storage arrays 4 is upward, and the front surface 4a of at least one of the storage arrays 4 is downward. Here, in the case where there are a plurality of storage arrays 4 with the front surface 4a upward, the plurality of storage arrays 4 with the front surface 4a upward can be arranged adjacently, or can be arranged with at least one storage array 4 with the front surface 4a downward in between, and the embodiments of the present application do not limit this.

[0086] In this way, the embodiments of the present application can greatly increase the number of vertically stacked storage units, greatly increase the storage density and storage capacity of the memory 730, without being limited to the number of stacked gate layers 411 in the laminated structure 41, without being limited to the process etching capability and channel current transmission capability. Moreover, this is also conducive to reducing the area occupied by the plurality of storage arrays 4 and reducing the area of the memory 730.

[0087] In some examples, as shown in Figure 8a and Figure 8bAs shown, the plurality of memory arrays 4 are respectively connected with the first gate 32. That is, each memory array 4 is individually connected with the first gate 32, and the interconnection structure (including the word line interconnection via, the bit line interconnection via, the source line interconnection via, etc. mentioned below) between different memory arrays 4 and the first gate 32 is independent of each other, and the first gate 32 and different memory arrays 4 can independently transmit signals (such as the driving signal mentioned below) to each other.

[0088] In some examples, as shown in Figure 8a and Figure 8b As shown, the plurality of memory arrays 4 includes a first memory array 4t. The memory array controller 31 is configured to control the first gate 32 to select the first memory array 4t, so as to output the driving signal to the selected first memory array 4t. For example, the first memory array 4t can also be referred to as a target memory array. The number of the selected first memory array 4t can be one, and correspondingly, the number of the first memory array 4t included in the plurality of memory arrays 4 is one; the number of the selected first memory array 4t can be multiple, and correspondingly, the number of the first memory array 4t included in the plurality of memory arrays 4 is multiple.

[0089] Each memory array 4 in the plurality of memory arrays 4 has a corresponding memory array number. For example, in Figure 8a , the memory array number of the memory array 4 closest to the peripheral circuit 3 is 1#, and the memory array numbers of the plurality of memory arrays 4 along the thickness direction of the peripheral circuit 3 and sequentially away from the peripheral circuit 3 are 2#, …, (n-1) #, n# respectively.

[0090] For example, the memory array controller 31 can generate a selection signal based on the data address issued to the memory system 700, and the selection signal includes the memory array number of at least one memory array 4 (i.e. the first memory array 4t). For example, the selection signal is a digital signal, the number of memory arrays 4 is eight, and the memory array numbers are 1#, 2#, …, 7#, 8# respectively; if the selection signal is 000, the corresponding memory array 4 with the memory array number 1# (i.e. the memory array number of the first memory array 4t is 1#); if the selection signal is 011, the corresponding memory array 4 with the memory array number 4# (i.e. the memory array number of the first memory array 4t is 4#).

[0091] For example, part of the circuit structure in the peripheral circuit 3 can decode the selection signal and then transmit the decoding result to the first gate 32. At this time, the first gate 32 can selectively transmit the driving signal to the selected first storage array 4t and selectively shut down the path between the peripheral circuit 3 and the remaining storage arrays 4 under the control of the decoding result, so as to independently operate (for example, data writing, reading or erasing) the selected first storage array 4t. Optionally, the first gate 32 includes a plurality of gate transistors. Of course, the first gate 32 can also include other structures.

[0092] Therefore, the memory 730 provided by some embodiments of the present application can remove the limitation of the number of stacked gate layers 411 of the stacked structure 41 in the storage array 4 by stacking a plurality of storage arrays 4 along the thickness direction of the peripheral circuit 3, so that the memory 730 adopts a multi-array wafer stacked architecture, thereby greatly increasing the number of vertically stacked storage units and the storage density and storage capacity of the memory 730.

[0093] Moreover, by adding the storage array controller 31 and the first gate 32 in the peripheral circuit 3 and connecting the plurality of storage arrays 4 to the first gate 32 independently, the storage array controller 31 and the first gate 32 can be used to independently select and operate the plurality of storage arrays 4, to realize the independent control and driving operation of each storage array 4 and the normal operation of the memory 730. In addition, this can shorten the transmission path of the driving signal between the peripheral circuit 3 and the selected first storage array 4t, and reduce the time delay of the memory 730 and the storage system 700 to which the memory 730 is applied.

[0094] In some embodiments, as shown in Figure 9 The memory 730 further includes a second gate 331, for example, in the driver 33. The second gate 331 is connected between the first gate 32 and the plurality of storage arrays 4. For example, the second gate 331 is used to select at least one storage page in the selected first storage array 4t and output the driving signal to the selected at least one storage page.

[0095] That is, the second strobe 331 can selectively connect the first strobe 32 and at least one selected storage page in the selected first storage array 4t, and selectively shut off the path between the first strobe 32 and the remaining storage pages in the selected first storage array 4t. The drive signal output by the first strobe 32 is first transmitted to the second strobe 331, and then selectively output by the second strobe 331 to the at least one selected storage page in the selected first storage array 4t.

[0096] It can be understood that, in the case of operating the storage array 1 by the peripheral circuit 2, the format of the data address issued to the storage system 700 is as shown in Table 1: Figure 5

[0097] Table 1

[0098]

[0099] Specifically, the memory controller 720 can determine the target storage system according to the storage system number in the data address, and determine the target memory in the storage system, and then transmit the data address to the peripheral circuit 2 of the target memory; the peripheral circuit 2 can sequentially determine the target storage surface, the target storage block and the target storage page in the target memory according to the data address; then, the peripheral circuit 2 can operate the target storage page.

[0100] In some embodiments of the present application, in the case of operating the storage array 1 by the peripheral circuit 2, the format of the data address issued to the storage system 700 is as shown in Table 1: Figure 8a Figure 8b In the storage 730 shown in the storage 730, in the case of operating the storage array 4 by the peripheral circuit 3, the format of the data address issued to the storage system 700 is as shown in Table 2:

[0101] Table 2

[0102]

[0103] Specifically, the memory controller 720 can determine the target storage system according to the storage system number in the data address, and determine the target memory in the storage system, and then transmit the data address to the peripheral circuit 3 of the target memory; the storage array controller 31 in the peripheral circuit 3 can sequentially determine the target storage surface, the target storage block and the target storage page in the target storage array (i.e. the first storage array 4t) in the target memory according to the data address, and the driver 33 in the peripheral circuit 3 can cooperate with the storage array controller 31; then, the circuit structure (including but not limited to the second strobe 331) in the peripheral circuit 3 can operate the target storage page.

[0104] Compared with Figure 5 ​​The storage array number is newly added in the data address format in the scheme provided by the embodiments of the present application, so that the storage array controller 31 can identify each storage array 4.

[0105] That is, by stacking the plurality of storage arrays 4 and arranging the first gate 32 and the storage array controller 31, the embodiments of the present application can effectively realize the selection and independent operation of each storage array 4 by using the storage array controller 31 and the first gate 32. In this way, in the process of operating the target storage page (i.e., the selected at least one storage page in the selected first storage array 4t), the driving signal can be directly transmitted to the target storage page without passing through the remaining storage arrays 4, and the remaining storage arrays 4 do not need to be synchronously operated in the same way, which can effectively reduce the time delay of the memory 730 and the storage system 700 to which the memory 730 is applied.

[0106] The arrangement of the peripheral circuit 3 can be selected according to actual needs, and different arrangement modes of the peripheral circuit 3 will be described below with reference to the accompanying drawings. Of course, the arrangement mode of the peripheral circuit 3 is not limited to the several modes shown in the accompanying drawings.

[0107] In some possible embodiments, as shown in Figure 8a and Figure 8b , the number of peripheral circuits 3 is one. In this case, the peripheral circuit 3 can select a first storage array 4t from the plurality of storage arrays 4 and independently write data or read data in the first storage array 4t.

[0108] For example, as shown in Figure 8a and Figure 8b , the peripheral circuit 3 is located on one side of the plurality of storage arrays 4 along the thickness direction of the peripheral circuit 3. For example, the orthographic projection of the peripheral circuit 3 on a reference plane partially overlaps the orthographic projection of each storage array 4 on the reference plane. Further, the orthographic projection of each storage array 4 on the reference plane is located in the orthographic projection range of the peripheral circuit 3 on the reference plane, for example. The reference plane is perpendicular to the thickness direction of the peripheral circuit 3.

[0109] In other possible embodiments, as shown in Figure 10 and Figure 11 , the number of peripheral circuits 3 is multiple, and each peripheral circuit 3 is independently connected to the plurality of storage arrays 4. Alternatively, the number of peripheral circuits 3 can be two, three or even more. In this case, Figure 10 and Figure 11The number of the peripheral circuits 3 is two in the illustration. In this case, a coordination mechanism is provided between the storage array controllers 31 of the plurality of peripheral circuits 3, and the plurality of peripheral circuits 3 can coordinate to control, manage and drive the plurality of storage arrays 4. For example, each peripheral circuit 3 can control, manage and drive a different storage array 4, so as to realize efficient operation of the plurality of storage arrays 4 and improve the performance of the memory 730.

[0110] In some examples, the number of the first storage arrays 4t is a plurality. Optionally, the number of the first storage arrays 4t can be two, three or even more. In addition, the plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b.

[0111] The storage array controller 31 of the first peripheral circuit 3a is configured to control the first gate 32 of the first peripheral circuit 3a to select a part of the plurality of first storage arrays 4t to output a driving signal to the selected part of the plurality of first storage arrays 4t. The storage array controller 31 of the second peripheral circuit 3b is configured to control the first gate 32 of the second peripheral circuit 3b to select another part of the plurality of first storage arrays 4t to output a driving signal to the selected another part of the plurality of first storage arrays 4t. That is, the storage array controller 31 of the first peripheral circuit 3a and the storage array controller 31 of the second peripheral circuit 3b can independently select different first storage arrays 4t.

[0112] For example, when the memory 730 receives a plurality of types of commands (for example, also including a data erase command, etc.) at the same time, such as reading data from the first storage array 4t numbered 2# and writing data into the first storage array 4t numbered 3#, the storage array controller 31 in the first peripheral circuit 3a and the storage array controller 31 in the second peripheral circuit 3b can be coordinated to perform the reading operation on the data in the first storage array 4t numbered 2# by one of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the first peripheral circuit 3a) at the same time as performing the data writing operation on the first storage array 4t numbered 3# by the other of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the second peripheral circuit 3b).

[0113] That is, by providing the plurality of peripheral circuits 3, the memory 730 can support the synchronous execution of a plurality of types of commands, thereby improving the performance of the memory 730.

[0114] For example, in the case of a large amount of data writing or data reading in the memory 730, the storage array controllers 31 in the first peripheral circuit 3a and the storage array controllers 31 in the second peripheral circuit 3b can be cooperatively processed, so that one of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the first peripheral circuit 3a) can concentrate on processing data writing or reading operations of a part of the storage arrays 4 (for example, storage arrays numbered 1#, 2#, …, or 1#, 3#, …, (2n-1)#), and the other of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the second peripheral circuit 3b) can concentrate on processing data writing or reading operations of another part of the storage arrays 4 (for example, storage arrays numbered n#, (n-1)#, …, or 2#, 4#, …, 2n#).

[0115] That is, by providing multiple peripheral circuits 3, the memory 730 can preferentially select a better command execution path, thereby improving the performance of the memory 730.

[0116] For example, in the case of a failure of one of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the first peripheral circuit 3a) and the inability to work, the storage array controllers 31 in the first peripheral circuit 3a and the storage array controllers 31 in the second peripheral circuit 3b can be cooperatively processed, so that the other of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the second peripheral circuit 3b) manages the operations of the multiple storage arrays 4.

[0117] That is, by providing multiple peripheral circuits 3, the availability of the memory 730 can be ensured, thereby improving the safety and reliability of the memory 730.

[0118] The arrangement mode between the multiple peripheral circuits 3 and the multiple storage arrays 4 can include various modes, which can be selected according to actual needs.

[0119] In some embodiments, as shown in Figure 10 For example, the multiple peripheral circuits 3 are located on the same side of the multiple storage arrays 4 along the thickness direction of the peripheral circuit 3. For example, the orthographic projections of the multiple peripheral circuits 3 on the reference plane coincide with each other. Further, the orthographic projections of the storage arrays 4 on the reference plane are located within the orthographic projection range of the peripheral circuit 3 on the reference plane.

[0120] In this way, the arrangement regularity of the peripheral circuit 3 and the storage array 4 in the memory 730 can be improved, and the internal space of the memory 730 can be reasonably designed.

[0121] Continuing to refer to Figure 10The memory 730 further includes a plurality of conductive vias 5, for example, the number of which can be determined according to the number of the memory arrays 4 and the number of functional structures in the memory arrays 4. The functional structures in the memory arrays 4 can include, for example, the gate layer 411, the channel structure 42, the common source structure 43, and the like. Optionally, the conductive vias 5 include through silicon vias (TSVs).

[0122] As shown in Figure 10 the plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b, wherein the first peripheral circuit 3a and the second peripheral circuit 3b are adjacently arranged, and the first peripheral circuit 3a is located between the second peripheral circuit 3b and the plurality of memory arrays 4. The conductive vias 5 pass through the first peripheral circuit 3a and connect the output end of the first gate 32 in the first peripheral circuit 3a and the output end of the first gate 32 in the second peripheral circuit 3b.

[0123] At this time, the driving signal output by the output end of the first gate 32 in the second peripheral circuit 3b can be transmitted to the selected first memory array 4t through the output end of the first gate 32 in the first peripheral circuit 3a without flowing through the first gate 32 in the first peripheral circuit 3a.

[0124] In this way, the connection between the second peripheral circuit 3b and each memory array 4 can also be realized through the conductive vias 5, thereby realizing the independent connection between each peripheral circuit 3b and the memory array 4. Moreover, the second peripheral circuit 3b can share the same set of interconnection structures (including the word line interconnection vias, the bit line interconnection vias, the source line interconnection vias, and the like mentioned below) with the first peripheral circuit 3a, and thus a set of interconnection structures can be shared by the plurality of peripheral circuits 3, which can reduce the arrangement of the interconnection structures, facilitate the simplification of the structure of the memory 730, and reduce the cost of the memory 730.

[0125] In other embodiments, as shown in Figure 11 the plurality of peripheral circuits 3 are respectively located on opposite sides of the plurality of memory arrays 4 along the thickness direction of the peripheral circuit 3. The number of the peripheral circuits 3 located on the opposite sides of the plurality of memory arrays 4 can be the same or different. For example, the orthographic projections of the plurality of peripheral circuits 3 on the reference plane are coincident. Further, the orthographic projections of the memory arrays 4 on the reference plane are, for example, located within the orthographic projection range of the peripheral circuit 3 on the reference plane.

[0126] In this way, the connection between each peripheral circuit 3 and the memory array 4 can be realized, which is conducive to improving the reliability and yield of the memory 730.

[0127] Continuing to refer to Figure 11The memory 730 further includes a plurality of interconnect vias 6, which can be in accordance with the number of memory arrays 4 and the number of functional structures in the memory arrays 4. For example, the interconnect vias 6 include word line interconnect vias, bit line interconnect vias, and source line interconnect vias, as will be described in more detail below. The interconnect vias 6 connect the first memory array 4t and the first gate 32.

[0128] As shown in FIG. 3A, the plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b, which are located on opposite sides of the plurality of memory arrays 4. The interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the first peripheral circuit 3a are connected to the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the second peripheral circuit 3b. Figure 11

[0129] Optionally, as shown in FIG. 3B, the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the first peripheral circuit 3a are located below the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the second peripheral circuit 3b, and the two form a continuous columnar structure along the thickness direction of the peripheral circuit 3. Alternatively, the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the first peripheral circuit 3a and the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the second peripheral circuit 3b can be staggered, and then connected by an interconnect layer. Figure 11 Figure 11 For the sake of clarity, the interconnect vias 6 are shown in the same figure to show the interconnection between the first peripheral circuit 3a, the second peripheral circuit 3b, and the first memory array 4t.

[0130] For example, the material of the interconnect vias 6 includes a conductive material, which includes but is not limited to tungsten, aluminum, copper, cobalt, or any combination thereof. In this way, the interconnect vias 6 can be used to electrically connect the first gate 32 and the first memory array 4t, and signals in the first peripheral circuit 3a and / or the second peripheral circuit 3b can be transmitted to the corresponding first memory array 4t through the interconnect vias 6.

[0131] In this way, the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the first peripheral circuit 3a and the interconnect vias 6 connecting the first gate 32 and the first memory array 4t of the second peripheral circuit 3b can share various types of contacts and various types of interconnect lines in the memory array, which is conducive to simplifying the structure of the memory array.

[0132] ​​The type of the interconnection via 6 can be various, depending on the structure of the memory array 4. The type of the interconnection via 6 will be described below with reference to the accompanying drawings, and by way of example with respect to a first memory array 4t of the plurality of memory arrays 4.

[0133] In some embodiments, in combination with Figure 7 and Figure 8a The first memory array 4t comprises a stack structure 41. With respect to the stack structure 41, reference can be made to the above description, which will not be repeated here. Further, the first memory array 4t further comprises word line contacts 44 extending along the thickness direction of the peripheral circuit 3, and word line interconnection lines 45 extending along a direction perpendicular to the thickness direction of the peripheral circuit 3, such as the direction X shown in the accompanying drawings. The word line contacts 44 are connected to the gate layers 411 at one end of the common source structure 43, and the word line contacts 44 are connected to one end of the word line interconnection lines 45 at the other end of the common source structure 43.

[0134] The number of the word line contacts 44 and the word line interconnection lines 45 is, for example, plural. Each of the gate layers 411 in the stack structure 41 is connected to a word line contact 44, and each of the word line contacts 44 is connected to a word line interconnection line 45.

[0135] In this case, the interconnection via 6 comprises a word line interconnection via 61 extending along the thickness direction of the peripheral circuit 3, and the word line interconnection via 61 is connected to the first gate 32 and the word line interconnection line 45. For example, the number of the word line interconnection via 61 is plural, and the plurality of word line interconnection vias 61 and the plurality of word line interconnection lines 45 can be connected one-to-one. For example, one end of each of the word line interconnection vias 61 is connected to the first gate 32, and the other end of each of the word line interconnection vias 61 is connected to the corresponding word line interconnection line 45.

[0136] Optionally, when the number of the peripheral circuit 3 is one or more, and each of the peripheral circuit 3 is located at one side of the plurality of memory arrays 4, the height (i.e. the dimension in the thickness direction of the peripheral circuit 3) of different word line interconnection vias 61 can be the same or different. Figure 10 In the case of the different word line interconnection vias 61 having different heights, the height of each of the word line interconnection vias 61 is, for example, equal to the minimum spacing between the word line interconnection line 45 and the peripheral circuit 3 connected by the word line interconnection via 61.

[0137] Optionally, when the number of the peripheral circuit 3 is plural, and each of the peripheral circuit 3 is located at opposite sides of the plurality of memory arrays 4, as shown in Figure 11As shown, each word line interconnection via 61 is located between a first peripheral circuit 3a and a second peripheral circuit 3b, and the first peripheral circuit 3a and the second peripheral circuit 3b can be connected to the same word line interconnection line 45 through the word line interconnection via 61. Moreover, the two word line interconnection vias 61 connected to the same word line interconnection line 45 are connected to each other.

[0138] For example, as shown in FIG. 1, the two word line interconnection vias 61 connected to the same word line interconnection line 45 are in an integrated structure. Figure 11 As shown, at least two word line interconnection vias 61 connected to the same word line interconnection line 45 are in an integrated structure; and at least two word line interconnection vias 61 connected to the same word line interconnection line 45 are connected through an interconnection layer. Figure 11 In order to show the word line interconnection vias 61 connected to the word line interconnection line 45, the part of the word line interconnection line 45 and the word line interconnection via 61 that are not electrically connected to each other are crossed, but this does not limit the arrangement of the word line interconnection line 45 and the word line interconnection via 61.

[0139] By arranging the word line interconnection via 61 and connecting each word line interconnection via 61 to the corresponding first storage array 4t through the corresponding word line interconnection line 45, the word line contact 44, and the corresponding first storage array 4t, the driving signal can be transmitted to the selected gate layer 411 in the selected first storage array 4t independently, instead of being transmitted to the gate layer 411 with the same serial number in each storage array 4 synchronously. In this way, the storage array controller 31 can be used to select and independently operate at least one gate layer 411 in the first storage array 4t.

[0140] Further, in some embodiments, in combination with Figure 7 and Figure 8b , the first storage array 4t further comprises a channel structure 42. For the channel structure 42, please refer to the relevant description above, which will not be repeated here. Further, the first storage array 4t further comprises a bit line contact 46 and a bit line interconnection line 47, the bit line contact 46 extends along the thickness direction of the peripheral circuit 3, and the bit line interconnection line 47 extends along the direction perpendicular to the thickness direction of the peripheral circuit 3, such as the direction X shown in the drawings. Moreover, the bit line contact 46 connected to the channel structure 42 at one end of the common source structure 43, and the bit line contact 46 connected to one end of the bit line interconnection line 47 at the other end of the common source structure 43.

[0141] The number of the above-mentioned bit line contact 46 and bit line interconnection line 47 is, for example, multiple. Each channel structure 42 is connected to a bit line contact 46, and each bit line contact 46 is connected to a bit line interconnection line 47, for example, in combination with Figure 7 and Figure 8b At least two channel structures 42 arranged along the direction Y share a bit line interconnection line 47.

[0142] In this case, the above-mentioned interconnection conductive pillars 6 include bit line interconnection conductive pillars 62 extending in the thickness direction of the peripheral circuit 3, and the bit line interconnection conductive pillars 62 connect the first gate 32 and the bit line interconnection lines 47. For example, the number of the bit line interconnection conductive pillars 62 is plural, and the bit line interconnection conductive pillars 62 and the bit line interconnection lines 47 can be connected in one-to-one correspondence. For example, one end of each of the bit line interconnection conductive pillars 62 is connected to the first gate 32, and the other end of each of the bit line interconnection conductive pillars 62 is connected to the corresponding bit line interconnection line 47.

[0143] Here, in the case where the number of the peripheral circuits 3 is one or more, the arrangement between the bit line interconnection conductive pillars 62 and the peripheral circuit 3 and the like can be seen in the arrangement between the word line interconnection conductive pillars 61 and the peripheral circuit 3 and the like described above, and will not be described here.

[0144] By providing the bit line interconnection conductive pillars 62 and connecting each of the bit line interconnection conductive pillars 62 to the corresponding first memory array 4t via the corresponding bit line interconnection line 47, the bit line contact 46, and the corresponding first memory array 4t, the drive signal can be transmitted to the selected channel structure 42 in the selected first memory array 4t independently, rather than being transmitted to the channel structures 42 having the same serial number in each of the memory arrays 4 simultaneously. Thus, the selection and independent operation of at least one channel structure 42 in the first memory array 4t can be achieved by the memory array controller 31.

[0145] Further, in some embodiments, in combination with Figure 7 and Figure 8b , the first memory array 4t further includes a common source structure 43. Regarding the common source structure 43, reference can be made to the related description above, and will not be described here. Further, the first memory array 4t further includes a source line contact 48 extending in the thickness direction of the peripheral circuit 3 and a source line interconnection line 49 extending in a direction perpendicular to the thickness direction of the peripheral circuit 3 (for example, the direction X shown in the drawings). One end of the source line contact 48 is connected to the common source structure 43, and the other end of the source line contact 48 away from the common source structure 43 is connected to one end of the source line interconnection line 49.

[0146] The number of the above-mentioned source line contact 48 and the source line interconnection line 49 is, for example, plural or one. In the case where a plurality of memory blocks in the first memory array 4t share the common source structure 43, the number of the above-mentioned source line contact 48 and the source line interconnection line 49 is, for example, one.

[0147] In this case, the interconnection via 6 includes a source line interconnection via 63 extending along the thickness direction of the peripheral circuit 3, and the source line interconnection via 63 connects the first selector 32 and the source line interconnection line 49. For example, the number of the source line interconnection via 63 can be one or multiple, which can be determined according to whether multiple memory blocks in the first memory array 4t share the common source structure 43. For example, one end of each source line interconnection via 63 is connected to the first selector 32, and the other end of each source line interconnection via 63 is connected to the corresponding source line interconnection line 49.

[0148] Here, in the case where the number of the peripheral circuit 3 is one or multiple, the arrangement between the source line interconnection via 63 and the peripheral circuit 3 and other structures can refer to the arrangement between the word line interconnection via 61 and the peripheral circuit 3 and other structures, which will not be described herein.

[0149] By arranging the source line interconnection via 63 and connecting each source line interconnection via 63 to the corresponding first memory array 4t through the corresponding source line interconnection line 49 and source line contact 48, the driving signal can be transmitted to the selected common source structure 43 in the selected first memory array 4t independently, instead of being transmitted to the common source structure 43 with the same serial number in each memory array 4 synchronously. In this way, the selection and independent operation of the common source structure 43 in the first memory array 4t can be realized by the memory array controller 31.

[0150] In combination with Figure 8a and Figure 8b , the word line interconnection via 61, the bit line interconnection via 62, and the source line interconnection via 63 are arranged away from the first memory array 4t. That is, the orthogonal projection of the word line interconnection via 61, the bit line interconnection via 62, and the source line interconnection via 63 on a reference plane does not overlap with the orthogonal projection of the first memory array 4t on the reference plane.

[0151] In this way, in the process of manufacturing the word line interconnection via 61, the bit line interconnection via 62, and the source line interconnection via 63, the memory array 4 can be prevented from being damaged, and the yield of the memory 730 can be improved.

[0152] Some embodiments of the present application also provide a memory, which can be applied to the above-mentioned storage system 700. Optionally, the memory can be used as the memory 710 in Figure 2 , Figure 3 or Figure 4 . The application embodiments do not limit the application scenarios of the above-mentioned memory. Among them, Figure 12a and Figure 12b respectively illustrate the structure diagram of a memory provided by the application embodiments,Figure 12a and Figure 12b the storage array shown in Figure 7 a cross-sectional structure of the storage array, the cross-sectional line of which is parallel to the direction X and parallel to the direction Z.

[0153] As shown in Figure 12a and Figure 12b the memory 740 includes a plurality of peripheral circuits 3 and a plurality of storage arrays 4, and the plurality of peripheral circuits 3 and the plurality of storage arrays 4 are stacked in the thickness direction of the peripheral circuit 3.

[0154] Optionally, in the present embodiment, the structure of the peripheral circuit 3 and the structure of the storage array 4 are the same as the structure of the peripheral circuit 3 and the structure of the storage array 4 in the memory 730 mentioned in any one of the above-mentioned embodiments, which will not be described here again.

[0155] In some examples, as shown in Figure 12a and Figure 12b the above-mentioned plurality of peripheral circuits 3 includes adjacent first peripheral circuit 3a and second peripheral circuit 3b, and the above-mentioned plurality of storage arrays 4 is located between the first peripheral circuit 3a and the second peripheral circuit 3b. Among them, a part of the plurality of storage arrays 4 are respectively connected with the first gate 32 of the first peripheral circuit 3a, and another part of the plurality of storage arrays 4 are respectively connected with the first gate 32 of the second peripheral circuit 3b.

[0156] Optionally, the interconnection mode between the first peripheral circuit 3a and a part of the plurality of storage arrays 4, and the interconnection mode between the second peripheral circuit 3b and another part of the plurality of storage arrays 4 are the same. And the interconnection mode and the required interconnection structure are the same as the interconnection mode and the interconnection structure between the peripheral circuit 3 and the storage array 4 in the memory 730 mentioned in any one of the above-mentioned embodiments. Here will not be described again.

[0157] In some examples, the storage array controller 31 of the first peripheral circuit 3a is configured to control the first gate 32 of the first peripheral circuit 3a to select a first storage array 4t from a part of the plurality of storage arrays 4, so as to output a driving signal to the selected first storage array 4t. The storage array controller 31 of the second peripheral circuit 3b is configured to control the first gate 32 of the second peripheral circuit 3b to select a first storage array 4t from another part of the plurality of storage arrays 4, so as to output a driving signal to the selected first storage array 4t.

[0158] In other words, the first peripheral circuit 3a can select and operate independently a portion of the memory array 4 it is connected to, and the second peripheral circuit 3b can select and operate independently another portion of the memory array 4 it is connected to.

[0159] This allows for a significant increase in the number of vertically stacked memory cells using multiple memory arrays 4, thereby greatly increasing the storage density and capacity of the memory 740 while ensuring its normal operation. Furthermore, this reduces the latency of the memory 740 and the associated storage system 700.

[0160] In the storage system 700 provided in this application embodiment, the number of memories is multiple. These multiple memories include a first memory, which can be one or more. The first memory can be the memory 730 described in any of the above embodiments. Alternatively, the first memory can be the memory 740 described in any of the above embodiments.

[0161] Optionally, if the first memory included in the plurality of memories in the storage system 700 is memory 730, the plurality of memories may further include a second memory. The number of second memories may be one or more. The second memory may, for example, be memory 740 as described in any of the above embodiments.

[0162] Some embodiments of this application also provide a method for operating a memory, which can be applied to the memory 730 described in any of the above embodiments. Of course, this method can also be applied to the memory 740 described in any of the above embodiments. This application provides an illustrative example using the application of this method to the memory 730. Regarding the peripheral circuits 3 and the storage array 4 included in the memory 730 to which the method is applied, please refer to the relevant descriptions above, which will not be repeated here.

[0163] in, Figure 13 A flowchart illustrating a method for operating a memory is provided. It should be understood that... Figure 13 The steps shown are not exclusive; more steps can be taken at other times. Figure 13 Other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figure 13 The execution is performed in the order shown.

[0164] The following is combined with Figures 8a-11 This provides an illustrative explanation of how the memory is operated. For example... Figure 13 As shown, the operation methods include: S100-S300.

[0165] S100, the peripheral circuit 3 receives a data address.

[0166] The data address is, for example, a digital signal, and includes a storage array number of a first storage array 4t in the plurality of storage arrays 4. Further, the data address can also include, for example, a storage surface number of one or more storage surfaces in the first storage array 4t, and a storage block number of one or more storage blocks in the one or more storage surfaces. Further, the data address can also include a storage page number of one or more storage pages in the one or more storage blocks.

[0167] For example, in the process of receiving the data address, the peripheral circuit 3 also receives a command. The type of the command includes a plurality of,

[0168] For example, the command includes at least one of a data read command, a data write command, and a data erase command. Alternatively, the command received by the peripheral circuit 3 can include only the data read command, or can include both the data read command and the data write command.

[0169] S200, the storage array controller 31 controls the first selector 32 to select the first storage array 4t according to the data address.

[0170] For example, the storage array controller 31 can generate a selection signal based on the data address, and the selection signal includes a storage array number of at least one storage array 4 (i.e. the first storage array 4t). For example, the selection signal is a digital signal.

[0171] The first selector 32 includes a plurality of selection transistors. Of course, the first selector 32 can also include other structures. Here, "selecting" means, for example, that the first selector 32 can turn on a path between the selected first storage array 4t and the peripheral circuit 3 (e.g. a driver in the peripheral circuit 3).

[0172] S300, the first selector 32 outputs a driving signal to the selected first storage array 4t.

[0173] For example, the driving signal corresponds to the command received by the peripheral circuit 3. At this time, the selected first storage array 4t can be independently operated (e.g. data write, read or erase).

[0174] Therefore, the operation method of the memory provided by the embodiments of the present application can cooperate with the storage array controller 31 to realize the independent selection and operation of the plurality of storage arrays 4 in the memory, realize the separate control management and driving operation of each storage array 4, and realize the normal operation of the memory. In addition, the transmission path between the driving signal and the selected first storage array 4t from the peripheral circuit 3 can be shortened, and the time delay of the memory and the storage system 700 to which the memory is applied can be reduced.

[0175] In some embodiments, as shown in Figure 9 The memory 730 includes a second gate 331, and the setting mode of the second gate 331 can refer to the related description above, which will not be repeated here.

[0176] Before S300, that is, before the first gate 32 outputs the driving signal to the selected first storage array 4t, the operation method further includes: the second gate 331 selects at least one storage page in the selected first storage array 4t and receives the driving signal, and outputs the driving signal to the selected at least one storage page.

[0177] For example, the second gate 331 can selectively connect the first gate 32 and the at least one storage page in the selected first storage array 4t. The driving signal output by the first gate 32 is first transmitted to the second gate 331, and then selectively output by the second gate 331 to the selected at least one storage page in the selected first storage array 4t.

[0178] By selecting the first storage array 4t before the driving signal is output to the selected at least one storage page, the driving signal can be directly transmitted to the selected at least one storage page during the operation of the selected at least one storage page, without passing through the remaining storage arrays 4, and without synchronously performing the same operation on the remaining storage arrays 4, which can effectively reduce the time delay of the memory and the storage system 700 to which the memory is applied.

[0179] In some embodiments, as shown in Figure 10 and Figure 11 The number of the first storage arrays 4t is a plurality, and the number of the peripheral circuits 3 is a plurality, and the plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b. The first peripheral circuit 3a and the second peripheral circuit 3b can refer to the related description above, which will not be repeated here.

[0180] In the S200, the storage array controller 31 controls the first gating device 32 to select the first storage array 4t according to the data address. The storage array controller 31 of the first peripheral circuit 3a controls the first gating device 32 of the first peripheral circuit 3a to select a part of the first storage arrays 4t from the plurality of first storage arrays 4t, and the storage array controller 31 of the second peripheral circuit 3b controls the first gating device 32 of the second peripheral circuit 3b to select another part of the first storage arrays 4t from the plurality of first storage arrays 4t.

[0181] For example, the storage array controllers 31 of the plurality of peripheral circuits 3 are provided with a coordination mechanism. At this time, the plurality of peripheral circuits 3 can cooperatively control, manage and drive the plurality of storage arrays 4. For example, each peripheral circuit 3 can control, manage and drive a different storage array 4, so as to realize efficient operation of the plurality of storage arrays 4 and improve the performance of the memory 730.

[0182] For example, the first peripheral circuit 3a and the second peripheral circuit 3b can perform cooperative processing and operate the selected first storage arrays 4t. The operations can be the same or different. Alternatively, the first peripheral circuit 3a and the second peripheral circuit 3b can perform cooperative processing, and only one of the first peripheral circuit 3a and the second peripheral circuit 3b operates the selected first storage array 4t.

[0183] In this way, on the one hand, the plurality of types of commands can be supported and synchronously executed in the case that the plurality of types of commands are received by the peripheral circuit 3. On the other hand, the better command execution path can be preferentially selected according to the actual situation. On the other hand, in the case that a part of the peripheral circuits 3 fail, the other peripheral circuits 3 can be cooperatively operated to ensure the availability of the memory 730.

[0184] Those skilled in the art should be aware that in the above one or more examples, the functions described in the embodiments of the present application can be implemented in hardware, software, firmware or any combination thereof. When implemented in software, the functions can be stored in a computer readable medium or transmitted as one or more instructions or codes on a computer readable medium. The computer readable medium includes computer storage medium and communication medium, wherein the communication medium includes any medium that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0185] Based on this, the embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions. When the computer executable instructions are executed on the device, the operation method of any one of the above examples can be realized.

[0186] The embodiments of the present application further provide a computer program product, which, when running on a computer, enables the computer to perform the operation method of any one of the above examples.

[0187] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, The memory includes: The peripheral circuitry includes a storage array controller and a first selector; the storage array controller is connected to the first selector. Multiple memory arrays are stacked along the thickness direction of the peripheral circuit; the multiple memory arrays are respectively connected to the first selector; the multiple memory arrays include the first memory array; The storage array controller is used to control the first selector to select the first storage array, so as to output a drive signal to the selected first storage array.

2. The memory according to claim 1, characterized in that, The number of peripheral circuits is multiple, and the multiple peripheral circuits are located on the same side of the multiple memory arrays.

3. The memory according to claim 2, characterized in that, The two adjacent peripheral circuits are respectively the first peripheral circuit and the second peripheral circuit; the first peripheral circuit is located between the second peripheral circuit and the plurality of memory arrays; The memory also includes a conductive channel that runs through the first peripheral circuit and connects the output of the first selector in the first peripheral circuit and the second peripheral circuit.

4. The memory according to claim 1, characterized in that, The number of peripheral circuits is multiple, and the multiple peripheral circuits are respectively located on opposite sides of the multiple storage arrays.

5. The memory according to claim 4, characterized in that, The plurality of peripheral circuits include: a first peripheral circuit and a second peripheral circuit located on opposite sides of the plurality of memory arrays, respectively; The memory further includes interconnection posts that connect the first memory array and the first selector; The interconnection post connecting the first selector of the first peripheral circuit and the first memory array is connected to the interconnection post connecting the first selector of the second peripheral circuit and the first memory array.

6. The memory according to any one of claims 2-5, characterized in that, The number of the first storage arrays is multiple, and the multiple peripheral circuits include first peripheral circuits and second peripheral circuits; The memory array controller of the first peripheral circuit is used to control the first selector of the first peripheral circuit to select a portion of the first memory arrays from a plurality of the first memory arrays, so as to output a drive signal to the selected portion of the first memory arrays; The storage array controller of the second peripheral circuit is used to control the first selector of the second peripheral circuit to select another portion of the first storage arrays among the plurality of first storage arrays, so as to output a drive signal to the selected other portion of the first storage arrays.

7. The memory according to any one of claims 1-6, characterized in that, The first storage array includes: The stacked structure includes multiple gate layers and multiple gate dielectric layers that are alternately stacked along the thickness direction of the peripheral circuit; Word line contacts extend along the thickness direction of the peripheral circuit; the word line contacts are connected to the gate layer; Word line interconnects extend in a direction perpendicular to the thickness direction of the peripheral circuit; the word line interconnects are connected to the word line contacts; The memory further includes: word line interconnection posts extending along the thickness direction of the peripheral circuit; the word line interconnection posts are connected to the first selector and the word line interconnection lines.

8. The memory according to claim 7, characterized in that, The first storage array further includes: A channel structure that penetrates the stacked structure; Bit line contacts extend along the thickness direction of the peripheral circuit; the bit line contacts are connected to the channel structure; Bit line interconnects extend in a direction perpendicular to the thickness direction of the peripheral circuit; the bit line interconnects are connected to the bit line contacts; The memory further includes: a bit line interconnection post extending along the thickness direction of the peripheral circuit; the bit line interconnection post is connected to the first selector and the bit line interconnection line.

9. The memory according to claim 7 or 8, characterized in that, The first storage array further includes: A common source structure is located on one side of the stacked structure along the thickness direction of the peripheral circuit. The source line contact extends along the thickness direction of the peripheral circuit; the source line contact is connected to the common source structure; The source line interconnect extends in a direction perpendicular to the thickness direction of the peripheral circuit; the source line interconnect is connected to the source line contact. The memory further includes: a source line interconnection post extending along the thickness direction of the peripheral circuit; the source line interconnection post connects the first selector and the source line interconnection line.

10. The memory according to any one of claims 7-9, characterized in that, The word line interconnection posts, bit line interconnection posts, and source line interconnection posts are staggered from the first memory array.

11. The memory according to any one of claims 1-10, characterized in that, The memory further includes a second gate, which is connected between the first gate and the plurality of memory arrays; The second strobe is used to select at least one memory page in the selected first memory array and output the drive signal to the selected at least one memory page.

12. A method for operating a memory, characterized in that, The invention is applied to a memory, which includes peripheral circuitry and multiple memory arrays. The peripheral circuitry includes a memory array controller and a first selector. The memory array controller is connected to the first selector. The multiple memory arrays are stacked along the thickness direction of the peripheral circuitry. Each of the multiple memory arrays is connected to the first selector. The plurality of storage arrays includes a first storage array; The operation method includes: The peripheral circuit receives the data address; The storage array controller controls the first selector to select the first storage array based on the data address; The first selector outputs a drive signal to the selected first storage array.

13. The operating method according to claim 12, characterized in that, The memory further includes a second gate, which is connected between the first gate and the plurality of memory arrays; Before the first selector outputs a drive signal to the selected first memory array, the operation method further includes: The second selector selects at least one memory page in the selected first memory array, receives the drive signal, and outputs the drive signal to the selected at least one memory page.

14. The operating method according to claim 12 or 13, characterized in that, The number of the first storage arrays is multiple, and the number of the peripheral circuits is multiple, including the first peripheral circuit and the second peripheral circuit; The storage array controller controls the first selector to select the first storage array based on the data address, including: The memory array controller of the first peripheral circuit controls the first selector of the first peripheral circuit to select a portion of the first memory arrays from a plurality of the first memory arrays; The storage array controller of the second peripheral circuit controls the first selector of the second peripheral circuit to select another portion of the first storage arrays among the multiple first storage arrays.

15. A storage system, characterized in that, The storage system includes: A plurality of memories, including a first memory; the first memory includes the memory as described in any one of claims 1-11; A memory controller, connected to the plurality of memories.

16. The storage system according to claim 15, characterized in that, The plurality of memories further includes a second memory, the second memory comprising: Multiple peripheral circuits are stacked along the thickness direction of the peripheral circuits; each peripheral circuit includes a memory array controller and a first selector; the memory array controller is connected to the first selector; the multiple peripheral circuits include adjacent first peripheral circuits and second peripheral circuits. Multiple memory arrays are stacked along the thickness direction of the peripheral circuit; the multiple memory arrays are located between the first peripheral circuit and the second peripheral circuit; a portion of the multiple memory arrays are respectively connected to a first selector of the first peripheral circuit, and another portion of the memory arrays are respectively connected to a first selector of the second peripheral circuit. The storage array controller of the first peripheral circuit is used to control the first selector of the first peripheral circuit to select the first storage array in the portion of storage arrays, so as to output a drive signal to the selected first storage array. The storage array controller of the second peripheral circuit is used to control the first selector of the second peripheral circuit to select the first storage array in the other part of the storage array, so as to output a drive signal to the selected first storage array.

17. An electronic device, characterized in that, The electronic device includes: The storage system as described in claim 15 or 16; The circuit board is connected to the storage system.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions; when the computer-executable instructions are executed, the operating method of any one of claims 12-14 can be implemented.

19. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the operating method as described in any one of claims 12-14.

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