System-in-package, electronic device and system-in-package method

Abstract

The invention relates to the field of integrated circuit packaging, in particular to a system-in-package part, an electronic device and a system-in-package method, and the system-in-package part comprises a first substrate, a second substrate, an alloy cover plate and a packaging electronic part, the first substrate, the second substrate and the alloy cover plate are connected into an integral structure; the second surface of the first substrate comprises an assembly assembling area; the packaging electronic parts comprise a first packaging electronic part and a second packaging electronic part; the first packaging electronic part is assembled in the component assembling area, and the second packaging electronic part is assembled on the first surface of the second substrate; the alloy cover plate surrounds at least one part of the component assembling area; the second surface of the first substrate further comprises a non-assembly area, the non-assembly area comprises an electric connection structure, and the packaging electronic part is electrically connected with an external circuit through the electric connection structure. According to the invention, the space occupation and weight of the package are reduced, the assembly process is simplified, and the signal transmission quality is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit packaging, in particular to a system-in-package, an electronic device and a system-in-package method. BACKGROUND

[0002] With the development of integrated circuit technology, higher and higher requirements are put forward for the packaging means of integrated circuits, among which the existing DP-SIP (Dual Polarization System-in-Package) packaging problems are becoming more and more prominent.

[0003] Taking microwave and millimeter wave packaging as an example, the current microwave and millimeter wave packaging usually needs to prepare three ceramic substrates, which are stacked and welded to form two cavities for placing electronic components (such as chips, capacitors, etc.) on the upper and lower layers. However, such packaging structure not only has complex and troublesome production process and high production cost, but also too many levels will cause the RF transmission path of the core chip to be lengthened, and the path needs to pass through multiple layers of ceramic and copper pillars and other structures, resulting in large insertion loss and affecting the performance index. In addition, the three-layer ceramic substrate occupies a large space and has a large weight, which is not conducive to the miniaturization of the device.

[0004] Therefore, how to simplify the production process of system-in-package, reduce cost, improve signal transmission quality and reduce space occupation and weight of the package is a problem to be solved by those skilled in the art. SUMMARY

[0005] The purpose of the present application is to provide a system-in-package, an electronic device and a system-in-package method to solve the problems in the prior art.

[0006] To solve the above technical problems, the present application provides a system-in-package, comprising a first substrate, a second substrate, an alloy cover plate and a packaged electronic component.

[0007] The first substrate, the second substrate and the alloy cover plate are connected into an integrated structure; wherein the first surface of the first substrate is opposite to the first surface of the second substrate, and the alloy cover plate is opposite to the second surface of the first substrate.

[0008] The second surface of the first substrate comprises a component assembly area.

[0009] The packaged electronic component comprises a first packaged electronic component and a second packaged electronic component.

[0010] The first packaged electronic component is assembled in the component assembly area, and the second packaged electronic component is assembled on the first surface of the second substrate.

[0011] The alloy cover plate surrounds at least part of the component assembly area.

[0012] The second surface of the first substrate further comprises a non-mounting area, the non-mounting area comprising an electrical connection structure, the package electronic device being electrically connected with external circuit through the electrical connection structure; the non-mounting area does not overlap with the component mounting area.

[0013] Optionally, in the system-in-package, the electrical connection structure is a ball grid array.

[0014] Optionally, the first substrate and the second substrate are ceramic substrates.

[0015] Optionally, in the system-in-package, the electrical connection structure comprises a signal connection structure and a ground connection structure.

[0016] The ground connection structure surrounds the alloy cover plate or the component mounting area.

[0017] Optionally, in the system-in-package, the package electronic device further comprises a third package electronic device.

[0018] The third package electronic device is disposed on the first surface of the first substrate.

[0019] Optionally, in the system-in-package, the distance from the upper surface of the alloy cover plate to the second surface of the first substrate in the integrated structure ranges from 0.5 mm to 1.0 mm, inclusive.

[0020] Optionally, in the system-in-package, further comprising a heat dissipation plate.

[0021] The heat dissipation plate is connected to the second surface of the second substrate.

[0022] Optionally, in the system-in-package, the package electronic device disposed in the component mounting area comprises a phase-array multifunctional chip.

[0023] The package electronic device disposed on the first surface of the second substrate comprises a power amplifier chip.

[0024] Optionally, in the system-in-package, the electrical connection structure is higher than the alloy cover plate.

[0025] An electronic device, comprising a PCB board and any one of the system-in-packages described above.

[0026] The system-in-package is electrically connected with the PCB board through the electrical connection structure.

[0027] Optionally, in the electronic device, the PCB board further comprises a PCB blind slot.

[0028] The PCB board is connected with the electric connection structure, and the alloy cover plate is embedded in the PCB blind slot at least in part.

[0029] A system-in-package method for producing any of the above system-in-package, comprising:

[0030] Preparation of a first substrate, a second substrate, an alloy cover plate and a packaged electronic component;

[0031] Assembling the packaged electronic component to the second surface of the first substrate and the first surface of the second substrate; the second surface of the first substrate comprises a component assembly area, and the packaged electronic component is assembled in the component assembly area;

[0032] Pre-fixing the first substrate, the second substrate and the alloy cover plate; in the pre-fixing, the first surface of the first substrate is arranged opposite to the first surface of the second substrate, and the alloy cover plate is arranged opposite to the component assembly area;

[0033] Connecting the first substrate, the second substrate and the alloy cover plate into an integrated structure based on the position relationship of the pre-fixing;

[0034] In the non-assembly area of the second surface of the first substrate, an electric connection structure is arranged, so that the packaged electronic component is electrically connected with an external circuit through the electric connection structure; the non-assembly area does not overlap with the component assembly area.

[0035] The system-level package provided by the application comprises a first substrate, a second substrate, an alloy cover plate and packaged electronic components; the first substrate, the second substrate and the alloy cover plate are connected into an integrated structure; wherein the first surface of the first substrate is opposite to the first surface of the second substrate, and the alloy cover plate is opposite to the second surface of the first substrate; the second surface of the first substrate comprises a component assembly area; the packaged electronic components comprise first packaged electronic components and second packaged electronic components; the first packaged electronic components are assembled in the component assembly area, and the second packaged electronic components are assembled on the first surface of the second substrate; the alloy cover plate surrounds at least part of the component assembly area; the second surface of the first substrate further comprises a non-assembly area, the non-assembly area comprises an electrical connection structure, and the packaged electronic components are electrically connected with external circuits through the electrical connection structure; the non-assembly area does not overlap with the component assembly area. In the application, only two substrates and one alloy cover plate are used, and the two-layer arrangement of the packaged electronic components is completed, which reduces the space occupation and weight of the package, simplifies the assembly process, improves the product yield, and shortens the radio frequency transmission path of the second packaged electronic components on the lowermost substrate (the second substrate in the application) to the external circuits, thereby improving the signal transmission quality. The application also provides an electronic device and a system-level packaging method with the above advantages. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0037] Figure 1 It is a structural schematic diagram of the system-level package in the prior art;

[0038] Figure 2 It is a structural schematic diagram of one specific embodiment of the system-level package provided by the application;

[0039] Figure 3 It is a structural schematic diagram of another specific embodiment of the system-level package provided by the application;

[0040] Figure 4 It is a structural schematic diagram of another specific embodiment of the system-level package provided by the application;

[0041] Figure 5A schematic diagram comparing the power amplifier output power at various frequency bands of a specific embodiment of the system-in-package provided by the present invention with that of a conventional double-layer package in the prior art.

[0042] Figure 6 A schematic diagram of a specific embodiment of the electronic device provided by the present invention;

[0043] Figure 7 A schematic diagram of another specific embodiment of the electronic device provided by the present invention;

[0044] Figure 8 A schematic diagram of another specific embodiment of the electronic device provided by the present invention;

[0045] Figure 9 A schematic diagram of another specific embodiment of the electronic device provided by the present invention;

[0046] Figure 10 This is a flowchart illustrating a specific implementation of the system-level encapsulation method provided by the present invention.

[0047] Instruction manual illustrations:

[0048] 11-First substrate; 12-Second substrate; 20-Alloy cover plate; 30-Encapsulated electronic components; 40-Electrical connection structure; 50-Heat sink; 100-PCB board; 110-PCB blind slot. Detailed Implementation

[0049] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The core of this invention is to provide a system-level package (SLP), the structural diagram of which is shown in a specific embodiment. Figure 2 As shown, this is referred to as Specific Embodiment 1, which includes a first substrate 11, a second substrate 12, an alloy cover plate 20, and an encapsulated electronic component 30.

[0051] The first substrate 11, the second substrate 12 and the alloy cover plate 20 are connected to form an integral structure; wherein, the first surface of the first substrate 11 is opposite to the first surface of the second substrate 12, and the alloy cover plate 20 is opposite to the second surface of the first substrate 11.

[0052] The second surface 12 of the first substrate 11 includes a component assembly area;

[0053] The package electronic component 30 comprises a first package electronic component 31 and a second package electronic component 32;

[0054] The first package electronic component 31 is assembled in the component assembly area, and the second package electronic component 32 is assembled in the first surface of the second substrate 12;

[0055] The alloy cover plate 20 surrounds at least a part of the component assembly area;

[0056] The second surface of the first substrate 11 further comprises a non-assembly area, the non-assembly area comprises an electrical connection structure 40, and the package electronic component 30 is electrically connected with external circuit through the electrical connection structure 40; the non-assembly area does not overlap with the component assembly area.

[0057] In some embodiments, the non-assembly area can surround the assembly area, and in other embodiments, the non-assembly area can also not surround the component assembly area. In addition, although the first package electronic component 31 is entirely arranged in the component assembly area, the first package electronic component 31 is not necessarily entirely covered by the alloy cover plate 20, in other words, the projection of the alloy cover plate 20 on the second surface of the first substrate 31 can partially overlap with the component assembly area, or can completely overlap with the component assembly area. For example, in some embodiments, there are multiple first package electronic components 31 in the component assembly area, and the alloy cover plate 20 only surrounds a part of the first package electronic components 31, and another part of the first package electronic components 31 is not surrounded by the alloy cover plate 20 and is exposed outside.

[0058] Reference can be made to Figure 1 , Figure 1 The prior art three-layer substrate two-chip structure is shown in FIG. 1, and the signal transmission paths of the chip in the upper layer (hereinafter referred to as the upper layer chip) and the chip in the lower layer (hereinafter referred to as the lower layer chip) are indicated by dashed lines. In order for the upper layer chip to achieve signal transmission, it needs to pass through one layer of substrate, and in order for the lower layer chip to achieve signal transmission, it needs to pass through two layers of copper pillars and two layers of substrates, which has large insertion loss and affects the performance index. In contrast, the structure of the present application is a two-layer substrate two-chip structure (reference can be made to FIG. 2), in which the upper layer chip (corresponding to the first package electronic component 31) needs to pass through only the surface circuit of the first substrate 11 to reach the corresponding electrical connection structure 40, without penetrating the substrate, and the lower layer chip (corresponding to the second package electronic component 32) needs to pass through only one layer of copper pillars (not shown in FIG. 3, the position of the copper pillar can be referred to in FIG. 4) and one layer of substrate, which greatly shortens the signal transmission path, reduces the signal loss, and improves the signal quality compared with the prior art. Figure 2 Figure 2 Figure 1 In contrast, the structure of the present application is a two-layer substrate two-chip structure (reference can be made to FIG. 2), in which the upper layer chip (corresponding to the first package electronic component 31) needs to pass through only the surface circuit of the first substrate 11 to reach the corresponding electrical connection structure 40, without penetrating the substrate, and the lower layer chip (corresponding to the second package electronic component 32) needs to pass through only one layer of copper pillars (not shown in FIG. 3, the position of the copper pillar can be referred to in FIG. 4) and one layer of substrate, which greatly shortens the signal transmission path, reduces the signal loss, and improves the signal quality compared with the prior art.​​

[0059] like Figure 1 As shown, the traditional three-layer substrate system-in-package weighs 2.9 grams. Furthermore, if the substrate is a ceramic substrate, the greater weight further reduces its reliability due to the significant difference in the coefficients of thermal expansion between the ceramic substrate and the PCB board 100 with which the electrical connection structure 40 is mated. In addition, the existing three-layer substrate structure requires a larger size of gold-tin solder sheet, resulting in higher costs.

[0060] In one specific implementation, the electrical connection structure 40 is a ball grid array;

[0061] And / or, the first substrate 11 and the second substrate 12 are ceramic substrates.

[0062] The ball grid array has high flexibility and is easy to connect with the external PCB board 100, which is a preferred embodiment of the electrical connection structure 40 of the present invention. Of course, other electrical connection structures 40 can also be used, such as wire bonding. If the height of the upper surface of the alloy cover plate 20 (that is, the surface away from the first substrate 11) is higher than the electrical connection structure 40, a groove can be provided on the first substrate 11, and the alloy cover plate 20 can be placed in the groove so that the upper surface of the alloy cover plate 20 is lower than the electrical connection structure 40.

[0063] Using ceramic substrates can significantly improve the yield and operational stability of packaged components, while reducing the difficulty of the process.

[0064] Furthermore, the alloy cover plate 20 is a gold-tin Kovar cover plate.

[0065] The gold-tin Kovar cover plate is a Kovar (iron-nickel-cobalt alloy) cover plate with a gold-tin alloy solder layer on its surface. The gold-tin alloy solder layer has a melting point of approximately 280°C and possesses high thermal conductivity, high strength, and excellent airtight welding capability. The core characteristic of the Kovar cover plate itself is its coefficient of thermal expansion (CTE≈4.5–5.5×10⁻⁶). -6 ( / ℃) is highly compatible with packaging substrates such as ceramics and glass. When used with the ceramic substrate mentioned above, it can avoid thermal stress cracking caused by temperature changes, greatly improving the yield and operational stability of the packaged components.

[0066] Furthermore, the packaged electronic component 30 also includes a third packaged electronic component 33;

[0067] The third packaged electronic component 33 is disposed on the first surface of the first substrate 11.

[0068] You can refer to this. Figure 3 , Figure 3The third packaging electronic component 33 in the packaging electronic component 30 is arranged on the surface of the first substrate 11 facing the second substrate 12, and in this embodiment, the surface of the first substrate 11 is further utilized, which greatly improves the integration of the packaging component and facilitates the miniaturization and integration of the packaging component.

[0069] In addition, the first packaging electronic component, the second packaging electronic component, and the third packaging electronic component in the present application are not different types of electronic components, and the first, the second, and the third are used to distinguish only the positions where they are arranged. In addition, the first packaging electronic component, the second packaging electronic component, and the third packaging electronic component each include one or more independent electronic components, which can be active chips or passive chips or capacitors, and can be selected according to actual conditions.

[0070] As a preferred embodiment, the electrical connection structure 40 is higher than the alloy cover plate 20. In other words, the distance from the distal end of the electrical connection structure 40 to the first substrate 11 is greater than the distance from the distal end of the alloy cover plate 20 to the first substrate 11, which defines that the electrical connection structure 40 is higher than the alloy cover plate 20. This can greatly reduce the requirements for the connection surface of the system-level packaging component to the external circuit, improve the flexibility of the system-level packaging component, and reduce the space occupation of the system-level packaging component. In some embodiments, the height of the alloy cover plate 20 can also be set to be higher than the electrical connection structure 40.

[0071] Specifically, the distance from the upper surface of the alloy cover plate 20 to the second surface of the first substrate 11 in the integrated structure ranges from 0.5 mm to 1.0 mm, including the end point values, such as any one of 0.50 mm, 0.99 mm, or 1.00 mm. It should be noted that the upper surface of the alloy cover plate 20 refers to the surface of the alloy cover plate 20 away from the first substrate 11. If the distance from the upper surface to the second surface of the first substrate 11 is too small, the space of the cavity surrounded by the alloy cover plate 20 and the first substrate 11 will be severely limited, thereby increasing the limitations for circuit design. If the distance from the upper surface to the second surface of the first substrate 11 is too large, the system-level packaging component will be difficult to be fixed to the external circuit only by the electrical connection structure 40. The above parameter range is the best result after a large number of theoretical calculations and actual tests. Within the above parameter range, the arrangement of the packaging electronic component 30 is not affected, and the ball grid array is higher than the alloy cover plate 20. The system-level packaging component can be fixed only by the welding of the ball grid array and the external circuit, which greatly simplifies the production process and reduces the production cost.

[0072] As a specific embodiment, the electric connection structure 40 includes a signal connection structure and a ground connection structure;

[0073] The ground connection structure surrounds the alloy cover plate 20 or the component assembly area.

[0074] In the present embodiment, the electric connection structure 40 is further subdivided, specifically into the signal connection structure and the ground connection structure, the signal connection structure is used for signal transmission with the external circuit, and the ground connection structure is used for grounding to ensure line safety. Furthermore, in the present embodiment, the ground connection structure surrounds the alloy cover plate 20 or the component assembly area. Since the ground connection structure is all grounded, the area surrounded by the ground connection structure becomes an electromagnetic shielding area. Placing the packaged electronic components 30 that are prone to electromagnetic interference in the surrounding of the alloy cover plate 20 can significantly improve the working stability of the packaged electronic components 30. Whether the ground connection structure only surrounds the alloy cover plate 20 or also partially surrounds the component assembly area can be determined according to the installation position of the packaged electronic components 30 that need to be electromagnetically shielded. In some embodiments, the ground connection structure can also not completely surround the alloy cover plate 20 or the component assembly area, but only surround part of the alloy cover plate 20 or the component assembly area. In other embodiments, the alloy cover plate 20 or the component assembly area is arranged along the edge of the second surface of the first substrate 11, and there is no ground connection structure on the side close to the edge of the second surface.

[0075] Furthermore, a heat dissipation plate 50 is also included;

[0076] The heat dissipation plate 50 is connected to the second surface of the second substrate 12.

[0077] Please refer to Figure 4 In the present embodiment, the heat dissipation plate 50 is directly arranged on the second surface of the second substrate 12, which makes the heat dissipation distance of the packaged electronic components 30 on the second substrate 12 shorter and the heat dissipation effect better, greatly improving the selection freedom of the packaged electronic components 30 and the universality of the present application.

[0078] Furthermore, the packaged electronic components 30 arranged in the component assembly area include amplitude-phase multifunctional chips;

[0079] The packaged electronic components 30 arranged on the first surface of the second substrate 12 include power amplifier chips.

[0080] In the present preferred embodiment, the types of the packaged electronic components 30 on the second surface of the first substrate 11 and the first surface of the second substrate 12 are limited, that is, the

[0081] The amplitude-phase multifunctional chip belongs to a small signal device, that is, a device with small intensity (current, voltage) of received and processed electrical signals, which can work normally in a small space formed by the first substrate 11 and the alloy cover plate 20, while the power amplifier chip is a large power device with large intensity of electrical signals and much heat, and the power amplifier chip with much heat is placed on the second substrate 12 close to the heat dissipation plate 50, so that the heat dissipation effect is further improved, the working stability of the system-level package is improved, and the interference of the power amplifier chip with large heat to the working of the amplitude-phase multifunctional chip is avoided.

[0082] Please refer to Figure 5 , Figure 5 The comparison diagram of the power amplifier output power (Pout) of the system-level package of the technical scheme of the present application in various frequency bands (Freq) and the double-layer traditional product in the prior art is not difficult to see that, due to the further shortening of the transmission path and the further reduction of the loss, the output power of the system-level package (indicated by “single layer” in the figure) provided by the present application in various frequency bands is higher than that of the existing double-layer system-level package (indicated by “double layer” in the figure) in the traditional art.

[0083] The system-level package provided by the present application, the first substrate 11, the second substrate 12 and the alloy cover plate 20 are connected into an integrated structure; wherein the first surface of the first substrate 11 is opposite to the first surface of the second substrate 12, and the alloy cover plate 20 is opposite to the second surface of the first substrate 11; the second surface 12 of the first substrate 11 includes a component assembly area; the packaged electronic component 30 includes a first packaged electronic component 31 and a second packaged electronic component 32; the first packaged electronic component 31 is assembled in the component assembly area, and the second packaged electronic component 32 is assembled on the first surface of the second substrate 12; the alloy cover plate 20 surrounds at least a part of the component assembly area; the second surface of the first substrate 11 further includes a non-assembly area, the non-assembly area includes an electrical connection structure 40, and the packaged electronic component 30 is electrically connected with an external circuit through the electrical connection structure 40; the non-assembly area and the component assembly area do not overlap. In the present application, only two substrates and one alloy cover plate 20 are used, that is, the two-layer arrangement of the packaged electronic component 30 is completed, which not only reduces the space occupation and weight of the package, but also simplifies the assembly process, and improves the product yield, and compared with the three-layer substrate in the prior art, the radio frequency transmission path of the second packaged electronic component 33 arranged on the lowermost substrate (the second substrate 12 in the present application) to the external circuit is greatly shortened, and the signal transmission quality is improved.

[0084] The present application also provides an electronic device, and a structure diagram of one embodiment is as shown in Figure 6As shown in Fig. 2, which is referred to as the second embodiment, the electronic device comprises a PCB board 100 and any one of the above-mentioned system-in-package;

[0085] The system-in-package is electrically connected with the PCB board 100 through the electric connection structure 40.

[0086] For details, please refer to the description of the system-in-package above, and the second embodiment will not be repeated here.

[0087] As a preferred embodiment, the PCB board 100 further comprises a PCB blind slot 110;

[0088] The PCB board 100 is welded with the electric connection structure 40, and the alloy cover plate 20 is embedded in the PCB blind slot 110.

[0089] For details, please refer to the description of the system-in-package above, and the second embodiment will not be repeated here. Figure 7 , Figure 7 Fig. 4 is a partial view of the contact part of the PCB board 100 and the system-in-package, and the preferred embodiment is for the case that the alloy cover plate 20 is higher than the electric connection structure 40. In this case, the PCB board 100 is provided with a PCB blind slot 110, which can accommodate the alloy cover plate 20 in the extreme case without affecting the close connection between the electric connection structure 40 and the PCB board 100, thereby improving the universality of the present application.

[0090] Of course, in order to facilitate installation, the height of the electric connection structure 40 is usually set to be higher than the upper surface of the alloy cover plate 20. In order to realize that the electric connection structure 40 is higher than the alloy cover plate 20, the following methods can be used, one is to use large-size solder balls to form the ball grid array, and the corresponding structural schematic diagram is shown in Fig. 5; Figure 6 The second is to make the electric connection structure 40 into a column, such as a solder column, so as to more easily realize a larger height-width ratio, and the corresponding structural schematic diagram is shown in Fig. 6; Figure 8 The third is to groove the corresponding position of the assembly mounting area on the second surface 12 of the first substrate 11, so that the mounting plane of the first packaging electronic device 31 and the alloy cover plate 20 is lower than the mounting plane of the electric connection structure 40, and the corresponding structural schematic diagram is shown in Fig. 7; Figure 9 Of course, the height of the electric connection structure 40 and the height of the upper surface of the alloy cover plate 20 can be selected and adjusted according to actual needs.

[0091] The present application also provides a system-in-package method, and the flowchart of one embodiment thereof is shown in Fig. 8, which is referred to as the third embodiment. The system-in-package method is used to produce any one of the above-mentioned system-in-package, and comprises the following steps: Figure 10 ​

[0092] S101: Prepare the first substrate 11, the second substrate 12, the alloy cover plate 20 and the packaged electronic component 30.

[0093] S102: Assemble the packaged electronic component 30 to the second surface of the first substrate 11 and the first surface of the second substrate 12; the second surface of the first substrate 11 comprises a component assembly area, and the packaged electronic component 30 is assembled in the component assembly area.

[0094] S103: Pre-fix the first substrate 11, the second substrate 12 and the alloy cover plate 20; in the pre-fixing, the first surface of the first substrate 11 is arranged opposite to the first surface of the second substrate 12, and the alloy cover plate 20 is arranged opposite to the component assembly area.

[0095] S104: Based on the position relationship of the pre-fixing, melt and seal the first substrate 11, the second substrate 12 and the alloy cover plate 20 into an integrated structure.

[0096] As a preferred embodiment, the step comprises:

[0097] Based on the position relationship of the pre-fixing, the connection between the first substrate 11 and the second substrate 12 and the connection between the first substrate 11 and the alloy cover plate 20 are completed by single melting and sealing.

[0098] By single melting and sealing, the connection between the first substrate 11 and the second substrate 12 and the connection between the alloy cover plate 20 and the first substrate 11 are completed at the same time, which can greatly improve the packaging efficiency of the system-level packaging method and shorten the packaging time.

[0099] S105: On the non-assembly area of the second surface of the first substrate 11, arrange an electrical connection structure 40, so that the packaged electronic component 30 is electrically connected to the external circuit through the electrical connection structure 40; the non-assembly area does not overlap with the component assembly area.

[0100] The specific technical details of the present embodiment correspond to the system-level package in the foregoing, which can be referred to the foregoing.

[0101] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0102] It should be noted that, in the specification, the terms such as first and second, etc. are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0103] The system-in-package, electronic device and system-in-package method provided by the present application are described in detail above. The principles and implementation manners of the present application are described by applying specific examples in this paper, and the above description of the examples is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A system-in-package (SIP), characterized in that, Includes a first substrate, a second substrate, an alloy cover plate, and packaged electronic components; The first substrate, the second substrate, and the alloy cover plate are connected to form an integral structure; wherein, the first surface of the first substrate is opposite to the first surface of the second substrate, and the alloy cover plate is opposite to the second surface of the first substrate. The second surface of the first substrate includes a component assembly area; The packaged electronic component includes a first packaged electronic component and a second packaged electronic component; The first packaged electronic component is assembled in the component assembly area, and the second packaged electronic component is assembled on the first surface of the second substrate; The alloy cover plate surrounds at least a portion of the component assembly area; The second surface of the first substrate further includes a non-assembly area, which includes an electrical connection structure through which the packaged electronic component is electrically connected to an external circuit; the non-assembly area does not overlap with the component assembly area.

2. The system-in-package (SIP) as described in claim 1, characterized in that, The electrical connection structure is a ball grid array; And / or, the first substrate and the second substrate are ceramic substrates.

3. The system-in-package (SIP) as described in claim 1, characterized in that, The electrical connection structure includes a signal connection structure and a grounding connection structure; The grounding connection structure surrounds the alloy cover plate or the component assembly area.

4. The system-in-package (SIP) as described in claim 1, characterized in that, The packaged electronic component also includes a third packaged electronic component; The third packaged electronic component is disposed on the first surface of the first substrate.

5. The system-in-package (SIP) as described in claim 1, characterized in that, The distance from the upper surface of the alloy cover plate to the second surface of the first substrate in the integrated structure ranges from 0.5 mm to 1.0 mm, including the endpoint values.

6. The system-in-package (SIP) as described in any one of claims 1 to 5, characterized in that, It also includes a heat sink; The heat sink is connected to the second surface of the second substrate.

7. The system-in-package (SIP) as described in claim 6, characterized in that, The packaged electronic components disposed in the component assembly area include a phase-multifunctional chip; The packaged electronic components disposed on the first surface of the second substrate include a power amplifier chip.

8. The system-in-package (SIP) as described in claim 1, characterized in that, The electrical connection structure is higher than the alloy cover plate.

9. An electronic device, characterized in that, The electronic device includes a PCB board and a system-in-package as described in any one of claims 1 to 8; The system-in-package is electrically connected to the PCB board through the electrical connection structure.

10. The electronic device as claimed in claim 9, characterized in that, The PCB board also includes PCB blind slots; The PCB board is connected to the electrical connection structure, and at least a portion of the alloy cover plate is embedded in the PCB blind slot.

11. A system-level encapsulation method, characterized in that, The system-in-package method is used to produce a system-in-package as described in any one of claims 1 to 8, comprising: Prepare the first substrate, the second substrate, the alloy cover plate, and the packaged electronic components; The packaged electronic component is assembled onto the second surface of the first substrate and the first surface of the second substrate; the second surface of the first substrate includes a component assembly area, and the packaged electronic component is assembled into the component assembly area; The first substrate, the second substrate, and the alloy cover plate are pre-fixed; in the pre-fixing, the first surface of the first substrate and the first surface of the second substrate are disposed opposite to each other, and the alloy cover plate is disposed opposite to the component assembly area. The first substrate, the second substrate, and the alloy cover plate are connected into an integral structure based on the pre-fixed positional relationship; An electrical connection structure is provided in the non-assembly area on the second surface of the first substrate, so that the packaged electronic component is electrically connected to an external circuit through the electrical connection structure; the non-assembly area does not overlap with the component assembly area.

Images