Critical conduction mode three-level Boost PFC converter based on input voltage self-adaptive alpha value

Abstract

The invention discloses a critical conduction mode three-level Boost PFC converter based on an input voltage self-adaptive alpha value, alpha is a multiple of single switch conduction time relative to common conduction time, and the critical conduction mode three-level Boost PFC converter comprises an alternating current source, an EMI filter, a rectifier bridge circuit, a three-level Boost circuit, a load, a voltage sampling circuit and a control and drive circuit. By deducing and analyzing the PF expression of the converter, it is found that on the premise that the PF is not degraded, a larger alpha value is allowed to be used during high-voltage input, the alpha value is gradually increased along with the increase of the input voltage level, the increase of the alpha can bring about the reduction of the switching frequency, the inductance peak current and the switching loss of the converter, and the conversion efficiency of the converter is improved. And efficiency improvement and performance optimization are maximized. Compared with a three-level Boost PFC converter with a fixed alpha value, the converter associates alpha with input voltage, ingeniously utilizes the characteristic that PF is insensitive to alpha change under high voltage, breaks the performance bottleneck under the fixed alpha, and realizes better global efficiency-PF tradeoff.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a critical conduction mode three-level Boost PFC converter based on an input voltage adaptive α value. Background Technology

[0002] With the development of society and technology, the efficient use of electrical energy has become increasingly important, and this utilization is inseparable from power electronics technology. Power electronic devices such as switching power supplies, as power conversion devices, have advantages such as high power density, high efficiency, small size, and low cost, and are widely used in adapters, LED lighting, and medical equipment power supplies. However, the large-scale application of power electronic devices has led to increasingly serious problems that threaten the safe and stable operation of the power grid, such as current distortion on the grid input side, harmonic pollution, and reduced power factor. Therefore, how to improve the power factor and power quality has become a focus of attention.

[0003] Currently, common power factor correction (PFC) converters on the market include boost converters, buck converters, flyback converters, and buck-boost converters. Among these, the classic Boost PFC converter is the most effective in improving power factor and reducing current harmonics. However, it suffers from drawbacks such as a large power inductor (L) and high stress on downstream converter components, which are bottlenecks hindering its development. By introducing multi-level conversion technology and performing equivalent transformations on the traditional two-level Boost PFC converter, a three-level Boost PFC converter is obtained. Compared to the traditional topology, the voltage stress on the switching devices in the three-level Boost PFC converter can be reduced by half. Simultaneously, under the same inductor current ripple conditions, the required inductance value is also lower than that of the traditional topology. PFC converters operating in CRM mode have advantages such as zero-current turn-on of the switching transistors, no reverse recovery current of the diodes, and low switching losses. Furthermore, the control of the converter in this mode is relatively simple.

[0004] However, CRM three-level Boost PFC converters generally use a fixed α (i.e., the multiple of the single switch conduction time to the common conduction time), which limits the efficiency optimization space under high voltage. Furthermore, the fixed α only uses a single slope combination mode, failing to take advantage of the multi-level characteristics of three-level Boost to give the current slope degree of freedom (DOF) the adaptive potential over a wide voltage range. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a critical conduction mode three-level Boost PFC converter based on an input voltage adaptive α value. By fixing the converter's power factor (PF) value at a relatively high value, such as 0.995, across the entire wide input voltage range (85–265V), adaptive α value selection based on input voltage can be achieved. This solves the problem that traditional CRM three-level Boost PFC converters, which use a fixed α value, limit the efficiency optimization space under high voltage. The specific solution is as follows:

[0006] This invention relates to a critical conduction mode three-level Boost PFC converter based on an input voltage adaptive α value, comprising a main power circuit and a control circuit; the main power circuit includes an AC source (1), an EMI filter (2), a rectifier bridge (3), a power inductor L (4), series-connected switches S1 (5) and S2 (6), diodes D5 (7) and D6 (8), series-connected output filter capacitors C1 (9) and C2 (10), and a load R. o (11); The control circuit includes a differential sampling circuit (12), a voltage adaptive α value calculation circuit (13), a resistance sampling circuit (14), an error amplification circuit (15), a sawtooth wave generation circuit (16), a zero-crossing detection circuit (17), a pulse width modulation circuit (18), an output voltage balance control circuit (19), and a switch selection circuit (20).

[0007] The main power circuit includes an AC source (1), an EMI filter (2), a rectifier bridge (3), a power inductor L (4), series-connected switching transistors S1 (5) and S2 (6), diodes D5 (7) and D6 (8), series-connected output filter capacitors C1 (9) and C2 (10), and a load R. o (11); The AC source (1) is connected to the input port of the EMI filter (2), and the output port of the EMI filter (2) is output through the rectifier bridge (3); The rectifier bridge (3) is composed of diodes D1 (301), D2 (302), D3 (303), and D4 (304). The upper end of the rectifier bridge output port is connected in series with the positive terminal of the power inductor L (4), and its negative terminal is connected to the source of the switch S1 (5) and the anode of the diode D5 (7). The switch S1 (5) S2(6) is connected in series, and the lower end of the rectifier bridge output port is connected to the drain of the switching transistor S2(6) and the cathode of the diode D6(8); the output filter capacitors C1(9) and C2(10) are connected in series, the positive terminal of C1(9) is connected to the cathode of the diode D5(7), the negative terminal of C2(10) is connected to the anode of the diode D6(8), and the connection point of the negative terminal of the output filter capacitor C1(9) and the positive terminal of C2(10) is connected to the connection point of the drain of the switching transistor S1(5) and the source of S2(6); the load R o(11) The two ends are connected to the positive terminal of the output filter capacitor C1 (9) and the negative terminal of C2 (10) respectively.

[0008] The control circuit includes a differential sampling circuit (12), a voltage adaptive α value calculation circuit (13), a resistance sampling circuit (14), an error amplification circuit (15), a sawtooth wave generation circuit (16), a zero-crossing detection circuit (17), a pulse width modulation circuit (18), an output voltage balance control circuit (19), and a switch selection circuit (20). The input terminal of the differential sampling circuit (12) is connected to the output port of the rectifier bridge (3) for sampling the input voltage. The input terminal of the voltage adaptive α value calculation circuit (13) is connected to the output terminal of the differential sampling circuit (12) for generating an adaptive α value to be fed into the pulse width modulation circuit (18). The resistance sampling circuit (14) includes sampling resistors R5 (1401) and R6 (1402) for sampling the output voltage V. o Sampling resistors R7 (1403) and R8 (1404) are used to sample the voltage V of filter capacitor C2 (10). C1 R5(1401) = R7(1403), R6(1402) = R8(1404), and subtractor (1405) are used to calculate the sampling voltage V of filter capacitor C1(9). C2 The error amplifier circuit (15) includes a loop compensation circuit (1501), an error amplifier (1502), and a first reference power supply (1503). Its input terminal is connected to the output voltage V sampled by the resistor sampling circuit (14). o The error signal V used to output the output voltage of the main power circuit. compThe sawtooth wave generation circuit (16) generates a sawtooth wave signal by repeatedly charging and discharging the capacitor using a DC source, and its output is connected to the positive terminal of the voltage comparator (1801); the zero-crossing detection circuit (17) generates a ZCD signal by detecting the inductor voltage, and generates a zero-crossing signal through the zero-current detection circuit, which is then connected to the pulse width modulation circuit (18); the pulse width modulation circuit (18) includes a voltage comparator (1801), an RS flip-flop (1802), a pulse width counter (1803), a multiplier (1804), a controllable monostable multivibrator (1805), and a logic OR gate (1806), used to generate two pulse width signals that simultaneously activate one of which is delayed and deactivated; the output voltage balance The control circuit (19) includes a subtractor (1901), an absolute value operation module (1902), a second reference power supply (1903), a voltage comparator (1904), a D flip-flop (1905), a voltage comparator (1906), and a logic selector (1907). When the voltage difference between the two output capacitors exceeds a certain limit, i.e., the output voltage is unbalanced, a pulse width selection signal with voltage balance adjustment is generated and sent to the control terminal of the logic selector of the switch selection circuit (20). The switch selection circuit (20) is composed of a logic selector (2001) and a logic selector (2002), which can generate a switch drive signal with voltage balance adjustment capability and send it to the gate of each switch transistor.

[0009] Optionally, the input terminal of the voltage adaptive α value calculation circuit (13) is connected to the V output of the differential sampling circuit (12). ab The amplitude V of the input voltage is determined in the adaptive α value calculation module. m The calculation formula is derived by using the key waveform of the inductor current during converter operation to obtain the average input current expression and input power balance expression of the converter, and then substituting them into the PF expression of the converter to obtain the PF of the converter with respect to its voltage amplitude V. m And the relationship between the α values, substituting the fixed PF value of the design and the obtained V m Then the corresponding α value can be obtained, realizing the selection of adaptive α value.

[0010] Optionally, the error amplifier circuit (15) consists of a loop compensation circuit (1501), an error amplifier (1502), and a first reference power supply (1503). The loop compensation circuit (1501) is connected in parallel to the negative terminal and the output terminal of the error amplifier (1502). The positive terminal of the error amplifier (1502) is connected to the positive terminal of the first reference power supply (1503). The negative terminal of the first reference power supply (1503) is grounded as the reference voltage terminal of the error amplifier circuit (15). The output terminal of the error amplifier (1502) is the output terminal of the error amplifier circuit (15), and the negative terminal of the error amplifier (1502) is the input terminal of the error amplifier circuit (15).

[0011] Optionally, the sawtooth wave generating circuit (10) includes a charging current source (1601), a timing capacitor C3 (1602), and a switching transistor S3 (1603); the negative terminal of the charging current source (1601) is grounded, and the positive terminal serves as the first input terminal, connected to one end of the switching transistor S5 (1002), the positive terminal of the timing capacitor C3 (1602), and one end of the switching transistor S3 (1603), and outputs to the positive terminal of the voltage comparator (1801); the negative terminal of the timing capacitor C3 (1602) and the other end of the switching transistor S3 (1603) are both grounded; the RS flip-flop (1802) The terminal is connected to the second input terminal of the sawtooth wave generating circuit (16) to control the conduction and cutoff of the switching transistor S3 (1603); the sawtooth wave generating circuit (16) outputs sawtooth wave signals according to the working stage of the main power circuit.

[0012] Optionally, the pulse width modulation circuit (18) includes a voltage comparator (1801), an RS flip-flop (1802), a pulse width counter (1803), a multiplier (1804), a controllable monostable multivibrator (1805), and a logic OR gate (1806). The output terminal of the voltage comparator (1801) is connected to the R terminal of the RS flip-flop (1802), and the S terminal of the RS flip-flop (1802) is connected to the output of the zero-crossing detection circuit (17). The output signal Q of the RS flip-flop (1802) is a relatively short common pulse width signal, referred to as short pulse width v. Drv1 The pulse width counter (1803) is connected to the input of the pulse width meter (1803), the input of the logic OR gate (1806), and the falling edge trigger of the controllable monostable multiplier (1805). The output of the pulse width counter (1803) and the output of the voltage adaptive α value calculation circuit (13) are multiplied by the multiplier (1804) and output to the bottom control terminal of the controllable monostable multiplier (1805). The output of the controllable monostable multiplier (1805) is αv. Drv1 When connected to the input of a logic OR gate (1806), the output of the logic OR gate (1806) is (1+α)v. Drv1 The pulse width is vDrv2 This can generate two pulse width signals that simultaneously activate one of them while delaying its shutdown.

[0013] Optionally, the output voltage balance control circuit (19) includes a subtractor (1901), an absolute value operation module (1902), a reference power supply (1903), a voltage comparator (1904), a D flip-flop (1905), a voltage comparator (1906), and a logic selector (1907), wherein the input terminal of the subtractor (1901) is connected to the sampling capacitor voltage V output by the resistor sampling circuit (14). C1 and V C2 The output of the subtractor is connected to the negative input of the voltage comparator (1904) via the absolute value operation module. The positive terminal of the second reference power supply (1903) is connected to the positive input of the voltage comparator (1904), thereby outputting the control signal of the logic selector (1907). The control terminal of the D flip-flop (1905) is connected to the output of the zero-crossing detection circuit (17), and its D port is connected to the output terminal. The output terminal Q generates high and low level signals that alternate during the switching cycle. The input terminal of the voltage comparator (1906) is connected to the output of the output capacitor voltage differential sampling circuit. The logic selector (1907) selects the signal to pass through the output of the voltage comparator (1904). When the output of the voltage comparator (1904) is high, the output signal of the D flip-flop (1905) is selected to pass through, so that the long and short pulse widths can be alternately turned on by the two switching transistors. Conversely, the output signal of the voltage comparator (1906) is selected to pass through, so that the voltage balance can be adjusted.

[0014] Optionally, the switch selection circuit (20) consists of a logic selector (2001) and a logic selector (2002), wherein the upper path of the logic selector (2001) is connected to the short pulse width v output by the pulse width modulation circuit (18). Drv1 The lower path is connected to the output long pulse width v Drv2 The upper path of the logic selector (2002) is connected to the long pulse width v output of the pulse width modulation circuit (18). Drv2 Short pulse width v Drv1 The lower path is connected to the output short pulse width v Drv1 The function implemented is to output a drive signal v when the output voltage balance control circuit (19) outputs a high level. g1 For short pulse width v Drv1 The output drive signal v g2 For long pulse width v Drv2 When the output voltage balance control circuit (19) outputs a low level, the output drive signal v is... g1 For long pulse width v Drv2 The output drive signal v g2 For short pulse width v Drv1This generates a switch drive signal with voltage balance regulation capability, the drive signal v g1 The drive signal v is connected to the gate of the main power switch S1(5). g2 It is connected to the gate of the main power switch S2(6).

[0015] In summary, due to the adoption of the above technical solutions, the power factor correction converter proposed in this invention can achieve at least the following beneficial effects: (1) It solves the problems of excessively large power inductor L and high stress on subsequent converter devices in traditional two-level Boost PFC converters; (2) Since the three-level topology can realize three-level output, it effectively improves the output voltage level of the circuit, and the two capacitors at the output end have a clamping effect, effectively reducing the common-mode interference of the converter; (3) It solves the problem that the traditional CRM three-level Boost PFC converter uses a fixed α value to limit the efficiency optimization space under high voltage. The increase of the α value under high input voltage reduces the peak inductor current and the operating frequency of the switching transistor, reduces the conduction loss of the converter, improves the efficiency of the converter, and achieves performance improvement. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a three-level Boost PFC converter;

[0018] Figure 2 This is a schematic diagram of the four operating modes of the CRM three-level Boost PFC converter;

[0019] Figure 3 Key operating waveforms of the CRM three-level Boost PFC converter;

[0020] Figure 4 The inductor current of the CRM three-level Boost PFC converter is respectively at the input voltage v in <V o / 2 and v in >V o Key waveform diagram at / 2;

[0021] Figure 5aThis is a waveform diagram showing the operating frequency of a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value as disclosed in an embodiment of the present invention, when operating with a 110V AC power supply, as the α value changes.

[0022] Figure 5b The envelope diagram of the peak inductor current of a critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value disclosed in this embodiment of the invention is shown under different α values ​​when it is operating at 110V and 220V AC power frequency.

[0023] Figure 6a The PF value of a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value disclosed in this embodiment of the invention follows the input voltage amplitude V. m A three-dimensional graph showing the change in α value;

[0024] Figure 6b This invention discloses a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value. When the PF value is fixed at 0.995, the input voltage amplitude V... m The relationship between the value of α and the change in α;

[0025] Figure 7 This is a key waveform diagram illustrating the implementation of an output voltage balance control strategy for a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value, as disclosed in an embodiment of the present invention.

[0026] Figure 8 The input voltage v of a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value disclosed in this embodiment of the invention is... in Input current i in Inductor current i L and output voltage V o Simulation waveform diagram;

[0027] Figure 9 This is a schematic diagram of the main power circuit and control circuit of a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value disclosed in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] 1. Traditional Boost PFC converters suffer from problems such as large power inductor L size and high device stress.

[0030] As mentioned above, while traditional Boost PFC converters are simple in structure and widely used, they also have some inherent problems in practical applications. To achieve low inductor current ripple, a large inductance value is required, which affects the size and weight of the converter. Furthermore, larger inductors inherently have larger parasitic capacitances between windings and higher core losses. In addition, during circuit operation, the switching devices withstand a DC output voltage, requiring the selection of high-voltage-rated devices, which increases the conduction losses of the switching devices and affects the converter efficiency. Based on this, a three-level Boost PFC converter, derived from the traditional Boost PFC converter by combining multi-level conversion technology, has been proposed. Compared to the topology of the traditional Boost PFC converter, it adds a switching transistor, a diode, and a capacitor. Since the voltage across the PFC boost inductor can have three states within one switching cycle, it is called a three-level Boost PFC converter, and its structural diagram is shown below. Figure 1 As shown. This approach increases the equivalent switching frequency of the converter, reduces the required inductance value, and halves the voltage stress on the switching devices. However, current CRM three-level Boost PFC converters typically use a fixed α (i.e., the multiple of the single-switch on-time to the common on-time), which limits the efficiency optimization space under high voltage. Furthermore, the fixed α only uses a single slope combination mode, failing to leverage the adaptive potential of the current slope degree of freedom (DOF) over a wide voltage range given by the multi-level characteristics of three-level Boost.

[0031] Based on this, the present invention proposes a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value, which solves the problem that the traditional CRM three-level Boost PFC converter uses a fixed α value, which limits the efficiency optimization space under high voltage.

[0032] 2. Working principle of a critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value

[0033] Settings: 1. All components are ideal; 2. The output filter capacitor is large enough that the output voltage ripple is very small compared to its DC current; 3. The switching frequency of the switching transistor is much greater than the input AC voltage frequency.

[0034] Within one switching cycle, the converter has four operating modes. Figure 2Four operating mode diagrams of the novel CRM three-level Boost PFC converter based on the adaptive input voltage α value are presented. Figure 4 The inductor current is given at the input voltage v in <V o / 2 and v in >V o The key waveform diagram at / 2. In operating mode 1, switches S1 and S2 are simultaneously turned on, while diodes D1 and D2 are turned off. At this time, the voltage v across inductor L is... L For v in As the inductor L charges and stores more energy, the inductor current i increases. L As the voltage rises linearly, capacitors C1 and C2 release energy, supplying power to the load R. o Provides energy. In operating modes 2 and 3, one of the switching transistors S1 and S2 and diodes D2 and D1 is turned on while the other is turned off. At this time, the voltage v across inductor L is... L For (v in -V o / 2), when v in >V o / 2 inductor current i L As v increases linearly, the energy stored in the inductor L increases with charging. in <V o / 2 inductor current i L The voltage decreases linearly, and the energy stored in inductor L decreases as it discharges. In operating mode 4, both switches S1 and S2 are off, while diodes D1 and D2 are on. At this time, the voltage v across inductor L... L For (v in -V o As the inductor L discharges, its stored energy decreases, and the inductor current i L Linear decrease and in the inductor current i L When the temperature drops to zero, a new cycle begins and repeats continuously to achieve continuous operation of the converter.

[0035] Without loss of generality, the input AC voltage v is defined. in The expression is:

[0036] v in =V m sinωt (1)

[0037] Where V m ω and ω are the amplitude and angular frequency of the input AC voltage, respectively.

[0038] like Figure 4 As shown, the common on-time of the two switches is determined by the short pulse width v g1 Provided, its pulse width length is T on The single switch conduction time t α For αT onThe pulse width v can be obtained. g2 The length is (1+α)T on The switch-off time t can be calculated based on the volt-second balance characteristic. off for:

[0039]

[0040] Where V o This is the output voltage.

[0041] like Figure 4 As shown, the peak value of the converter inductor current i Lpeak At input voltage v in >V o / 2 and input voltage v in <V o Substituting / 2 into equation (2) above, we can obtain:

[0042]

[0043] Where V o V is the output voltage. m Where L is the input voltage amplitude and L is the power inductance value.

[0044] Combination Figure 4 Then, according to equations (2) and (3), the converter at the input voltage v can be calculated. in >V o / 2 and input voltage v in <V o When / 2, its input current i in All are:

[0045]

[0046] Assuming the converter efficiency is 100%, i.e., the input power equals the output power, the average input power P of the converter over half a power frequency cycle can be calculated using equations (1) and (4). in for:

[0047]

[0048] Therefore, the common conduction time T can be obtained. on The expression is:

[0049]

[0050] Combining equations (2) and (6), the operating frequency f of the converter can be obtained. sw for:

[0051]

[0052] According to the expression shown in equation (7) above, substituting α=0 and α=1 respectively, the operating frequency f of the converter under a power frequency of 110V AC voltage is... sw The change curve is as follows Figure 5a As shown, it can be seen that as the value of α increases, its operating frequency f sw Significantly reduced.

[0053] Combining equations (3) and (6), the peak value of the converter inductor current i can be obtained. Lpeak for:

[0054]

[0055] According to the expression shown in equation (8) above, when α = 0, α = 1 and α = 1 respectively, the peak value of the inductor current i of the converter under the power frequency AC voltage of 110V and 220V respectively is obtained. Lpeak The curve of the envelope variation is shown below. Figure 5b As shown, it can be seen that as the value of α increases, the peak value of the inductor current i Lpeak Significantly reduced.

[0056] Based on equations (4) and (5), we can obtain PF with respect to the input voltage amplitude V. m The relationship between α and α is expressed as follows:

[0057]

[0058] Where i in_rms This is the effective value of the input current;

[0059] According to the above formula (9), the PF value of the converter following the input voltage amplitude V can be plotted. m The three-dimensional plot of the change in α value is attached. Figure 6a As shown, it can be seen that with the increase of input voltage amplitude V m As the α value increases, the impact of changes in the PF value on the converter gradually decreases. Based on this, it is proposed that, under the premise of a fixed PF value of 0.995, the input voltage amplitude V can be obtained through formula (9). m The relationship between the change and the value of α is as follows Figure 6b As shown, this achieves efficiency optimization by enabling the selection of an adaptive α value based on the input voltage.

[0060] The control circuit is implemented by first using a voltage adaptive α value calculation circuit based on the corresponding input voltage amplitude V. m The corresponding α value is generated, and then the output control signal of the average current control loop is compared with the sawtooth wave signal generated by the sawtooth wave generation circuit to generate a reset signal. The set signal generated by the zero current detection circuit, along with the set signal generated by the RS flip-flop, generates a short pulse width v for the common conduction time. Drv1 Then, in the pulse width modulation circuit, the corresponding α value and short pulse width v are used...Drv1 Generate long pulse width v Drv2 Then, under the control of the output voltage balancing control circuit, the two pulse width signals are used as switching transistor drive signals in the switching selection circuit and applied to the two switching transistors in a controlled manner, thereby realizing the control of the converter.

[0061] Test conditions were set as follows: effective input voltage values ​​of 220V and 110V, frequency f = 50Hz, power inductance L = 200uH, output voltage 400V, and output power 300W. The input voltage v of the novel CRM three-level Boost converter based on adaptive input voltage α value disclosed in this embodiment of the invention was obtained. in Input current i in Inductor current i L and output voltage V o The simulation waveform is as follows Figure 8 As shown in the figure. The curve for selecting the adaptive α value is as follows. Figure 6b As shown, with the input voltage amplitude V m As the value of α increases, the corresponding value of α also increases, and the increase in the value of α leads to a decrease in the peak inductor current and the operating frequency. Figure 5a and Figure 5b As shown, this can reduce switching losses.

[0062] Based on the above analysis, it can be seen that the conversion circuit and its control method proposed in this invention can further improve the efficiency of the converter while maintaining a high power factor.

[0063] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0065] The above provides a detailed description of a critical conduction mode three-level Boost PFC converter based on an adaptive input voltage α value provided by the present invention. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value, characterized in that, It includes a main power circuit and a control circuit. The main power circuit includes an AC source, an EMI filter, a rectifier bridge, a power inductor L, series-connected switching transistors S1 and S2, diodes D5 and D6, series-connected output filter capacitors C1 and C2, and a load R. o The control circuit includes a differential sampling circuit, a voltage adaptive α value calculation circuit, a resistance sampling circuit, an error amplification circuit, a sawtooth wave generation circuit, a zero-crossing detection circuit, a pulse width modulation circuit, an output voltage balance control circuit, and a switch selection circuit. The main power circuit includes an AC source (1), an EMI filter (2), a rectifier bridge (3), a power inductor L (4), series-connected switching transistors S1 (5) and S2 (6), diodes D5 (7) and D6 (8), series-connected output filter capacitors C1 (9) and C2 (10), and a load R. o (11); The AC source (1) is connected to the input port of the EMI filter (2), and the output port of the EMI filter (2) is output through the rectifier bridge (3); The rectifier bridge (3) is composed of diodes D1 (301), D2 (302), D3 (303), and D4 (304). The upper end of the rectifier bridge output port is connected in series with the positive terminal of the power inductor L (4), and its negative terminal is connected to the source of the switch S1 (5) and the anode of the diode D5 (7). The switch S1 (5) S2(6) is connected in series, and the lower end of the rectifier bridge output port is connected to the drain of the switching transistor S2(6) and the cathode of the diode D6(8); the output filter capacitors C1(9) and C2(10) are connected in series, the positive terminal of C1(9) is connected to the cathode of the diode D5(7), the negative terminal of C2(10) is connected to the anode of the diode D6(8), and the connection point of the negative terminal of the output filter capacitor C1(9) and the positive terminal of C2(10) is connected to the connection point of the drain of the switching transistor S1(5) and the source of S2(6); the load R o (11) The two ends are connected to the positive terminal of the output filter capacitor C1(9) and the negative terminal of C2(10), respectively; The control circuit includes a differential sampling circuit (12), a voltage adaptive α value calculation circuit (13), a resistance sampling circuit (14), an error amplification circuit (15), a sawtooth wave generation circuit (16), a zero-crossing detection circuit (17), a pulse width modulation circuit (18), an output voltage balance control circuit (19), and a switch selection circuit (20). The input terminal of the differential sampling circuit (12) is connected to the output port of the rectifier bridge (3) for sampling the input voltage. The input terminal of the voltage adaptive α value calculation circuit (13) is connected to the output terminal of the differential sampling circuit (12) for generating an adaptive α value to be fed into the pulse width modulation circuit (18). The resistance sampling circuit (14) includes sampling resistors R5 (1401) and R6 (1402) for sampling the output voltage V. o Sampling resistors R7 (1403) and R8 (1404) are used to sample the voltage V of filter capacitor C2 (10). C1 R5(1401) = R7(1403), R6(1402) = R8(1404), and subtractor (1405) are used to calculate the sampling voltage V of filter capacitor C1(9). C2 The error amplifier circuit (15) includes a loop compensation circuit (1501), an error amplifier (1502), and a first reference power supply (1503). Its input terminal is connected to the output voltage V sampled by the resistor sampling circuit (14). o The error signal V used to output the output voltage of the main power circuit. comp The sawtooth wave generation circuit (16) generates a sawtooth wave signal by repeatedly charging and discharging the capacitor using a DC source, and its output is connected to the positive terminal of the voltage comparator (1801); the zero-crossing detection circuit (17) generates a ZCD signal by detecting the inductor voltage, and generates a zero-crossing signal through the zero-current detection circuit, which is then connected to the pulse width modulation circuit (18); the pulse width modulation circuit (18) includes a voltage comparator (1801), an RS flip-flop (1802), a pulse width counter (1803), a multiplier (1804), a controllable monostable multivibrator (1805), and a logic OR gate (1806), used to generate two pulse width signals that simultaneously activate one of which is delayed and deactivated; the output voltage balance The control circuit (19) includes a subtractor (1901), an absolute value operation module (1902), a second reference power supply (1903), a voltage comparator (1904), a D flip-flop (1905), a voltage comparator (1906), and a logic selector (1907). When the voltage difference between the two output capacitors exceeds a certain limit, i.e., the output voltage is unbalanced, a pulse width selection signal with voltage balance adjustment is generated and sent to the control terminal of the logic selector of the switch selection circuit (20). The switch selection circuit (20) is composed of a logic selector (2001) and a logic selector (2002), which can generate a switch drive signal with voltage balance adjustment capability and send it to the gate of each switch transistor.

2. The critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value according to claim 1, characterized in that, The input terminal of the voltage adaptive α value calculation circuit (13) is connected to the V output of the differential sampling circuit (12). ab The amplitude V of the input voltage is determined in the adaptive α value calculation module. m The calculation formula is derived by using the key waveform of the inductor current during converter operation to obtain the average input current expression and input power balance expression of the converter, and then substituting them into the PF expression of the converter to obtain the PF of the converter with respect to its voltage amplitude V. m And the relationship between the α values, substituting the fixed PF value of the design and the obtained V m Then the corresponding α value can be obtained, realizing the selection of adaptive α value.

3. The critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value according to claim 1, characterized in that, The error amplifier circuit (15) consists of a loop compensation circuit (1501), an error amplifier (1502), and a first reference power supply (1503). The loop compensation circuit (1501) is connected in parallel to the negative terminal and the output terminal of the error amplifier (1502). The positive terminal of the error amplifier (1502) is connected to the positive terminal of the first reference power supply (1503). The negative terminal of the first reference power supply (1503) is grounded as the reference voltage terminal of the error amplifier circuit (15). The output terminal of the error amplifier (1502) is the output terminal of the error amplifier circuit (15), and the negative terminal of the error amplifier (1502) is the input terminal of the error amplifier circuit (15).

4. The critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value according to claim 1, characterized in that, The sawtooth wave generating circuit (10) includes a charging current source (1601), a timing capacitor C3 (1602), and a switching transistor S3 (1603). The negative terminal of the charging current source (1601) is grounded, and the positive terminal serves as the first input terminal, connected to one end of the switching transistor S5 (1002), the positive terminal of the timing capacitor C3 (1602), and one end of the switching transistor S3 (1603), and outputs to the positive terminal of the voltage comparator (1801). The negative terminal of the timing capacitor C3 (1602) and the other end of the switching transistor S3 (1603) are both grounded. The RS flip-flop (1802)... The terminal is connected to the second input terminal of the sawtooth wave generating circuit (16) to control the conduction and cutoff of the switching transistor S3 (1603); the sawtooth wave generating circuit (16) outputs sawtooth wave signals according to the working stage of the main power circuit.

5. The critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value according to claim 1, characterized in that, The pulse width modulation circuit (18) includes a voltage comparator (1801), an RS flip-flop (1802), a pulse width counter (1803), a multiplier (1804), a controllable monostable multivibrator (1805), and a logic OR gate (1806). The output terminal of the voltage comparator (1801) is connected to the R terminal of the RS flip-flop (1802), and the S terminal of the RS flip-flop (1802) is connected to the output of the zero-crossing detection circuit (17). The output signal Q of the RS flip-flop (1802) is a relatively short common pulse width signal, referred to as short pulse width v. Drv1 The pulse width counter (1803) is connected to the input of the pulse width counter (1803), the input of the logic OR gate (1806), and the falling edge trigger of the controllable monostable multiplier (1805). The output of the pulse width counter (1803) and the output of the voltage adaptive α value calculation circuit (13) are multiplied by the multiplier (1804) and output to the bottom control terminal of the controllable monostable multiplier (1805). The output of the controllable monostable multiplier (1805) is αv. Drv1 When connected to the input of a logic OR gate (1806), the output of the logic OR gate (1806) is (1+α)v. Drv1 The pulse width is v Drv2 This can generate two pulse width signals that simultaneously activate one of them while delaying its shutdown.

6. The critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value according to claim 1, characterized in that, The output voltage balance control circuit (19) includes a subtractor (1901), an absolute value operation module (1902), a reference power supply (1903), a voltage comparator (1904), a D flip-flop (1905), a voltage comparator (1906), and a logic selector (1907). The input terminal of the subtractor (1901) is connected to the sampling capacitor voltage V output by the resistor sampling circuit (14). C1 and V C2 The output of the subtractor is connected to the negative input of the voltage comparator (1904) via the absolute value operation module. The positive terminal of the second reference power supply (1903) is connected to the positive input of the voltage comparator (1904), thereby outputting the control signal of the logic selector (1907). The control terminal of the D flip-flop (1905) is connected to the output of the zero-crossing detection circuit (17), and its D port is connected to the output terminal. The output terminal Q generates high and low level signals that alternate during the switching cycle. The input terminal of the voltage comparator (1906) is connected to the output of the output capacitor voltage differential sampling circuit. The logic selector (1907) selects the signal to pass through the output of the voltage comparator (1904). When the output of the voltage comparator (1904) is high, the output signal of the D flip-flop (1905) is selected to pass through, so that the long and short pulse widths can be alternately turned on by the two switching transistors. Conversely, the output signal of the voltage comparator (1906) is selected to pass through, so that the voltage balance can be adjusted.

7. The critical conduction mode three-level Boost PFC converter based on adaptive input voltage α value according to claim 1, characterized in that, The switch selection circuit (20) consists of a logic selector (2001) and a logic selector (2002), wherein the upper path of the logic selector (2001) is connected to the short pulse width v output by the pulse width modulation circuit (18). Drv1 The lower path is connected to the output long pulse width v Drv2 The upper path of the logic selector (2002) is connected to the long pulse width v output of the pulse width modulation circuit (18). Drv2 Short pulse width v Drv1 The lower path is connected to the output short pulse width v Drv1 The function implemented is to output a drive signal v when the output voltage balance control circuit (19) outputs a high level. g1 For short pulse width v Drv1 The output drive signal v g2 For long pulse width v Drv2 When the output voltage balance control circuit (19) outputs a low level, the output drive signal v is... g1 For long pulse width v Drv2 The output drive signal v g2 For short pulse width v Drv1 This generates a switch drive signal with voltage balance regulation capability, the drive signal v g1 The drive signal v is connected to the gate of the main power switch S1(5). g2 It is connected to the gate of the main power switch S2(6).

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