Clock signal generator, on-chip clock system and chip

Abstract

A clock signal generator (100), an on-chip clock system and a chip wherein the clock signal generator (100) comprises: a first transistor (T1), a second transistor (T2), a trigger and a power supply terminal; first poles of the first transistor (T1) and the second transistor (T2) are coupled to a power supply end, and second poles of the first transistor (T1) and the second transistor (T2) are coupled to a common ground (Gnd); the first input end of the trigger is coupled to the first pole of the first transistor (T1), and the second input end of the trigger is coupled to the first pole of the second transistor (T2). The clock signal generator (100) can make the frequency of the output clock signal more stable.

Description

[0001] This application is a divisional application. The original application has the application number 202080093156.2 and the original application date is January 16, 2020. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to electronic circuit technology, and more particularly to a clock signal generator, an on-chip clock system, and a chip. Background Technology

[0003] With the development of electronic technologies such as artificial intelligence, communication, and semiconductors, the functions of on-chip systems are becoming increasingly complex. To ensure the high reliability and high operating speed of on-chip systems, it is usually necessary to have an internal clock signal generator to provide an accurate and stable clock signal.

[0004] In related technologies, clock signal generators typically include flip-flops and comparators. The signal output from the comparator is provided to the input of the flip-flop, causing the flip-flop to generate a clock pulse at its output based on the received signal. Typically, there is a time delay between the input and output of the comparator. This delay varies depending on factors such as the circuit's static operating point and temperature drift, causing variations in the clock frequency output by the clock output circuit and reducing the frequency stability of the clock signal generated by the clock signal generator. Therefore, how to ensure a stable clock signal output from the clock signal generator becomes a problem. Summary of the Invention

[0005] The clock signal generator, on-chip clock system, and chip provided in this application, by coupling the input terminals of the flip-flops to the first terminals of the first transistor and the second transistor respectively, enable the output frequency of the clock signal generator to be related only to the on-off time of the first transistor and the second transistor, thereby enabling the clock signal generator to generate a clock signal with a stable frequency.

[0006] The technical solution adopted in this application is as follows:

[0007] In a first aspect, embodiments of this application provide a clock signal generator, which includes a first transistor, a second transistor, a flip-flop, and a power supply terminal; the first terminals of the first transistor and the second transistor are coupled to the power supply terminal, and the second terminals of the first transistor and the second transistor are coupled to the common ground; the first input terminal of the flip-flop is coupled to the first terminal of the first transistor, and the second input terminal of the flip-flop is coupled to the first terminal of the second transistor.

[0008] By coupling the first and second input terminals of the flip-flop to the first and second terminals of the first and second transistors, respectively, the high-level or low-level signals received by the first and second input terminals of the flip-flop are only related to the on-time or off-time of the first and second transistors. Consequently, the period or frequency of the clock pulse signal at the output terminal of the flip-flop is only related to the on-time and off-time of the first and second transistors. This avoids the clock frequency changing due to temperature variations in the time delay of the signal received by the flip-flop, thus making the frequency of the clock signal output by the clock signal generator more stable.

[0009] In one possible implementation, the clock signal generator further includes a control signal generation circuit; the output of the control signal generation circuit is coupled to the control electrode of the first transistor and the control electrode of the second transistor, respectively; the control signal generation circuit periodically provides control signals to the control electrodes of the first transistor and the second transistor, so that the first transistor and the second transistor alternately turn on and off based on the control signals.

[0010] In one possible implementation, the control signal output by the control signal generation circuit is a voltage signal. In this case, the control signal generation circuit may include two output terminals, one coupled to the control electrode of the first transistor and the other coupled to the control electrode of the second transistor. The control signal generation circuit can apply the generated voltage signal between the control electrode and the first electrode of the first transistor, and between the control electrode and the second electrode of the second transistor, to alternately control the on and off states of the first and second transistors.

[0011] In one possible implementation, the clock signal generator further includes a first capacitor and a second capacitor; a first terminal of the first capacitor is coupled to the control terminal of the first transistor, and a second terminal of the first capacitor is coupled to the common ground; the first transistor periodically turns on or off based on the charging and discharging of the first capacitor; a first terminal of the second capacitor is coupled to the control terminal of the second transistor, and a second terminal of the second capacitor is coupled to the common ground; the second transistor periodically turns on or off based on the charging and discharging of the second capacitor.

[0012] The charging and discharging of the first and second capacitors controls the first and second transistors, thereby triggering the level switching of the first and second output terminals of the flip-flop to generate a clock signal. The charging and discharging time of the capacitors is related to their material, capacitance, and charging / discharging constant. Therefore, by controlling the charging and discharging time of the first and second capacitors, the clock frequency output by the clock signal generator can be controlled, avoiding changes in the frequency of the output clock signal caused by temperature drift and changes in the static operating point of other devices in the clock signal generator, such as integrated operational amplifiers. This results in a more stable clock signal frequency. Furthermore, in some applications, when a higher clock frequency is required, a capacitor with a small capacitance and fast charging / discharging time can be used; when a lower clock frequency is required, a capacitor with a large capacitance and slow charging / discharging time can be used. This effectively increases the maximum frequency of the clock signal output by the clock signal generator, thereby improving the performance of the clock signal generator. The control signal output from the control signal generation circuit is a current signal. The control signal generation circuit periodically and alternately provides this current signal to the first terminal of the first capacitor and the first terminal of the second capacitor to charge the first and second capacitors, respectively.

[0013] In one possible implementation, the clock signal generator further includes a third transistor; the control electrode and the first electrode of the third transistor are coupled to the power supply terminal, and the second electrode is coupled to the common ground; the control signal generation circuit generates a current signal based on the voltage signal between the first electrode and the second electrode of the third transistor.

[0014] In one possible implementation, the clock signal generator further includes a current mirror circuit; the control signal generation circuit converts the voltage between the first and second terminals of the third transistor into a current and provides it to the current mirror circuit; the current mirror circuit mirrors the received current based on a preset ratio and provides the processed current to the first terminal of the first capacitor and the first terminal of the second capacitor.

[0015] By setting up a current mirror circuit, the requirements for the control signal generation circuit can be reduced. When the clock signal generator needs to input a large current, this can be achieved through the current mirror circuit, thereby improving the stability of the control signal generation circuit and thus improving the stability of the clock signal generated by the clock signal generator.

[0016] In one possible implementation, the clock signal generator further includes a first selector and a second selector; the control terminal of the first selector is coupled to the first output terminal of the flip-flop, the first input terminal of the first selector is coupled to the output terminal of the control signal generation circuit, the second input terminal of the first selector is coupled to the common ground, and the output terminal of the first selector is coupled to the control electrode of the first transistor; the control terminal of the second selector is coupled to the second output terminal of the flip-flop, the first input terminal of the second selector is coupled to the output terminal of the control signal generation circuit, the second input terminal of the second selector is coupled to the common ground, and the output terminal of the second selector is coupled to the control electrode of the second transistor; under the control of the clock signal output from the first output terminal of the flip-flop, the first selector periodically selects the first and second input terminals of the first selector to cause the first capacitor to charge and discharge periodically; under the control of the clock signal output from the first output terminal of the flip-flop, the second selector periodically selects the first and second input terminals of the second selector to cause the second capacitor to charge and discharge periodically.

[0017] In one possible implementation, the first input of the flip-flop is coupled to the first pole of the second transistor via an even number of inverters.

[0018] In one possible implementation, the second input of the flip-flop is coupled to the first pole of the third transistor via an even number of inverters.

[0019] By adding an inverter, the driving capability of the circuit can be improved, thereby increasing the switching speed of the level signals at the first and second input terminals of the flip-flop.

[0020] In one possible implementation, the number of the first transistor, the number of the second transistor, and the number of the third transistor are proportional. For example, the ratio of the first transistor to the third transistor is 1:1:1. The parameters of the first transistor, the second transistor, and the third transistor are identical. Specifically, the first transistor, the second transistor, and the third transistor can have the same physical and operating parameters, i.e., the on-state voltage drop, internal resistance, power, etc. are the same. This reduces the temperature drift of the clock signal generator's quiescent operating point, making the quiescent operating point of the clock signal generator more stable.

[0021] Secondly, embodiments of this application provide an on-chip clock system, which includes a clock signal generator as described in the first aspect.

[0022] Thirdly, embodiments of this application provide a chip that includes an on-chip clock system as described in the second aspect. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a clock circuit in the prior art;

[0025] Figure 2 This is a schematic diagram of the structure of a clock signal generator provided in an embodiment of this application;

[0026] Figure 3 This is yet another structural schematic diagram of the clock signal generator provided in the embodiments of this application;

[0027] Figure 4 This is yet another structural schematic diagram of the clock signal generator provided in the embodiments of this application;

[0028] Figure 5 This is a schematic diagram of a voltage-to-current conversion circuit provided in an embodiment of this application;

[0029] Figure 6 This is yet another structural schematic diagram of the clock signal generator provided in the embodiments of this application;

[0030] Figure 7 This is a schematic diagram of the specific structure of the clock signal generator provided in the embodiments of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "coupled," "connected," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0033] The term "unit" as used in this article usually refers to a functional structure that is logically divided. This "unit" can be implemented purely in hardware or a combination of hardware and software.

[0034] In the implementation of this application, "and / or" describes the relationship between related objects, indicating that there can be three kinds of relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0035] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0036] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0037] Please refer to Figure 1 , Figure 1 A typical clock circuit in the prior art is shown. For example... Figure 1 As shown, the clock circuit includes a voltage-to-current conversion unit 01 for converting voltage signals into current signals and a clock signal unit 02 for generating clock signals. The voltage-to-current conversion unit 01 is the preceding stage of the clock circuit. Its integrated operational amplifier B1 converts voltage into current and provides it to the gate of transistor A1, thereby inputting a signal to the clock signal unit 02 through transistor A1. The clock signal unit 02 is the following stage of the clock circuit. It contains two comparators C1 and C2 for generating trigger signals for the SR flip-flop. Figure 1As can be seen, one of the signal input terminals of comparators C1 and C2 is connected to the drain of transistors A3 and A4, respectively. The gates of transistors A3 and A4 are controlled by the drain current of transistor A1. This makes the signal used to trigger the SR flip-flop dependent on the voltage-to-current conversion circuit 01 and the signals output by comparators C1 and C2. Consequently, the clock signal CLK generated by the SR flip-flop follows the current generated by the integrated operational amplifier B1 and the signals output by comparators C1 and C2. When the signal VREF input to the integrated operational amplifier B1 or the devices in the voltage-to-current conversion unit 01 change with temperature or power supply variations, the clock signal CLK also changes accordingly. This significantly reduces the stability of the clock signal output by the clock circuit. Furthermore, the output signals of comparators C1 and C2 typically have a time delay compared to the input signals. This delay usually limits the highest frequency of the clock signal output by the clock circuit. Therefore, the clock signal generator provided in this application embodiment does not require a comparator. It generates a clock signal by controlling the first and second transistors to turn on or off. The frequency of the clock signal is only related to the on and off times of the first and second transistors. By stably controlling the on and off times of the first and second transistors, a stable clock signal can be output. Furthermore, in some implementations provided in this application embodiment, using the charging and discharging of a capacitor to control the on and off times of the first and second transistors ensures that the on and off times of the first and second transistors are not affected by the delay or temperature drift of the integrated operational amplifier in the voltage-to-current conversion unit. This further increases the maximum frequency of the clock signal output by the clock circuit.

[0038] Please refer to Figure 2 This shows a schematic diagram of the clock signal generator provided in an embodiment of this application.

[0039] exist Figure 2 In the clock signal generator 100, there is a power supply terminal Vdd and a clock signal generation circuit 10. The clock signal generation circuit 10 includes transistor T1, transistor T2, and SR flip-flop.

[0040] In this embodiment, transistors T1 and T2 each include a control electrode, a first electrode, and a second electrode. The first electrodes of transistors T1 and T2 are coupled to the power supply terminal Vdd. This power supply terminal Vdd is used to receive externally supplied electrical energy. The second electrodes of transistors T1 and T2 are coupled to the common ground Gnd. Transistors T1 and T2 can be insulated-gate field-effect transistors, such as PMOS transistors or NMOS transistors, and are not limited thereto. When transistors T1 and T2 are NMOS transistors, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; when transistors T1 and T2 are PMOS transistors, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain. The figure schematically illustrates the case where transistors T1 and T2 are NMOS transistors.

[0041] The SR flip-flop includes input terminal S, input terminal R, output terminal QN, and output terminal Q. The input terminal S of the SR flip-flop is connected to the first terminal of transistor T1, the input terminal R of the SR flip-flop is connected to the first terminal of transistor T2, and the output terminal QN or output terminal Q of the SR flip-flop is used to output a clock signal. Figure 2 The diagram schematically illustrates the situation where the output Q of the SR flip-flop outputs a clock signal. That is, the clock signal generator 100 outputs the clock signal through the external interface Clk_out. During the operation of the SR flip-flop, when the level or logic signal currently received at the inputs S and R of the SR flip-flop differs from the previously received level or logic signal, it triggers a transition in the level signals at the outputs QN and Q of the SR flip-flop. To make the signal output by the clock signal generator 100 more stable, typically, the inputs S and R of the SR flip-flop receive signals of different levels or different logic at the same time. That is, when input S receives "logic 0", input R receives "logic 1"; when input S receives "logic 1", input R receives "logic 0".

[0042] like Figure 2 As shown, the clock signal generator 100 may further include a control signal generation circuit 20 for controlling the on and off states of transistors T1 and T2. This control signal generation circuit 20 may include, but is not limited to, a programmable logic controller (PLC), a digital signal processor (DSP), or a signal generator. The output terminals of the control signal generation circuit 20 are coupled to the control terminals of transistors T1 and T2, respectively.

[0043] Specifically, such as Figure 2As shown, the control signal generation circuit 20 may include two output terminals, one of which is coupled to the control electrode of transistor T1, and the other output terminal is coupled to the control electrode of transistor T2. Here, the signal output by the control signal generation circuit 20 can be a voltage signal. Taking transistor T1 as an example, the control signal generation circuit 20 can be coupled to the second electrode of transistor T1 to the same common ground, thereby applying a voltage signal between the control electrode and the second electrode of transistor T1. When this voltage signal is greater than the turn-on voltage of transistor T1, transistor T1 is turned on; when the voltage signal is stopped, transistor T1 is turned off. In this embodiment, the control signal generation circuit 20 can control transistors T1 and T2 to alternately turn on and off. That is, when transistor T1 is on, transistor T2 is off; when transistor T2 is on, transistor T2 is off. Thus, the input terminal S and output terminal R of the SR flip-flop can alternately receive signals of different levels.

[0044] Combination Figure 2 The circuit structure shown illustrates the working principle of the clock signal generator 100 shown in the embodiment of this application.

[0045] Taking the operating state of transistor T1 as an example, the signal received at the input terminal S of the SR flip-flop is first explained. When transistor T1 is turned on, the potential at node a is the voltage drop across the internal resistance of transistor T1. Typically, the voltage drop across the internal resistance of transistor T1 is very small and almost negligible; here, the potential at node a can be considered as 0V. At this time, the input terminal S of the SR flip-flop receives a low-level signal or "logic 0". When transistor T1 is turned off, the potential at node a is the potential of the power supply terminal Vdd. At this time, the input terminal S of the SR flip-flop receives a high-level signal or "logic 1". The operating state of transistor T2 and the signal received at the input terminal R of the SR flip-flop are described in the description of the signals received at the input terminal S of transistors T1 and SR flip-flops, and will not be repeated here.

[0046] In the first time period, control transistor T1 is turned on and control transistor T2 is turned off. At this time, the input S of the SR flip-flop receives a low-level signal or "logic 0", and the input R of the SR flip-flop receives a high-level signal or "logic 1". The Q output is a low-level signal or "logic 0". In the second time period, control transistor T1 is turned off and control transistor T2 is turned on. At this time, the input S of the SR flip-flop receives a high-level signal or "logic 1", and the input R of the SR flip-flop receives a low-level signal or "logic 0". The Q output is a high-level signal or "logic 1". Therefore, by periodically controlling transistors T1 and T2 to turn on or off based on the desired clock cycle, the output Q of the SR flip-flop can alternately output high and low-level signals, i.e., clock pulse signals.

[0047] from Figure 2 As can be seen from the embodiments of this application, by connecting the input terminals S and R of the SR flip-flop to the first terminals of transistors T1 and T2 respectively, the signals input to the input terminals S and R of the SR flip-flop can be separated from the control signals that control the transistors T1 and T2 to turn on or off. Figure 1 Compared to the clock circuit shown where the comparator's output is connected to the SR flip-flop's input, in this embodiment, the period or frequency of the clock pulse signal at the SR flip-flop's output is only related to the on-time and off-time of transistors T1 and T2. By stably controlling the on-time and off-time of transistors T1 and T2, a stable clock signal can be output from the SR flip-flop, avoiding changes in clock frequency due to temperature variations in the comparator's output signal delay, thus making the clock signal output by the clock signal generator 100 more stable. The signals applied to the control electrodes of the first transistor T1 and the second transistor T2 can also be achieved through the charging and discharging of capacitors. Specifically, see [link to relevant documentation]. Figure 3 This shows a schematic diagram of the structure of another clock signal generator provided in an embodiment of this application.

[0048] like Figure 3 As shown, capacitor C1 is connected between the control electrode of transistor T1 and the common ground Gnd, and capacitor C2 is connected between the control electrode of transistor T2 and the common ground Gnd. The control signal generation circuit 20 can have an internal switch to charge and discharge capacitors C1 and C2. When the control signal generation circuit 20 charges capacitors C1 and C2, the control signal output by the control signal generation circuit 20 is a current signal. Taking capacitor C1 as an example, when the control signal generation circuit 20 inputs a current signal to capacitor C1, capacitor C1 charges, and the potential at point n1 gradually rises. When the potential at point n1 rises to a certain value, making the voltage between the control electrode and the second electrode of transistor T1 greater than the turn-on voltage, transistor T1 turns on. When the current signal generation terminal inside the control signal generation circuit 20 switches to a low potential terminal (e.g., the common ground terminal), capacitor C1 discharges. Under the action of capacitor C1, the potential at point n1 does not change abruptly. When capacitor C1 discharges to a certain value, making the voltage of transistor T1 less than the turn-on voltage, transistor T1 turns off. When capacitor C1 charges, capacitor C2 discharges; when capacitor C2 charges, capacitor C1 discharges. Thus, by controlling the alternating charging and discharging of capacitors C1 and C2, the alternating on and off of transistors T1 and T2 is achieved. In one possible implementation, the clock signal generator 100 further includes a third transistor T3, such as... Figure 4 As shown. In Figure 4In this circuit, transistor T3 can be an NMOS transistor, PMOS transistor, etc., and is not limited here. The control electrode and first electrode of transistor T3 are coupled to the power supply terminal Vdd. This power supply terminal Vdd is used to receive externally supplied power. The second electrode of transistor T3 is coupled to the common ground Gnd. When external power from the clock signal generator 100 is supplied to the control electrode and first electrode of transistor T3 through the power supply terminal Vdd, the voltage between the control electrode and the second electrode of transistor T3 is greater than the turn-on voltage, and transistor T3 turns on. At this time, Figure 4 The potential at node b in the transistor is equal to the voltage drop between the first and second terminals of transistor T3. Figure 4 In this circuit, as long as the voltage difference between the power supplied by the power supply terminal Vdd and the common ground Gnd is greater than the turn-on voltage of transistor T3, the transistor can operate in the on state, and changes in the power supply signal will not have a significant impact on the potential of node b. Therefore, by setting transistor T3, a stable voltage signal can be provided to the control signal generation circuit 20, thereby enabling the control signal generation circuit 20 to provide a stable current signal to the clock signal generation circuit 10.

[0049] exist Figure 4 In the circuit, the control signal generation circuit 20 can convert the voltage signal between the first and second terminals of transistor T3 into a current signal, which is then alternately supplied to... Figure 3 The capacitors C1 and C2 are shown.

[0050] In this implementation, the control signal generation circuit 20 can be a circuit where the output current is proportional to the input voltage. Any existing circuit capable of achieving a proportional relationship between output current and input voltage can be the control signal generation circuit 20 shown in this application; no specific limitation is made here. Specifically, the control signal generation circuit 20 can be... Figure 5 The structure shown. In Figure 5 In the control signal generation circuit shown, the output current of the integrated operational amplifier B1 is the sum of the bias voltage of the integrated operational amplifier and the potential of node b, divided by the resistance value of resistor R. By setting the bias voltage of integrated operational amplifier B1 and the resistance value of resistor R, the output current of integrated operational amplifier B1 can be made to have a certain proportional relationship with the potential of node b.

[0051] In some alternative implementations, the clock signal generator 100 may also include a current mirror circuit 30, such as... Figure 6 As shown, Figure 6A schematic diagram showing the connection relationship between the current mirror circuit 30 and other circuit components is provided. The output terminal of the control signal generation circuit 20 is coupled to the input terminal of the current mirror circuit 30, and the output terminal of the current mirror circuit 30 is coupled to the control terminals of transistors T1 and T2 in the clock signal generation circuit 10. After mirroring the received current signal, the current mirror circuit 30 provides the current signal to capacitors C1 and C2 in the clock signal generation circuit 10 through its output terminal. The control signal generation circuit 20 can be a circuit that realizes a proportional relationship between the output current and the input voltage, for example... Figure 5 The circuit structure of the control signal generation circuit 20 is shown. The current mirror circuit 30 can be a current mirror circuit that mirrors the current at a preset ratio, or a circuit that amplifies the current at a preset ratio. For example, the current ratio between the input and output terminals of the current mirror circuit is 1:N. Here, N is an integer greater than or equal to 1. That is to say, in this optional implementation, the current mirror circuit 30 mirrors the current input to the control signal generation circuit 20 at a preset ratio and provides the processed current to the clock signal generation circuit 10.

[0052] In this optional implementation, by setting the current mirror circuit 30, the requirements on the control signal generation circuit 20 can be reduced. When the clock signal generation circuit 10 needs to input a large current, it can be achieved through the current mirror circuit 30, thereby improving the stability of the control signal generation circuit 20 and thus improving the stability of the clock signal generated by the clock signal generator 100.

[0053] The following is combined with Figure 7 The specific structure of the clock signal generator 100 provided in the embodiments of this application will be described.

[0054] exist Figure 7 In the clock signal generator 100, there are clock signal generation circuit 10, control signal generation circuit 20, current mirror circuit 30, transistor T3, power supply terminal Vdd, and clock signal output terminal Clk_out. The clock signal generation circuit 10 includes transistor T1, transistor T2, SR flip-flop, capacitor C1, and capacitor C2. The connection relationships between the components in the clock signal generation circuit 10 can be found in [reference needed]. Figure 2 , Figure 3 For related descriptions, the structure and connection relationships of each unit in the control signal generation circuit 20 and the current mirror circuit 30, please refer to... Figures 4-6 The relevant descriptions will not be repeated here.

[0055] like Figure 7In the clock signal generator 100 shown, the clock signal generation circuit 10 further includes selectors M1 and M2. The control terminal k1 of selector M1 is coupled to the output terminal QN of the SR flip-flop; the input terminal d1 of selector M1 is coupled to the output terminal of the current mirror circuit 30; the input terminal d2 of selector M1 is coupled to the common ground Gnd; and the output terminal o1 of selector M1 is coupled to the control terminal of transistor T1. The control terminal k2 of selector M2 is coupled to the output terminal Q of the SR flip-flop; the input terminal d3 of selector M2 is coupled to the output terminal of the current mirror circuit 30; the input terminal d4 of selector M2 is coupled to the common ground Gnd; and the output terminal o2 of selector M2 is coupled to the control terminal of transistor T2. Capacitor C1 is coupled between the control terminal of transistor T1 and the common ground Gnd, and capacitor C2 is coupled between the control terminal of transistor T2 and the common ground Gnd.

[0056] Taking selector M1 as an example, the working principles of selectors M1 and M2 are explained. When the control terminal k1 of selector M1 receives a "logic 0" or low-level signal, selector M1 selects input terminal d1. At this time, the output terminal of current mirror unit 22 is connected to the control electrode of transistor T1, capacitor C1 charges, and the potential at point n1 gradually rises. When the potential at point n1 rises to a certain value, making the voltage between the control electrode and the second electrode of transistor T1 greater than the turn-on voltage, transistor T1 turns on. When the control terminal k1 of selector M1 receives a "logic 1" or high-level signal, selector M1 selects input terminal d2. At this time, the control electrode of transistor T1 is connected to the common ground Gnd, capacitor C1 discharges, and under the action of capacitor C1, the potential at point n1 will not change abruptly. When capacitor C1 discharges to a certain value, making the voltage of transistor T1 less than the turn-on voltage, transistor T1 turns off. The working principle of selector M2 is the same as that of selector M1, and will not be described again.

[0057] exist Figure 7 In this circuit, the charging and discharging of capacitors C1 and C2 enables transistors T1 and T2 to be turned on or off. Capacitors C1 and C2, selectors M1 and M2, transistors T1 and T2, and flip-flop SR work together to periodically generate a clock signal.

[0058] Specifically, the output terminal QN of the SR flip-flop has the same level signal as the input terminal S of the SR flip-flop, and the output terminal Q of the SR flip-flop has the same level signal as the input terminal R of the SR flip-flop.

[0059] Assume that at the current moment, the output QN of the SR flip-flop outputs a "logic 1" or a high-level signal, and the output Q of the SR flip-flop outputs a "logic 0" or a low-level signal. In the first time period, capacitor C1 charges, and the potential of node n1 gradually increases. When the potential of node n1 rises to a certain value, transistor T1 turns on, making the potential of point a1 low. The input S of the SR flip-flop receives a low-level signal or a "logic 0," triggering the output QN of the SR flip-flop to flip, meaning the output QN of the SR flip-flop outputs a "logic 0" or a low-level signal. Meanwhile, capacitor C2 discharges, and the potential of node n2 gradually decreases. When the potential of node n2 drops to a certain value, transistor T2 turns off, making the potential of node a2 high. The input R of the SR flip-flop receives a high-level signal, triggering the output Q of the SR flip-flop to flip, meaning the output Q of the SR flip-flop outputs a "logic 1" or a high-level signal. Then, the second time period begins.

[0060] During the second time period, capacitor C1 discharges, and the potential of node n1 gradually decreases. When the potential of node n1 drops to a certain value, transistor T1 turns off, making the potential of point a1 high. The input terminal S of the SR flip-flop receives a high-level signal or "logic 1". At this time, the output terminal QN of the SR flip-flop flips to flip, that is, the output terminal QN of the SR flip-flop outputs "logic 1" or a high-level signal. Capacitor C2 charges, and the potential of node n2 gradually increases. When the potential of node n2 rises to a certain value, transistor T2 turns on, making the potential of node a2 low. The input terminal R of the SR flip-flop receives a low-level signal, which triggers the output terminal Q of the SR flip-flop to flip, that is, the output terminal Q of the SR flip-flop outputs "logic 0" or a low-level signal.

[0061] Therefore, through the charging and discharging of capacitors C1 and C2, the output terminals Q and QN of the SR flip-flop periodically output high-level and low-level signals, respectively, thus forming clock signals at output terminals Q and QN. The clock frequency of these clock signals is the toggle frequency of either the level signal at output terminal Q or the level signal at output terminal QN.

[0062] from Figure 7 As can be seen from the diagram, this embodiment controls transistors T1 and T2 by charging and discharging capacitors C1 and C2, thereby triggering the level flipping of the output terminals QN and Q of the RS flip-flop to generate a clock signal.

[0063] and Figure 1Unlike existing technologies, in this embodiment, the turn-on and turn-off times of transistors T1 and T2 are only related to the charging and discharging times of capacitors C1 and C2. The clock frequency output by the clock signal generator 100 can be controlled by controlling the charging and discharging times of capacitors C1 and C2. The charging and discharging times of capacitors C1 and C2 are related to their own materials, capacitance, and charging / discharging constants. This decouples the turn-on and turn-off times of transistors T1 and T2 from the output current of the control signal generation circuit 20, and decouples the clock signal output by the SR flip-flop from the control signal generation circuit. This avoids changes in the turn-on and turn-off times of the transistors due to temperature drift and changes in the static operating point of the integrated operational amplifier in the control signal generation circuit, thus improving the stability of the output clock signal. Furthermore, in certain application scenarios, when a higher clock frequency is required, a capacitor with a small capacitance and fast charging and discharging time can be used; when a lower clock frequency is required, a capacitor with a large capacitance and slow charging and discharging time can be used. Therefore, the maximum frequency of the clock signal to be output by the clock signal generator 100 can be effectively increased, thereby improving the performance of the clock signal generator.

[0064] In some implementations, the input S of the SR flip-flop is coupled to the first terminal of transistor T1 through an even number of inverters; the input R of the SR flip-flop is coupled to the first terminal of transistor T2 through an even number of inverters. For example... Figure 7 As shown, Figure 7 The diagram schematically illustrates the case where the input S of the SR flip-flop is coupled to the first terminal of transistor T1 via inverters F1 and F2, and the input R of the SR flip-flop is coupled to the first terminal of transistor T2 via inverters F3 and F4. By configuring inverters F1, F2, F3, and F4, the clock signal generator 100 can improve the circuit's driving capability, thereby increasing the switching speed of the level signals at the inputs S and R of the SR flip-flop.

[0065] In some implementations, the parameters of transistors T1, T2, and T3 are related. Specifically, to provide a stable quiescent operating point for the clock signal generator 100, transistors T1 and T2 can have the same physical and operating parameters, i.e., the same on-state voltage drop, internal resistance, power, etc. Furthermore, the physical and operating parameters of transistors T1 and T3 can have a certain proportional relationship. This ensures that the current flowing through node a1 is the same as the current flowing through node a2, and that the current flowing through node b is proportional to the current flowing through node a1, thus reducing the temperature drift of the clock signal generator 100's quiescent operating point.

[0066] Figures 2-7In the illustrated embodiment, the number of transistors T1, T2, and T3 is schematically shown to be in a 1:1:1 ratio. In some scenarios, the number of transistors T1, T2, and T3 can also be in other ratios. For example, there can be two transistors T1 connected in series between the power supply terminal Vdd and the common ground Gnd, and there can be one transistor T2 and one transistor T3.

[0067] This application also provides an on-chip clock system, which may include any of the clock signal generators described above, as well as other structures such as voltage sources. Voltage sources and other such structures are existing, well-known technologies and will not be described further here.

[0068] This application also provides a chip that includes the on-chip clock system described above. The on-chip clock system, including any clock signal generator described above, can provide a stable clock signal for each module within the chip, thereby enabling each module to operate stably based on the clock signal.

[0069] Specifically, the chip can be an integrated circuit chip, including but not limited to artificial intelligence chips, digital signal processing chips, and image processing chips. When the chip is used to provide image processing, data analysis, and computing functions for applications installed on terminal devices (such as mobile phones, computers, and wearable smart devices), the aforementioned electronic device can be a server device, and the chip can be housed within the server device. When the chip is applied in the field of autonomous driving to provide necessary in-vehicle computing, the aforementioned electronic device can be an in-vehicle control device, and the AI ​​chip can also be housed within the in-vehicle control device. The aforementioned chip can also be a 5G chip; in this case, the aforementioned electronic device can be a base station hardware device that communicates with the terminal, and the AI ​​chip can be housed within the base station hardware device.

[0070] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A clock signal generator, characterized in that, Includes a first transistor, a second transistor, a flip-flop, and a power supply terminal; The first transistor and the second transistor have their first terminals coupled to the power supply terminal, and their second terminals coupled to a common ground. The first input terminal of the flip-flop is coupled to the first terminal of the first transistor, the second input terminal of the flip-flop is coupled to the first terminal of the second transistor, and the output terminal of the flip-flop is used to generate a clock signal; The clock signal generator further includes a control signal generation circuit; The signal output terminal of the control signal generation circuit is coupled to the control electrode of the first transistor and the control electrode of the second transistor, respectively.

2. The clock signal generator according to claim 1, characterized in that, The control signal is a voltage signal.

3. The clock signal generator according to claim 1, characterized in that, The clock signal generator also includes a first capacitor and a second capacitor; The first terminal of the first capacitor is coupled to the control terminal of the first transistor, and the second terminal of the first capacitor is coupled to the common ground. The first transistor is periodically turned on or off based on the charging and discharging of the first capacitor. The first terminal of the second capacitor is coupled to the control terminal of the second transistor, and the second terminal of the second capacitor is coupled to the common ground. The second transistor periodically turns on or off based on the charging and discharging of the second capacitor.

4. The clock signal generator according to claim 3, characterized in that, The control signal is a current signal, and the control signal generating circuit periodically and alternately provides the current signal to the first terminal of the first capacitor and the first terminal of the second capacitor to charge the first capacitor and the second capacitor.

5. The clock signal generator according to claim 4, characterized in that, The clock signal generator also includes a third transistor; The control electrode and the first electrode of the third transistor are coupled to the power supply terminal, and the second electrode of the third transistor is coupled to the common ground; The control signal generation circuit generates the current signal based on the voltage signal between the first and second terminals of the third transistor.

6. The clock signal generator according to claim 5, characterized in that, The clock signal generator also includes a current mirror circuit; The control signal generation circuit provides the current signal to the current mirror circuit; The current mirror circuit mirrors the received current based on a preset ratio and provides the processed current to the first terminal of the first capacitor and the first terminal of the second capacitor.

7. The clock signal generator according to any one of claims 4-6, characterized in that, The clock signal generator also includes a first selector and a second selector; The control terminal of the first selector is coupled to the first output terminal of the flip-flop, the first input terminal of the first selector is coupled to the output terminal of the control signal generation circuit, the second input terminal of the first selector is coupled to the common ground, and the output terminal of the first selector is coupled to the control electrode of the first transistor. The control terminal of the second selector is coupled to the second output terminal of the flip-flop, the first input terminal of the second selector is coupled to the output terminal of the control signal generation circuit, the second input terminal of the second selector is coupled to the common ground, and the output terminal of the second selector is coupled to the control electrode of the second transistor. Under the control of the clock signal output from the first output terminal of the trigger, the first selector periodically selects the first input terminal and the second input terminal of the first selector so that the first capacitor is periodically charged and discharged. Under the control of the clock signal output from the first output terminal of the trigger, the second selector periodically selects the first and second input terminals of the second selector, so that the second capacitor is periodically charged and discharged.

8. The clock signal generator according to any one of claims 1-6, characterized in that, The first input terminal of the flip-flop is coupled to the first terminal of the second transistor through an even number of inverters.

9. The clock signal generator according to claim 5, characterized in that, The second input terminal of the flip-flop is coupled to the first terminal of the third transistor through an even number of inverters.

10. The clock signal generator according to claim 5, characterized in that, The number of the first transistor, the number of the second transistor, and the number of the third transistor are in a preset ratio; The first transistor, the second transistor, and the third transistor have the same parameters.

11. An on-chip clock system, characterized in that, The on-chip clock system includes a clock signal generator as described in any one of claims 1-10.

12. A chip, characterized in that, The chip includes the on-chip clock system as described in claim 11.

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