Delay cell circuit
By introducing a combination of equivalent diode units and general-purpose inverters into the delay unit circuit, the problem of requiring a large number of cascaded inverters in existing delay unit circuits is solved, thereby increasing the delay value and reducing power consumption, making it suitable for timing design of integrated circuits.
Patent Information
- Application Number
- CN202511103220.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-06
- Publication Date
- 2025-11-21
AI Technical Summary
Existing delay unit circuits require a large number of cascaded inverters to achieve a large delay value, and the power consumption accumulates too high in large-scale applications, affecting circuit performance.
An equivalent diode unit is introduced into the intermediate stage inverter of the delay unit circuit. The equivalent diode unit forms a voltage drop effect between the power supply terminal and the PMOS transistor, which increases the delay and reduces the power consumption. Combined with the periodic configuration of the general inverter, the signal voltage is restored.
Without increasing the circuit area, it achieves large delay adjustment and power consumption reduction, making it suitable for applications with strict requirements on delay and power consumption, such as large clock trees.
Smart Images
Figure CN121000201A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a delay unit circuit. Background Technology
[0002] In integrated circuit design, delay cells, as an important component of the standard cell library, are primarily used to adjust signal path delays to meet timing constraints, and can also be used to compensate for delay differences on different paths. A delay cell typically consists of an even number of inverters, and the desired delay value is achieved through the delay accumulation of cascaded inverters.
[0003] Existing delay unit circuits have the following problems: the delay time of a single inverter is relatively short, requiring a large number of inverters to be cascaded to achieve a large delay value, which increases the circuit complexity; when a large number of delay units are used in the design (such as in large clock tree applications), the static and dynamic power consumption of multiple delay units accumulates, resulting in excessive overall power consumption and affecting circuit performance; in addition, a large number of delay units are required to obtain a sufficient delay value, which can easily increase the chip area occupied.
[0004] Ultimately, the main problem with existing technologies stems from their circuit architecture: traditional delay units only increase the delay value by adding inverter stages, lacking an effective power consumption control mechanism, and cannot reduce power consumption while increasing delay. Summary of the Invention
[0005] The purpose of this application is to provide a delay unit circuit to solve the technical problem that existing delay unit circuits require a large number of cascaded inverters to achieve a large delay value, and the power consumption is too high when applied on a large scale.
[0006] To achieve the above objectives, this application adopts the following technical solution.
[0007] This application provides a delay unit circuit, comprising: a first-stage inverter and a last-stage inverter, the first-stage inverter and the last-stage inverter constituting the input stage and output stage of the delay unit circuit, respectively; at least one intermediate-stage inverter coupled between the first-stage inverter and the last-stage inverter, the intermediate-stage inverter comprising an equivalent diode unit; wherein, the equivalent diode unit comprises a first PMOS transistor, the drain, gate and substrate of the first PMOS transistor being coupled as the cathode of the equivalent diode unit, the source of the first PMOS transistor being coupled to a power supply terminal, and the source of the first PMOS transistor serving as the anode of the equivalent diode unit.
[0008] In some possible implementations, the intermediate stage inverter further includes a second PMOS transistor, and the equivalent diode unit is connected in series with the second PMOS transistor between the power supply terminal and the output node of the intermediate stage inverter; when the second PMOS transistor is turned on, the equivalent diode unit is momentarily turned on and generates a voltage drop; when the second PMOS transistor is turned off, the equivalent diode unit is in the off state.
[0009] In some possible implementations, the forward conduction voltage of the equivalent diode unit ranges from 0.5V to 0.7V.
[0010] In some possible implementations, the intermediate stage inverter further includes: a first NMOS transistor connected in series with the first PMOS transistor and the second PMOS transistor; the source of the second PMOS transistor is coupled to the cathode of the equivalent diode unit, the drain of the second PMOS transistor is coupled to the drain of the first NMOS transistor as the output node of the intermediate stage inverter, and the substrate of the second PMOS transistor is coupled to a power supply terminal; the source of the first NMOS transistor is coupled to ground potential, and the substrate of the first NMOS transistor is grounded; the gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are coupled as the input terminal of the intermediate stage inverter.
[0011] In some possible implementations, the number of the first NMOS transistors is equal to the number of the second PMOS transistors, or the number of the first NMOS transistors is equal to the total number of the first PMOS transistors and the second PMOS transistors.
[0012] In some possible implementations, the channel width-to-length ratio of the first PMOS transistor is equal to that of the second PMOS transistor.
[0013] In some possible implementations, the delay unit circuit further includes a universal inverter coupled after at least one intermediate stage inverter, for pulling up the output voltage when the output voltage of the coupled intermediate stage inverter is lower than a preset threshold.
[0014] In some possible implementations, the delay unit circuit further includes a universal inverter coupled after a series of M intermediate stage inverters, used to pull up the output voltage of the M intermediate stage inverters, where M is determined based on the target delay value and noise margin requirements of each intermediate stage inverter.
[0015] In some possible implementations, the universal inverter includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor;
[0016] The source and substrate of the third PMOS transistor and the substrate of the fourth PMOS transistor are coupled to the power supply terminal. The drain of the third PMOS transistor is coupled to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is coupled to the drain of the second NMOS transistor as the output node of the universal inverter. The source of the second NMOS transistor is coupled to the drain of the third NMOS transistor. The substrates of the second NMOS transistor, the source of the third NMOS transistor, and the substrate of the third NMOS transistor are grounded. The gates of the third PMOS transistor, the fourth PMOS transistor, the second NMOS transistor, and the third NMOS transistor are coupled as the input terminal of the universal inverter.
[0017] In some possible implementations, the delay unit circuit includes a four-stage inverter, wherein the second-stage inverter and the third-stage inverter each contain an equivalent diode unit.
[0018] This application provides a delay unit circuit that achieves increased delay and reduced power consumption by introducing an equivalent diode unit in the intermediate stage inverter. The equivalent diode unit uses a diode connection where the drain, gate, and substrate of the first PMOS transistor are connected in series between the power supply and the second PMOS transistor in the intermediate stage inverter. When the second PMOS transistor in the same stage is turned on, the equivalent diode unit instantaneously conducts and generates a forward voltage drop of 0.5V to 0.7V. As the cathode voltage of the equivalent diode unit increases, its voltage drop decreases accordingly. This reduces the operating voltage of other MOS transistors in the same stage (such as the second PMOS transistor and the first NMOS transistor), thereby slowing down the switching speed and increasing the propagation delay. Simulation results show that, under 0.18μm process, 1.8V supply voltage, and 25℃ operating conditions, the rise delay and fall delay of the delay unit circuit in this application are increased by approximately 37% compared to traditional delay units, the average power consumption is reduced by approximately 10%, and the peak current is reduced from 140μA to 120μA. Furthermore, when using multiple stages of equivalent diode units consecutively, a general-purpose inverter is periodically coupled to restore the signal voltage to the normal operating level, ensuring the reliability of the circuit function. Compared to traditional delay units that can only increase the delay value by increasing the number of inverter stages, this application, through the above-described implementation, achieves a larger delay adjustment range and lower power consumption within a limited silicon area, providing effective technical support for applications with strict requirements on delay and power consumption, such as large clock trees. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of a traditional delay unit circuit.
[0021] Figure 2 This is a detailed implementation diagram of a traditional four-stage inverter delay unit circuit.
[0022] Figure 3 This is a circuit diagram of the delay unit circuit in one embodiment of this application.
[0023] Figure 4 This is a circuit diagram of the delay unit circuit in another embodiment of this application.
[0024] Figure 5 This is a schematic diagram of the current-voltage characteristic curve of a diode.
[0025] Figure 6 The simulation waveform diagram shows the relationship between the input signal and the voltage of MP5 over time.
[0026] Figure 7 Example diagram for configuring a multi-stage delay unit.
[0027] Figure 8 The simulation waveforms of the conventional circuit and the circuit of this application are shown in the comparison diagram.
[0028] Figure 9A and Figure 9B The circuit diagrams and logic voltage relationship diagrams for the output of the pre-stage and the input of the post-stage are shown respectively. Detailed Implementation
[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] As described in the background section, existing delay unit circuits typically employ an even number of inverters (such as...). Figure 1 The signal delay function is achieved by cascading the delay circuits shown. (See attached image.) Figure 2 As shown, a traditional delay unit circuit consists of four inverters connected in series, including four PMOS transistors (MP1', MP2', MP3', MP4') and four NMOS transistors (MN1', MN2', MN3', MN4'). The input signal I is inverted through four stages to output signal Z. The total delay value of this circuit is the sum of the delay times of the four inverters. Since the delay time of a single inverter is usually short, more stages of inverters are needed to achieve a larger delay value.
[0031] The aforementioned traditional architecture has significant technical limitations. When a large delay value is required, a large number of inverter stages must be used. Designers often need to cascade up to a dozen or more inverter stages to obtain sufficient total delay. The cascading of numerous inverters not only occupies valuable chip area but also generates significant static and dynamic power consumption at high frequencies. This cumulative power consumption effect is particularly pronounced in applications requiring a large number of delay units, such as large clock trees (tree-like network structures used to distribute clock signals to various functional modules within a chip). As the feature size of integrated circuits continues to shrink and circuit complexity continues to increase, the limitations of traditional delay unit architectures in power consumption control are becoming increasingly apparent. Power consumption has become a key bottleneck restricting the improvement of circuit performance.
[0032] To address the aforementioned technical problems, this application proposes an improved delay unit circuit. This delay unit circuit may include a first-stage inverter and a final-stage inverter, constituting the input and output stages of the delay unit, and at least one intermediate-stage inverter coupled between the first-stage and final-stage inverters. By introducing an equivalent diode unit in the intermediate-stage inverter, a voltage drop effect is created between the power supply terminal and the PMOS transistor, thereby increasing the circuit delay and reducing the power consumption level.
[0033] The equivalent diode unit may include a first PMOS transistor, whose drain, gate and substrate are coupled together as a cathode and its source is coupled to a power supply terminal as an anode, forming an equivalent diode structure.
[0034] In this embodiment, PMOS devices from the standard cell library can be used to implement the equivalent diode function. While dedicated diode devices are typically used in semiconductor manufacturing and design, these devices generally have a larger layout area, whereas PMOS devices from the standard cell library have a smaller layout area. Therefore, this application chooses to use PMOS devices to implement the equivalent diode function to meet the delay cell design requirements under area constraints.
[0035] In this embodiment, the working principle of the equivalent diode unit is based on the volt-ampere characteristics of a diode, see reference. Figure 5 As shown, when the forward voltage exceeds the turn-on voltage U on When the equivalent diode unit is turned on, the forward voltage drop is maintained at U. on Nearby; when the forward voltage is less than Uon, the voltage drop across the equivalent diode unit is small. Figure 5 Middle U BR Indicates the reverse breakdown voltage, I sThese parameters, representing the reverse saturation current, indicate the characteristics of the diode in the reverse bias region. Since the anode of the equivalent diode unit in this application is coupled to the power supply terminal, which is the highest voltage in the circuit, the equivalent diode unit always operates in the forward bias region and will not enter the reverse breakdown region. For devices made of silicon, U... on Typically between 0.5V and 0.7V, this characteristic provides a reliable operating basis for the voltage modulation of the delay unit, ensuring the stability and predictability of the circuit operation.
[0036] The configuration design of the equivalent diode unit needs to consider the noise margin characteristics of the circuit to ensure the reliability of the delay unit under various operating conditions. Based on the working principle of the equivalent diode unit described above, the application of the equivalent diode unit in the delay circuit is explained in detail below with specific embodiments.
[0037] See Figure 3 In the embodiment shown, in order to ensure the consistency of input and output phases, the delay unit circuit may include four stages of inverters, wherein the first stage inverter 10 and the last stage inverter 40 are first general-purpose inverters, and the second stage inverter 20 and the third stage inverter 30 each include an equivalent diode unit.
[0038] In this embodiment, the first-stage inverter 10 may include a PMOS transistor MP1 and an NMOS transistor MN1. The source of PMOS transistor MP1 is coupled to the power supply terminal VDD, the gate of PMOS transistor MP1 receives the input signal I, the drain of PMOS transistor MP1 is coupled to the drain of NMOS transistor MN1, the substrate of PMOS transistor MP1 is coupled to the power supply terminal VDD, the gate of NMOS transistor MN1 receives the same input signal I, the source of NMOS transistor MN1 is coupled to ground potential, and the substrate of NMOS transistor MN1 is coupled to ground potential. The output node of the first-stage inverter 10 is formed by the connection point of the drains of MP1 and MN1.
[0039] In this embodiment, the input signal I is inverted by the first-stage inverter 10 and then output.
[0040] Furthermore, the second-stage inverter 20 may include an equivalent diode unit 21, a second PMOS transistor MP2, and a first NMOS transistor MN2.
[0041] In this embodiment, the drain, gate, and substrate of the first PMOS transistor MP5 in the equivalent diode unit 21 are mutually coupled as a cathode, and its source is coupled to the power supply terminal VDD as an anode. The equivalent diode unit 21 is connected in series between the power supply terminal VDD and the source of the second PMOS transistor MP2. In other words, the equivalent diode unit 21 and the second PMOS transistor MP2 are connected in series between the power supply terminal and the output node of the second-stage inverter 20. The gate of the second PMOS transistor MP2 is coupled to the output node of the first-stage inverter 10, and the drain of the second PMOS transistor MP2 is coupled to the drain of the first NMOS transistor MN2 to form the output node of the second-stage inverter 20. The substrate of the second PMOS transistor MP2 is coupled to the power supply terminal VDD. The gate of the first NMOS transistor MN2 is coupled to the output node of the first-stage inverter 10, the source of the first NMOS transistor MN2 is coupled to ground potential, and the substrate of the first NMOS transistor MN2 is coupled to ground potential.
[0042] In this embodiment, the number of first NMOS transistors in the same stage inverter is the same as the number of second PMOS transistors.
[0043] In this embodiment, the gates of the second PMOS transistor MP2 and the first NMOS transistor MN2 are both coupled to the output node of the first-stage inverter 10, together forming the input terminal of the second-stage inverter 20.
[0044] Furthermore, the channel width-to-length ratio of the first PMOS transistor MP5 in the equivalent diode unit 21 is equal to the channel width-to-length ratio of the second PMOS transistor MP2 in the second-stage inverter 20, so as to achieve a balance between delay and power consumption.
[0045] In this embodiment, the circuit structure of the third-stage inverter 30 is the same as that of the second inverter.
[0046] Specifically, refer to Figure 3 The third-stage inverter 30 includes an equivalent diode unit 31, a second PMOS transistor MP3, and a first NMOS transistor MN3. The drain, gate, and substrate of the first PMOS transistor MP6 in the equivalent diode unit 31 are mutually coupled as a cathode, and its source is coupled to the power supply terminal VDD as an anode. The equivalent diode unit 31 is connected in series between the power supply terminal VDD and the source of the second PMOS transistor MP3. The gate of the second PMOS transistor MP3 is coupled to the output node of the second-stage inverter 20. The drain of the second PMOS transistor MP3 and the drain of the first NMOS transistor MN3 are coupled to form the output node of the third-stage inverter 30. The substrate of the second PMOS transistor MP3 is coupled to the power supply terminal VDD. The gate of the first NMOS transistor MN3 is coupled to the output node of the second-stage inverter 20. The source of the first NMOS transistor MN3 is coupled to ground potential, and the substrate of the first NMOS transistor MN3 is coupled to ground potential.
[0047] In this embodiment, refer to Figure 3 The final-stage inverter 40 has the same circuit structure as the first-stage inverter 10, and may include a PMOS transistor MP4 and an NMOS transistor MN4, forming a first general-purpose inverter structure. The source of the PMOS transistor MP4 is coupled to the power supply terminal VDD, and the gate of the PMOS transistor MP4 is coupled to the output node of the third-stage inverter 30. The drain of the PMOS transistor MP4 and the drain of the NMOS transistor MN4 are coupled to form the final output terminal Z of the delay unit circuit, and the substrate of the PMOS transistor MP4 is coupled to the power supply terminal VDD. The gate of the NMOS transistor MN4 is coupled to the output node of the third-stage inverter 30, and the source of the NMOS transistor MN4 is coupled to ground potential. The substrate of the NMOS transistor MN4 is coupled to ground potential.
[0048] In this embodiment, taking the first PMOS transistor MP5 in the equivalent diode unit 21 as an example, such as... Figure 6 As shown, the simulation waveform illustrates the relationship between the voltage across its terminals and the input signal. The MOSFET in the simulation circuit uses a 0.18μm process device, with a supply voltage set to 1.8V and an operating temperature of 25℃. Combined with... Figure 3 As shown, when the input signal is low, the PMOS transistor MP1 of the first-stage inverter 10 is turned on, and the NMOS transistor MN1 of the first-stage inverter 10 is turned off. The high-level output is transmitted to the second-stage inverter 20, and the first NMOS transistor MN2 of the second-stage inverter 20 is turned on, while the second PMOS transistor MP2 of the second-stage inverter 20 is turned off. At this time, the cathode voltage of the equivalent diode unit 21 is stable at around 1.68V, and the forward voltage is about 0.12V (i.e., the power supply voltage 1.8V minus the cathode voltage 1.68V), which is in the forward cutoff range, and only a small amount of leakage current flows through. When the input signal turns high, the PMOS transistor MP1 of the first-stage inverter 10 is cut off, and the NMOS transistor MN1 of the first-stage inverter 10 is turned on, so the low-level output is transmitted to the second-stage inverter 20. The first NMOS transistor MN2 of the second-stage inverter 20 is cut off, and the second PMOS transistor MP2 of the second-stage inverter 20 is turned on. At the instant the input signal turns from low to high, the cathode potential of the equivalent diode unit 21 drops to about 1.1V. At this time, the forward voltage of the equivalent diode unit 21 reaches about 0.7V and enters the forward conduction state. Subsequently, the output node voltage of the second-stage inverter 20 is gradually pulled up, and the forward voltage of the equivalent diode unit 21 decreases accordingly until the next time the input signal turns from high to low, at which point the equivalent diode unit 21 returns to the forward cutoff state with a forward voltage of 0.12V.
[0049] In this embodiment, the operation of the equivalent diode unit 31 of the third-stage inverter 30 is similar to that of the equivalent diode unit 21 of the second-stage inverter 20. However, since the output voltage of the previous stage, i.e., the second-stage inverter 20, is already lower than the supply voltage of 1.8V, the overall voltage drop of the third-stage inverter 30 is greater. When there are many delay units, the voltage of the later stages will further decrease. Therefore, the equivalent diode unit structure cannot be used indefinitely. When a certain stage is reached, the voltage of the previous stage may have dropped to a certain level, making it impossible for the MOSFET of the next stage to switch normally, thus causing the circuit to malfunction. In this case, the output voltage may enter an unrecognizable forbidden region, destroying the integrity of the circuit's logic function.
[0050] To address the excessive voltage drop caused by the continuous application of equivalent diode units across multiple stages, this application employs a periodic configuration of universal inverters. (See also...) Figure 7 The multi-level configuration embodiment shown in this embodiment includes multiple cascaded inverters, illustrating an alternating configuration of equivalent diode units and a universal inverter (second universal inverter).
[0051] In this embodiment, the number of PMOS transistors and NMOS transistors in the general-purpose inverter (second general-purpose inverter) is equal to the number of PMOS transistors and NMOS transistors in the intermediate-stage inverter. For example... Figure 7 As shown, each transistor consists of two PMOS transistors and two NMOS transistors.
[0052] The following combination Figure 7 Further details will be provided.
[0053] Specifically, the first-stage inverter 10 may include a PMOS transistor MP1 and an NMOS transistor MN1, forming a first general-purpose inverter structure. The source of the PMOS transistor MP1 is coupled to the power supply terminal VDD, the gate receives the input signal I, and the drain is coupled to the drain of the NMOS transistor MN1 to form the output node of the first-stage inverter 10. The source and substrate of the NMOS transistor MN1 are both coupled to ground potential.
[0054] In this embodiment, the second-stage inverter 20 includes an equivalent diode unit 21 (which includes a first PMOS transistor MP7), a second PMOS transistor MP2, and first NMOS transistors MN2 and MN7. The drain, gate, and substrate of the first PMOS transistor MP7 in the equivalent diode unit 21 are coupled together as a cathode, and its source is coupled to the power supply terminal VDD as an anode. It is connected in series between the power supply terminal and the source of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is coupled to the output node of the first-stage inverter 10, and its drain is coupled to the drain of the first NMOS transistor MN2 to form the output node of the second-stage inverter 20. The first NMOS transistors MN2 and MN7 are connected in series between the second-stage output node and ground potential. The third-stage inverter 30 includes an equivalent diode unit 31 (which includes a first PMOS transistor MP8), a second PMOS transistor MP3, and first NMOS transistors MN3 and MN8. Its circuit structure is the same as that of the second-stage inverter 20, thus realizing a two-stage equivalent diode unit configuration.
[0055] In this embodiment, the fourth-stage inverter 40 adopts a general-purpose inverter structure (second general-purpose inverter), which may include a third PMOS transistor MP9, a fourth PMOS transistor MP4, and a second NMOS transistor MN9 and MN4. The source of the third PMOS transistor MP9 is coupled to the power supply terminal VDD and does not include an equivalent diode unit. The fourth-stage inverter 40 is used to restore the voltage drop generated by two consecutive equivalent diode units to the normal operating level. In other words, the fourth-stage inverter 40 is coupled after the second-stage inverter and the third-stage inverter containing equivalent diode units. When the output voltage of these intermediate stage inverters is lower than a preset threshold, this general-purpose inverter can effectively pull up the output voltage.
[0056] In this embodiment, the fifth-stage inverter 50 includes an equivalent diode unit 51 (which includes a first PMOS transistor MP10), a second PMOS transistor MP5, and a first NMOS transistor MN5 and a first NMOS transistor MN10, wherein the equivalent diode unit 51 generates a voltage drop effect.
[0057] Furthermore, the final stage inverter 60 adopts a first general-purpose inverter structure, including a PMOS transistor MP6 and an NMOS transistor MN6 as the output stage.
[0058] In this embodiment, the inverters at each stage are connected sequentially via signal lines. The periodic configuration of the general-purpose inverters ensures the noise margin and functional reliability of the entire delay link. That is, after every M consecutive intermediate stage inverters containing equivalent diode units, a general-purpose inverter needs to be coupled to restore the voltage. Figure 7The diagram shows an example configuration with M=2, where a general-purpose inverter (fourth-stage inverter 40) is coupled after every two consecutive stages of equivalent diode units (second-stage inverter 20 contains equivalent diode unit 21, third-stage inverter 30 contains equivalent diode unit 31), then a fifth-stage inverter 50 contains equivalent diode unit 51, and finally a general-purpose inverter 60 serves as the output stage.
[0059] In one embodiment, the specific value of M needs to be determined based on the target delay value and noise margin requirements of the intermediate stage inverter, and is also affected by the device manufacturing process parameters and supply voltage. Under different process feature sizes and supply voltage conditions, the threshold voltage and voltage drop characteristics of the device are different, which in turn affects the number of consecutive equivalent diode unit stages. For example, under 0.18μm process and 1.8V supply conditions, an M=2 configuration can achieve good delay performance while ensuring noise margin.
[0060] In the delay unit circuit of this application, when the first PMOS transistor MP5 of the second-stage inverter 20 and the first PMOS transistor MP6 of the third-stage inverter 30 are connected in an equivalent diode configuration, the operating voltage of the other MOS transistors in the same stage is reduced, thereby effectively reducing the power consumption of the circuit. Simultaneously, due to the reduction in operating voltage, the signal transmission delay of the circuit increases accordingly, making it suitable for applications requiring greater delay to adjust and repair timing.
[0061] Referring to Table 1, simulation results based on the 0.18μm process show that, under operating conditions of 25℃, 1.8V power supply voltage, and 50MHz operating frequency, the performance comparison data between the circuit of this application and the conventional circuit are as follows: The rise delay time (DelayRise(s)) increased from 2.566912e-10 seconds in the conventional circuit to 3.529522e-10 seconds in the circuit of this application, an increase of 37.5%; the fall delay time (Delay Fall(s)) increased from 2.551713e-10 seconds in the conventional circuit to 3.480061e-10 seconds in the circuit of this application, an increase of 36.4%; the average current (Avg I(A)) decreased from 2.443779e-06 amperes in the conventional circuit to 2.201090e-06 amperes in the circuit of this application, a decrease of 9.93%; the average power consumption (Avg I(A)) decreased from 2.443779e-06 amperes in the conventional circuit to 2.201090e-06 amperes in the circuit of this application; and the average power consumption (Avg I(A)) decreased from 2.443779e-06 amperes in the conventional circuit to 2.201090e-06 amperes in the circuit of this application. P(W) is reduced from 4.398802e-06 watts in the conventional circuit to 3.961960e-06 watts in the circuit of this application, a reduction of 9.93%.
[0062] Traditional circuits The circuit of this application Delay Rise(s) 2.566912e-10 3.529522e-10 37.5％ Delay Fall(s) 2.551713e-10 3.480061e-10 36.4％ Avg I(A) 2.443779e-06 2.201090e-06 -9.93％ Avg P(W) 4.398802e-06 3.961960e-06 -9.93％
[0063] Table 1
[0064] See Figure 8As shown in the simulation waveform diagram, the peak current during level transition in the traditional circuit is around 140μA, while in the circuit of this application, due to the voltage drop of the equivalent diode unit, the peak current is reduced to around 120μA. The reduction in peak current directly leads to a reduction in average power consumption, thus verifying the effectiveness of this application in power consumption optimization.
[0065] See Figure 4 In the specific embodiment shown, to obtain a larger delay value, the number of first NMOS transistors connected in series in the intermediate stage inverter can be increased. Figure 4 The intermediate delay unit circuit also includes four stages of inverters. The first stage inverter 10 and the last stage inverter 40 are the first general-purpose inverters, and the second stage inverter 20 and the third stage inverter 30 each contain an equivalent diode unit.
[0066] In this embodiment, the connection relationship of each device in the first-stage inverter 10 and the last-stage inverter 40 is as follows: Figure 3 The embodiment shown is the same, with the first-stage inverter 10 including PMOS transistor MP1 and NMOS transistor MN1, and the last-stage inverter 40 including PMOS transistor MP4 and NMOS transistor MN4.
[0067] Continue reading Figure 4 As shown, the second-stage inverter 20 includes an equivalent diode unit 21, a second PMOS transistor MP2, and first NMOS transistors MN2 and MN5. (The last sentence appears to be incomplete and possibly refers to a different inverter.) Figure 3 The difference is, Figure 4 A first NMOS transistor MN5 is added in series on the NMOS transistor side, forming a series configuration of MN2 and MN5. The drain, gate, and substrate of the PMOS transistor MP5 in the equivalent diode unit 21 are mutually coupled as a cathode, and its source is coupled to the power supply terminal VDD as an anode, connected in series between the power supply terminal VDD and the source of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is coupled to the output node of the first-stage inverter 10, and the drain of the second PMOS transistor MP2 is coupled to the drain of the first NMOS transistor MN2 to form the output node of the second-stage inverter 20. The substrate of the second PMOS transistor MP2 is coupled to the power supply terminal VDD. The gate of the first NMOS transistor MN2 is coupled to the output node of the first-stage inverter 10, the source of the first NMOS transistor MN2 is coupled to the drain of the first NMOS transistor MN5, and the substrate of the first NMOS transistor MN2 is coupled to ground potential. The gate of the first NMOS transistor MN5 is coupled to the output node of the first inverter 10, the source of the first NMOS transistor MN5 is coupled to ground potential, and the substrate of the first NMOS transistor MN5 is coupled to ground potential.
[0068] In this embodiment, the third-stage inverter 30 includes an equivalent diode unit 31, a second PMOS transistor MP3, and first NMOS transistors MN3 and MN6. The drain, gate, and substrate of the first PMOS transistor MP6 in the equivalent diode unit 31 are mutually coupled to form a cathode, and its source is coupled to the power supply terminal VDD as an anode, connected in series between the power supply terminal VDD and the source of the second PMOS transistor MP3. The gate of the second PMOS transistor MP3 is coupled to the output node of the second-stage inverter 20, and the drain of the second PMOS transistor MP3 is coupled to the drain of the first NMOS transistor MN3 to form the output node of the third-stage inverter 30. The substrate of the second PMOS transistor MP3 is coupled to the power supply terminal VDD. The gate of the first NMOS transistor MN3 is coupled to the output node of the second-stage inverter 20, the source of the first NMOS transistor MN3 is coupled to the drain of the first NMOS transistor MN6, and the substrate of the first NMOS transistor MN3 is coupled to ground. The gate of the first NMOS transistor MN6 is coupled to the output node of the second-stage inverter 20, the source of the first NMOS transistor MN6 is coupled to ground potential, and the substrate of the first NMOS transistor MN6 is coupled to ground potential.
[0069] Figure 4 The second-stage inverter 20 and third-stage inverter 30 not only add equivalent diode units 21 and 31 on the PMOS transistor side, but also add first NMOS transistors MN5 and MN6 connected in series on the NMOS transistor side, making the total number of NMOS transistors in each stage equal to the total number of first and second PMOS transistors. In the second-stage inverter 20, there are two first NMOS transistors (MN2 and MN5), and the total number of first and second PMOS transistors is two (MP5 and MP2), which are equal. In the third-stage inverter 30, there are two first NMOS transistors, and the total number of first and second PMOS transistors is two, which are also equal. This configuration can further increase the impedance on the signal transmission path, producing a delay increase effect in both the PMOS and NMOS transistor sides, which is suitable for applications requiring a wider delay adjustment range. Figure 4 In the embodiment shown, the gates of the second PMOS transistor and all the first NMOS transistors connected in series are coupled to the same input signal terminal, forming a unified input terminal of the intermediate stage inverter.
[0070] In this embodiment, the configuration of the equivalent diode unit has high flexibility and can be adjusted according to specific application requirements. For example, in a 0.18μm process with a supply voltage of 1.8V, a general-purpose inverter needs to be coupled after two consecutive stages of equivalent diode units; however, at more advanced process nodes or lower supply voltages, a general-purpose inverter may need to be configured after each stage of equivalent diode units. Changes in process parameters affect the threshold voltage and leakage current characteristics of the MOSFET, thereby affecting the voltage drop effect of the equivalent diode unit and the overall circuit performance. It should be noted that process parameters include the feature size of the manufacturing process (e.g., 0.18μm) and the threshold voltage type (e.g., high threshold voltage HVT, standard threshold voltage SVT, low threshold voltage LVT). The consideration of device input / output noise margin is mainly to ensure that the circuit can still maintain reliable logic function under the conditions of process deviations and environmental changes, avoiding malfunctions caused by insufficient noise margin.
[0071] To illustrate this constraint more clearly, see [link / reference]. Figure 9A and Figure 9B As shown, there is a defined logic level relationship between the output of the pre-stage and the input of the post-stage of the delay unit. The high-level range of the pre-stage output is V. OH The output low level range is from ground potential to V, up to the supply voltage. OL The high-level input recognition range of the subsequent stage is V. IH The input low-level recognition range is from ground potential to V, up to the supply voltage. IL Under normal operating conditions, when the current stage outputs a high level, its voltage value V OH It needs to be greater than V IH Only then can the subsequent stage correctly identify it as a high-level signal; when the current stage outputs a low level, its voltage value V OL It needs to be less than V IL Only then can the subsequent stage correctly identify it as a low-level signal. Due to V IL and V IH The voltage range between these two thresholds is a prohibited region; the signal voltage should not remain within this region for extended periods. Noise margin is defined as the difference between the output level and the input threshold. A high-level noise margin is NM. H equals V OH Subtract V IH Low-level noise margin NM L equals V IL Subtract V OLThese parameters directly affect the delay unit's immunity to interference signals and its operational stability. When the equivalent diode unit causes a voltage drop, it is necessary to ensure that the input voltage of the subsequent inverter still meets the corresponding noise margin requirements to avoid logic errors or circuit malfunctions due to insufficient noise margin. When equivalent diode units are used in multiple consecutive stages, the output voltage of the preceding stage will decrease step by step, and the corresponding noise margin will also decrease. To maintain sufficient noise margin, the configuration number M of the general-purpose inverter needs to be determined based on the changes in the target delay value and noise margin conditions. When the noise margin is near a critical value, it is necessary to couple with a general-purpose inverter to restore the voltage and ensure the normal operation of subsequent circuits. For example, under 0.18μm process conditions, when the noise margin drops to a critical value that may affect the normal operation of subsequent circuits, it is usually necessary to couple with a general-purpose inverter for voltage recovery.
[0072] The delay unit circuit design in this application utilizes the voltage drop characteristics of an equivalent diode unit, achieving coordinated control of delay and power consumption through circuit structure improvements. Compared to the traditional method of simply increasing the number of inverter stages, this application's voltage-reduction-based delay control method can effectively reduce the required number of components and circuit area under the same delay target, while exhibiting significant advantages in power consumption control. In applications with stringent requirements for delay accuracy and power consumption, such as large clock distribution networks and signal timing adjustments, this delay unit circuit demonstrates good delay controllability and power efficiency, making it suitable for timing design requirements in integrated circuits.
[0073] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.
[0074] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A delay unit circuit, characterized in that, include: The first-stage inverter and the last-stage inverter respectively constitute the input stage and the output stage of the delay unit circuit; At least one intermediate stage inverter is coupled between the first stage inverter and the final stage inverter, the intermediate stage inverter including an equivalent diode unit; The equivalent diode unit includes a first PMOS transistor. The drain, gate, and substrate of the first PMOS transistor are coupled together to serve as the cathode of the equivalent diode unit. The source of the first PMOS transistor is coupled to the power supply terminal and serves as the anode of the equivalent diode unit.
2. The delay unit circuit as described in claim 1, characterized in that, The intermediate stage inverter also includes a second PMOS transistor, and the equivalent diode unit is connected in series with the second PMOS transistor between the power supply terminal and the output node of the intermediate stage inverter; when the second PMOS transistor is turned on, the equivalent diode unit is instantaneously turned on and generates a voltage drop; when the second PMOS transistor is turned off, the equivalent diode unit is in the off state.
3. The delay unit circuit as described in claim 2, characterized in that, The forward conduction voltage range of the equivalent diode unit is 0.5V to 0.7V.
4. The delay unit circuit as described in claim 2, characterized in that, The intermediate stage inverter further includes a first NMOS transistor connected in series with the first PMOS transistor and the second PMOS transistor; The source of the second PMOS transistor is coupled to the cathode of the equivalent diode unit, the drain of the second PMOS transistor is coupled to the drain of the first NMOS transistor as the output node of the intermediate stage inverter, and the substrate of the second PMOS transistor is coupled to the power supply terminal. The source of the first NMOS transistor is grounded, and the substrate of the first NMOS transistor is grounded. The gates of the second PMOS transistor and the first NMOS transistor are coupled together to serve as the input terminals of the intermediate stage inverter.
5. The delay unit circuit as described in claim 4, characterized in that, The number of the first NMOS transistors is equal to the number of the second PMOS transistors, or the number of the first NMOS transistors is equal to the total number of the first PMOS transistors and the second PMOS transistors.
6. The delay unit circuit as described in claim 2, characterized in that, The channel width-to-length ratio of the first PMOS transistor is equal to that of the second PMOS transistor.
7. The delay unit circuit as described in claim 1, characterized in that, The delay unit circuit further includes a universal inverter, which is coupled after at least one intermediate stage inverter and is used to pull up the output voltage when the output voltage of the coupled intermediate stage inverter is lower than a preset threshold.
8. The delay unit circuit as described in claim 1, characterized in that, The delay unit circuit further includes a general-purpose inverter, which is coupled after the M consecutive intermediate stage inverters and is used to pull up the output voltage of the M intermediate stage inverters, where M is determined according to the target delay value and noise margin requirements of each intermediate stage inverter.
9. The delay unit circuit as described in claim 7 or 8, characterized in that, The general-purpose inverter includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor; The source and substrate of the third PMOS transistor and the substrate of the fourth PMOS transistor are coupled to the power supply terminal. The drain of the third PMOS transistor is coupled to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is coupled to the drain of the second NMOS transistor as the output node of the universal inverter. The source of the second NMOS transistor is coupled to the drain of the third NMOS transistor. The substrates of the second NMOS transistor, the source of the third NMOS transistor, and the substrate of the third NMOS transistor are grounded. The gates of the third PMOS transistor, the fourth PMOS transistor, the second NMOS transistor, and the third NMOS transistor are coupled as the input terminal of the universal inverter.
10. The delay unit circuit as described in claim 1, characterized in that, The delay unit circuit includes four inverters, wherein the second-stage inverter and the third-stage inverter each contain an equivalent diode unit.