UART Baud rate adaptive circuit

Abstract

The invention provides a UART Baud rate adaptive circuit, which comprises an internal clock, a UART module and a matching calibration module, the UART module comprises a data serial-parallel conversion module, a Baud rate generator, a TX and an RX, the matching calibration module comprises a sampling module and a calibration module, the data serial-parallel conversion module is connected with the calibration module, and the Baud rate generator is connected with the sampling module. And the baud rate generator is connected with the data serial-parallel conversion module and the calibration module. According to the method, matching calibration logic is added, the length of the current frame is sampled in real time, the matching value of the baud rate is changed, and the baud rate of the next frame is calibrated.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of UART circuit, and particularly relates to a UART baud rate adaptive circuit. BACKGROUND

[0002] UART is a kind of asynchronous serial communication mode which can use asynchronous transceiver, and needs two signal lines to realize, one is used for sending TX, and the other is used for receiving RX. The communication data of the protocol is in units of frames, and each frame is composed of a start bit, a data bit and a stop bit, the start bit indicates the starting point, followed by 8 data bits, and finally the stop bit indicates the end of transmission. The rate of communication is represented by baud rate, and only when the baud rate and the frame format of the host and the slave are the same, the data transmission can be correctly completed.

[0003] When the baud rate of the host sending data does not match the baud rate of the slave receiving data, the slave receives the frame data incorrectly, resulting in receiving failure. Usually, the slave of the UART will be configured by the controller to match the baud rate of the host, but this also needs to be set in advance between the host and the slave.

[0004] Due to the importance of data, many application scenarios need to transmit a large amount of data, and due to the different lengths of the transmission signals, the frame length of the same baud rate of the UART will have an error, and this error will accumulate and affect the transmission of the next frame due to the continuous transmission of data. Due to the massive transmission data, when the accumulated error reaches the tolerance value, transmission errors will occur. SUMMARY

[0005] In order to solve the technical problems of baud rate adaptation and massive data transmission baud rate calibration, the application provides a UART baud rate adaptive circuit which can automatically match the transmission baud rate without external tool configuration before transmission, and automatically calibrate the matched baud rate in real time during the transmission process.

[0006] The application is realized by the following technical solutions:

[0007] A UART baud rate adaptive circuit, comprising an internal clock, a UART module and a matching and calibration module, the UART module comprising a data serial-parallel conversion module, a baud rate generator, TX and RX, the matching and calibration module comprising a sampling module and a calibration module, the data serial-parallel conversion module being connected to the calibration module, and the baud rate generator being connected to the data serial-parallel conversion module and the calibration module.

[0008] Preferably, the TX is the sending end of the data serial-parallel conversion module, and the RX is the receiving end of the data serial-parallel conversion module.

[0009] Preferably, the RX is further connected to the sampling module.

[0010] Preferably, the internal clock is connected with the baud rate generator and the sampling module.

[0011] Preferably, the sampling module is connected with the calibration module.

[0012] Compared with the prior art, the present application has the following advantages:

[0013] In the present application, the matching calibration logic is added, the current frame length is sampled in real time, the matching value of the baud rate is changed, and the baud rate of the next frame is calibrated. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is the circuit diagram of the present application.

[0015] Figure 2 is the circuit diagram of the UART module of the present application.

[0016] Figure 3 is the circuit diagram of the matching calibration module of the present application.

[0017] Figure 4 is the calibration control timing diagram of the present application.

[0018] Figure 5 is the baud rate generation timing diagram of the present application.

[0019] In the drawings:

[0020] 1, internal clock; 2, UART module; 3, matching calibration module; 21, data serial-parallel conversion module; 22, baud rate generator; 23, TX; 24, RX; 31, sampling module; 32, calibration module. DETAILED DESCRIPTION

[0021] The present application will be described in detail below with reference to the accompanying drawings, in which: Figure 1 and Figure 2 As shown in the drawings, a UART baud rate adaptive circuit comprises an internal clock 1, a UART module 2 and a matching calibration module 3, the UART module 2 comprises a data serial-parallel conversion module 21, a baud rate generator 22, a TX 23 and a RX 24, the matching calibration module 3 comprises a sampling module 31 and a calibration module 32, the data serial-parallel conversion module 21 is connected with the calibration module 32, and the baud rate generator 22 is connected with the data serial-parallel conversion module 21 and the calibration module 32.

[0022] In the present embodiment, specifically, the TX 23 is the sending end of the data serial-parallel conversion module 21, and the RX 24 is the receiving end of the data serial-parallel conversion module 21.

[0023] In the present embodiment, specifically, the RX 24 is further connected with the sampling module 31.

[0024] In this embodiment, specifically, the internal clock 1 is connected to the baud rate generator 22 and the sampling module 31.

[0025] In this embodiment, specifically, the sampling module 31 is connected to the calibration module 32.

[0026] In this embodiment, as shown in the attached Figure 4 and the attached Figure 5 , the width corresponding to each bit is fixed with respect to different baud rates, when the baud rate generator 22 is configured to the required baud rate, the internal clock 1 REFCLK is frequency-divided according to the configured baud rate, to generate the BAUDRATE_EN signal to enable the baud rate generator 22 to generate the baud rate clock, at this time, the parallel-serial conversion module 21 of the parallel-serial conversion module works under the baud rate clock, and sends the start bit, then sends the data and the stop bit.

[0027] In this embodiment, specifically, since the reference clock of each device is biased itself, it may cause the same configured baud rate to cause the bit width sent by different devices to be biased, since the UART communication is a single-wire clockless communication mode, the stability and correctness of the data mainly depend on the small bias of the bit width, when the data is continuously transmitted, the bias is superimposed, and when a large amount of data is transmitted, incorrect data may appear, before communication, each device can send a calibration data frame 0xAA, since the RX 24 inputs the calibration data frame, at this time, the sampling module 31 detects the start bit to generate the START_SAMPLE signal, uses the internal clock 1 REFCLK to sample the bit, calculates the width PULSE_CNT of each bit, completes the sampling of a frame of data, and calculates the average value SAMPLE_TS of the width of the bit, and outputs it to the calibration module 32, when the calibration module 32 obtains the latest average value, outputs the baudrate_update to update the baud rate generator configuration value, to generate the baud rate matched with the current device, the parallel-serial conversion module 21 in the parallel-serial conversion module (transmission) transmits data according to the latest baud rate, at this time, the transmitted data is the calibration data, and the calibration module 32 also calibrates the serial-parallel module (receiving module) in the data serial-parallel conversion module 21, when the calibration data serial-parallel conversion module 21 of the parallel-serial conversion module is calibrated, receive_sample is also output to the serial-parallel module of the data serial-parallel conversion module 21, to adjust the data detection position to the optimal, to ensure the stability of the collected data.

[0028] Working principle

[0029] In the application, before matching, the host needs to send a matching frame first, which is used for matching the baud rate of the slave, after the matching is completed, the host can send data for transmission, at this time, the sampling module 31 samples the RX24 end in real time, the length of each 1BIT of data is calculated, and the matched baud rate is compared and adjusted, the current frame length is sampled in real time, the matching value of the baud rate is changed, the baud rate of the next frame is calibrated, and the accuracy of data transmission is ensured.

[0030] The technical solutions of the application or the technical solutions designed by the person skilled in the art based on the technical solutions of the application and achieving the above technical effects all fall within the protection scope of the application.

Claims

1. A UART baud rate adaptation circuit, characterized by The UART baud rate adaptive circuit comprises an internal clock (1), a UART module (2) and a matching calibration module (3), the UART module (2) comprises a data string parallel conversion module (21), a baud rate generator (22), a TX (23) and a RX (24), the matching calibration module (3) comprises a sampling module (31) and a calibration module (32), the data string parallel conversion module (21) is connected with the calibration module (32), and the baud rate generator (22) is connected with the data string parallel conversion module (21) and the calibration module (32).

2. The UART baud rate adaptation circuit of claim 1, wherein, The TX (23) is a sending end of the data string parallel conversion module (21).

3. The UART baud rate adaptation circuit of claim 1, wherein, The RX (24) is a receiving end of the data string parallel conversion module (21).

4. The UART baud rate adaptation circuit of claim 1, wherein, The RX (24) is further connected with the sampling module (31).

5. The UART baud rate adaptation circuit of claim 1, wherein, The internal clock (1) is connected with the baud rate generator (22) and the sampling module (31).

6. The UART baud rate adaptation circuit of claim 1, wherein, The sampling module (31) is connected with the calibration module (32).

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