Power supply system of intelligent processing chip

Abstract

A power supply system of an intelligent processing chip belongs to the technical field of space power supplies. The slow start circuit controls voltage between a source electrode and a grid electrode of an FET tube through a RC circuit of the slow start circuit to achieve the purpose of slow start, and input charging surge current generated at the moment of power-up is reduced; the input filter circuit is used for allowing low-frequency pulse current to flow through and suppressing high-frequency noise interference; the power supply module is used for carrying out DC-DC conversion on the voltage signal; the output filter circuit is used for allowing low-frequency pulse current to flow through and suppressing high-frequency noise interference; the power supply modules and the output filter circuits are in one-to-one correspondence to form multi-path output; the FPGA control and feedback circuit is used for dynamically adjusting interval time of different paths of output voltage according to requirements and carrying out feedback control on amplitudes of the different paths of output voltage; and monitoring the temperature of each group of power supply modules in real time, and performing feedback control on the output power of the power supply modules.

Description

Technical Field

[0001] This invention relates to a power supply system for an intelligent processing chip, belonging to the field of space power technology. Background Technology

[0002] With the development of intelligent processing chips (such as AI accelerators, GPUs, and ASICs) and the improvement of big data processing capabilities, chip power consumption is constantly increasing, significantly enhancing the necessity and complexity of power control and management. These intelligent processing chips used in CPU / AICORE / DDR / PCIe systems typically require multiple high-precision power supplies, placing extremely high demands on power supply dynamic response speed, noise control, and energy efficiency management. Traditional power management methods rely on fixed-function power management chips or complex analog circuits, which are insufficient to meet the needs of intelligent processing chips for dynamic load adaptability and multiple high-precision controls. Summary of the Invention

[0003] The technical problem to be solved by this invention is to overcome the shortcomings of the prior art and solve the problem of complex power control and management of intelligent processing chips under irradiation environment.

[0004] The objective of this invention is achieved through the following technical solutions:

[0005] A power supply system for an intelligent processing chip includes a soft-start circuit, an input filter circuit, a power module, an output filter circuit, and an FPGA control and feedback circuit; wherein there are multiple sets of power modules and output filter circuits, which correspond one-to-one to form multiple outputs;

[0006] Soft-start circuit: It achieves the purpose of soft-start by controlling the voltage between the source and gate of its own FET through its own RC circuit, thereby reducing the input charging surge current generated at the moment of power-up;

[0007] Input filtering circuit: includes differential mode inductor, common mode inductor, and capacitor, which allows low-frequency pulse current to flow and suppresses high-frequency noise interference;

[0008] The power supply module is used to perform DC-DC conversion on voltage signals;

[0009] Output filter circuit: including circuit beads, ceramic capacitors, and tantalum capacitors, it is a low-pass filter circuit that allows low-frequency pulse current to flow through and suppresses high-frequency noise interference.

[0010] FPGA control and feedback circuit: dynamically adjusts the interval time of different output voltages according to requirements, and performs feedback control on the amplitude of different output voltages; monitors the temperature of each power module in real time, and uses this to perform feedback control on the output power of the power modules.

[0011] Compared with the prior art, the present invention has the following advantages:

[0012] (1) This invention enables the startup time of multiple secondary power supplies by controlling the power supply module with a small-scale FPGA, and dynamically adjusts the time of different intervals according to requirements; this invention is designed to send commands to set the startup and interval times, and at the same time receive remote telemetry from each secondary power supply, quantize it through FPGA, and then output it to the feedback end of the power supply module to adjust the precise output of the power supply module; this invention can monitor the temperature of the power supply module in real time, and dynamically adjust the temperature through the feedback circuit. If the temperature is too high, the frequency is automatically reduced; or if the load is increased, the voltage and frequency are increased.

[0013] (2) This invention utilizes an anti-radiation controller and a power module to solve the problem of the availability of anti-radiation power management unit devices, realizes the control and management of complex multi-group power supplies for intelligent processing chips, and can monitor and adjust power parameters in real time with nanosecond-level delay, significantly improving the dynamic response speed and control accuracy of the power system, and can also realize temperature detection of high-power power chips.

[0014] (3) This invention realizes the controllable and adjustable power-on and power-off timing of the intelligent processing chip and chip temperature detection, realizing intelligent power control and management. At the same time, it solves the problem that there are no radiation-resistant devices available for the power management unit, providing technical support for the large-scale aerospace application of intelligent processing chips in the future, and has broad application prospects on more intelligent processing platforms in the future.

[0015] (4) Compared to traditional methods, FPGAs can achieve real-time monitoring, dynamic adjustment, and precise control of multiple power parameters through hardware acceleration, thereby significantly improving the efficiency and flexibility of power management. Furthermore, the reconfigurability and flexibility of FPGAs enable them to quickly optimize power management strategies according to the needs of different application scenarios, such as Dynamic Voltage Frequency Scaling (DVFS), power rail sequence management, and power consumption optimization. Dynamic voltage adjustment reduces system power consumption, and FPGA control improves the reliability and stability of power management, providing better technical support for the efficient operation of intelligent processing chips. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the system of the present invention.

[0017] Figure 2 This is the schematic diagram of a soft-start circuit.

[0018] Figure 3 This is a schematic diagram of the FPGA control and feedback circuit. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0020] Intelligent processing chips (such as AI accelerators, GPUs, DSPs, and ASICs) place extremely high demands on the stability and efficiency of power supply systems in applications such as high-performance computing, artificial intelligence, and real-time processing. The main problems that need to be solved in these applications include: insufficient adaptability to dynamic loads, high requirements for power supply parameter accuracy and real-time performance, complex power-on sequencing and management needs, and power consumption and heat dissipation issues.

[0021] A power supply system for an intelligent processing chip enables the control, output, and adjustment of multiple power supplies for the chip. It effectively expands the system's load adaptability through the hardware flexibility and intelligent algorithms of an FPGA; it controls the enable signals of the power modules via the FPGA to meet the power-on sequence of multiple power rails, and receives telemetry feedback from the output power signals to precisely regulate the output voltage; it also detects the temperature of the power modules via the FPGA; and finally, through the design of multiple power supply circuits, it outputs multiple high-precision voltages.

[0022] A power supply system for an intelligent processing chip includes a soft-start circuit, an input filter circuit, an FPGA control and feedback circuit, a power module, and an output filter circuit, such as... Figure 1 As shown. There are multiple sets of power supply modules and output filter circuits, which correspond one-to-one to form multiple outputs.

[0023] like Figure 2 As shown, the soft-start circuit uses an RC circuit to achieve a soft-start effect by adjusting the voltage between the source and gate of the FET, thus reducing the input charging inrush current generated at the moment of power-up. The soft-start circuit includes resistors R1, R2, R3, and R4, a diode, a FET, and a capacitor C1. One end of resistor R1, one end of resistor R2, one end of resistor R4, and one end of capacitor C1 are all connected together. The other end of resistor R1, the other end of capacitor C1, one end of the diode, and the source of the FET are all connected to the external input voltage. The other end of the diode, the other end of resistor R2, and one end of resistor R3 are all connected together, and the other end of resistor R3 is grounded. The gate of the FET is connected to the other end of resistor R4, and the drain of the FET is connected to the input filter circuit. At the moment of power-on, the voltage levels on both sides of capacitor C1 are the same, and the FET is not turned on. After a period of power-on, the voltage across capacitor C1 is determined by the voltage division of resistors R1, R2, and R3. Once the voltage reaches the turn-on voltage of the FET, it starts to work. The soft-start time can be shortened by reducing the capacitance of capacitor C1 or the resistance of resistor R3.

[0024] Input filter circuit: This circuit mainly consists of a differential-mode inductor, a common-mode inductor, and a capacitor. It allows low-frequency pulse current to flow while suppressing higher-frequency noise interference. Its function is to prevent electromagnetic interference generated by the power supply itself from entering the primary bus, and at the same time, to prevent interference from the primary power bus from entering the power supply and affecting its normal operation.

[0025] Power Module: This module uses integrated circuits to perform DC-DC conversion on voltage signals. During the design process, standardized packaging allows for in-situ replacement of modules to adapt to different primary voltages. The power module features overvoltage protection. Connecting a suitable resistor to the overvoltage protection pin automatically cuts off power when the output voltage exceeds the set voltage and resumes operation when the voltage drops below the set voltage. The power module also features overcurrent protection. When the output current exceeds the overcurrent protection point of 50A, it triggers overcurrent protection, shutting down the internal drive, reducing the output voltage to 0V, and simultaneously implementing hiccup protection. After a period of time, the power module will restart. If an overcurrent fault still exists at this point, after a fixed soft-start setup time, the power module will again enter a shutdown state.

[0026] like Figure 3 As shown, the FPGA control and feedback circuit mainly includes an FPGA and an XADC (i.e., an analog-to-digital converter module). The FPGA controls the enabling of multiple power supply modules, adjusting their startup times. Figure 3 The output of the second group of power modules is delayed by 30ms compared to the first group, the third group by 50ms, and the nth group by 20ms. Based on user requirements, different start-up and interval times are set for different groups of power modules via the FPGA, achieving dynamic control over the output times of different groups. Simultaneously, remote telemetry data from each group of power modules is received near the external intelligent processing chip. After digital quantization via XADC, the data is input to the FPGA and compared with the target voltage. If the output of a power module is lower than the target voltage, the FPGA increases the output of that group; if it is higher, the FPGA decreases the output. This solves the problem of load voltage mismatch due to losses during electrical transmission, resulting in more accurate power module output. Furthermore, the FPGA can monitor the temperature of multiple secondary power modules in real time and dynamically adjust and control the temperature. For example, if an overheating of a power module is detected, the switching frequency of the corresponding module's hiccup protection function is automatically reduced.

[0027] Output filter circuit: This circuit is a low-pass filter circuit mainly composed of ferrite beads, ceramics, and tantalum capacitors. It allows low-frequency pulse current to flow through and suppresses high-frequency noise interference, making the output voltage of each channel more accurate.

[0028] The contents not described in detail in this specification are common knowledge to those skilled in the art.

[0029] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A power supply system for an intelligent processing chip, characterized in that, It includes a soft-start circuit, an input filter circuit, a power supply module, an output filter circuit, and an FPGA control and feedback circuit. The soft-start circuit achieves the purpose of soft-start by controlling the voltage between the source and gate of its own FET through its own RC circuit, thereby reducing the input charging surge current generated at the moment of power-up. The input filter circuit allows low-frequency pulse current to flow while suppressing higher-frequency noise interference. The power supply module is used to perform DC-DC conversion on voltage signals; Output filter circuit: used to allow low-frequency pulse current to flow through and suppress high-frequency noise interference; There are multiple sets of power supply modules and output filter circuits, which correspond one-to-one to form multiple outputs; The FPGA control and feedback circuit dynamically adjusts the interval time of different output voltages according to requirements and provides feedback control on the amplitude of different output voltages; it also monitors the temperature of each power module in real time to provide feedback control on the output power of the power modules.

2. The power supply system for the intelligent processing chip according to claim 1, characterized in that, The soft-start circuit includes resistors R1, R2, R3, and R4, a diode, a FET, and a capacitor C1. One end of resistor R1, one end of resistor R2, one end of resistor R4, and one end of capacitor C1 are all connected together. The other end of resistor R1, the other end of capacitor C1, one end of diode, and the source of FET are all connected to the external input voltage. The other end of diode, the other end of resistor R2, and one end of resistor R3 are all connected together. The other end of resistor R3 is grounded. The gate of FET is connected to the other end of resistor R4, and the drain of FET is connected to the input filter circuit.

3. The power supply system of the intelligent processing chip according to claim 2, characterized in that, At the moment of power-up of the soft-start circuit, the voltage levels on both sides of capacitor C1 are the same, and the FET is not conducting. After a period of power-up, the voltage across capacitor C1 is determined by the voltage division of resistors R1, R2, and R3. Once the voltage reaches the turn-on voltage of the FET, the circuit starts to work.

4. The power supply system of the intelligent processing chip according to claim 2, characterized in that, The soft-start time can be shortened by reducing the capacitance of capacitor C1 or the resistance of resistor R3.

5. The power supply system of the intelligent processing chip according to claim 1, characterized in that, By standardizing the packaging during the design process, the power module can be replaced in situ to adapt to different primary voltages.

6. The power supply system of the intelligent processing chip according to claim 1, characterized in that, The power module has overvoltage protection. A preset resistor is connected to the overvoltage protection pin of the power module so that when the output voltage is higher than the set voltage, the power is automatically cut off and can resume operation when the voltage is lower than the set voltage.

7. The power supply system of the intelligent processing chip according to claim 1, characterized in that, The power module has overcurrent protection. When the output current exceeds the overcurrent protection point of the power module, the overcurrent protection will be triggered, and the power module will block the internal drive and shut down. It also has hiccup protection. After a period of time, the power module will restart. If the overcurrent fault still exists at the output, the power module will enter the shutdown state again after a fixed soft start setup time.

8. The power supply system of the intelligent processing chip according to claim 1, characterized in that, The FPGA control and feedback circuit mainly includes an FPGA and an analog-to-digital converter module. The FPGA controls the enable of multiple power modules and adjusts the startup time of the multiple power modules. The analog-to-digital converter module performs digital quantization on the remote telemetry of each power module and inputs it to the FPGA for voltage feedback control.

9. The power supply system of the intelligent processing chip according to claim 8, characterized in that, The FPGA can monitor the temperature of multiple secondary power supply modules in real time and control the temperature of the power supply modules by dynamically adjusting the switching frequency of the power supply module hiccup protection function.

10. The power supply system of the intelligent processing chip according to claim 8, characterized in that, The control functions of an FPGA are reconfigurable.

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