A multi-chip stacked package structure and a method of manufacturing the same

Abstract

The application provides a multi-chip stacked package structure and a preparation method thereof. The multi-chip stacked package structure comprises a first chip distributed on a substrate, a side surface of the first chip being covered by a first plastic package structure; a second chip stacked on the first chip, a side surface and a bottom surface of the second chip being covered by a second plastic package structure; and a heat dissipation structure comprising micro-flow channels located on both sides of the first chip and the second chip, the micro-flow channels penetrating a top surface of the second plastic package structure and extending to a bottom surface of the first plastic package structure, and side surfaces of the micro-flow channels being covered by the first plastic package structure and the second plastic package structure. The multi-chip stacked package structure can quickly conduct the heat generated by the chips to the outside of the overall package structure, avoid the accumulation of heat in the plastic package structure, and ensure the reliability and service life of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a multi-chip stacked packaging structure and a preparation method thereof. BACKGROUND

[0002] At present, three-dimensional stacked packaging technology is an important implementation way to improve chip integration density and system performance. One of the key technologies to realize three-dimensional interconnection is through-silicon via (TSV) technology. The through-silicon via technology can form a vertical electrical connection in a silicon wafer to realize high-bandwidth signal transmission between chips, and has become the first choice for many high-density integration schemes. However, the through-silicon via process still has many problems: 1. High process complexity, requiring multiple processes such as deep silicon etching, insulation layer deposition, copper filling, and chemical mechanical polishing, which requires high equipment and process control; 2. The formation of through-silicon vias usually accompanies problems such as thermal stress concentration, wafer warping, and micro-cracks, affecting the integration reliability and yield; 3. The cost of through-silicon via technology is very high, especially the cost of equipment investment and process development in large-scale production.

[0003] In order to avoid the above shortcomings of the through-silicon via process, in recent years, a kind of non-through-silicon via stacked packaging technology based on copper pillar interconnection and secondary plastic packaging has appeared. This kind of technology usually includes the following steps: first, a copper pillar structure is prepared on a single chip using photolithography, physical vapor deposition and electroplating process; then a redistribution layer with corresponding copper pillars is formed on a carrier wafer through fan-out packaging process; finally, the chip is mounted on the carrier wafer, the copper pillars are exposed by plastic packaging and grinding, and the stacked interconnection and ball planting are continued. Although this kind of structure simplifies the process to some extent and improves the yield, it introduces new technical problems:

[0004] Especially in high-power density chip stacking, heat is easily accumulated inside the plastic packaging material and the multi-layer medium, which is difficult to dissipate quickly, resulting in high chip junction temperature and seriously affecting the device reliability and service life. Traditional heat dissipation schemes such as external heat sinks or thermal interface materials cannot be embedded inside the plastic package, and the convection heat dissipation path is limited, making it difficult to cope with local high heat flux problems. SUMMARY

[0005] Therefore, the present application provides a multi-chip stacked packaging structure and a preparation method thereof, aiming to solve the technical problem that heat accumulation in the multi-chip stacked packaging structure cannot be dissipated in the prior art.

[0006] The technical scheme provided by the present application is as follows:

[0007] In a first aspect, the present application provides a multi-chip stacked packaging structure, which comprises:

[0008] The first chip is distributed on the substrate, and a side surface of the first chip is covered by a first plastic encapsulation structure.

[0009] The second chip is stacked on the first chip, and a side surface and a bottom surface of the second chip are covered by a second plastic encapsulation structure.

[0010] The multi-chip stacked encapsulation structure further comprises a heat dissipation structure.

[0011] The heat dissipation structure comprises:

[0012] The micro flow channel is located on both sides of the first chip and the second chip, penetrates a top surface of the second plastic encapsulation structure, and extends to a bottom surface of the first plastic encapsulation structure, and a side surface of the micro flow channel is covered by the first plastic encapsulation structure and the second plastic encapsulation structure.

[0013] Further, the heat dissipation structure further comprises a micro flow channel cover plate.

[0014] The micro flow channel cover plate is arranged on a back surface of the first chip, is in close contact with the bottom surface of the first plastic encapsulation structure, and a bottom surface of the micro flow channel is in close contact with a top surface of the micro flow channel cover plate, so as to form a bottom-sealed micro flow channel; and the micro flow channel cover plate is filled with heat dissipation liquid.

[0015] Further, the heat dissipation structure further comprises a heat dissipation block.

[0016] The heat dissipation block is arranged on both sides of the first chip and is connected with the micro flow channel, and an interval exists between the heat dissipation block and the first chip.

[0017] Further, top surfaces of the first chip and the second chip are respectively provided with a first rewiring structure and a second rewiring structure, the first rewiring structure and the second rewiring structure are connected through a first metal structure, and a side surface of the first metal structure is covered by the second plastic encapsulation structure.

[0018] Further, the first rewiring structure and the second rewiring structure are respectively covered by a first dielectric structure and a second dielectric structure, the first dielectric structure is arranged between the first plastic encapsulation structure and the second plastic encapsulation structure, a position of the first rewiring structure which is not covered by the first dielectric structure is connected with the first metal structure, and a bump is arranged at an end portion of the second rewiring structure which exceeds the second dielectric structure.

[0019] In another aspect, the application further provides a preparation method of a multi-chip stacked encapsulation structure, which is used for forming the multi-chip stacked encapsulation structure, and the preparation method comprises the following steps:

[0020] Step S11: providing a first chip and a second chip stacked on the first chip, and a first re-wiring structure and a second re-wiring structure disposed on top surfaces of the first chip and the second chip respectively, the first chip being covered by a first plastic encapsulation structure;

[0021] Step S12: forming a microfluidic channel in communication with both sides of the first chip and the second chip, and a gap existing between the microfluidic channel and the first chip and the second chip.

[0022] Further, after the step S12, further comprising:

[0023] Step S13: forming a microfluidic channel cover plate on a bottom surface of the first chip, the microfluidic channel cover plate being in close contact with a bottom surface of the first plastic encapsulation structure, and a top surface of the microfluidic channel cover plate being in close contact with a bottom surface of the microfluidic channel, both constituting a complete heat dissipation structure.

[0024] Further, after the step S13, further comprising:

[0025] Step S101: forming a first dielectric structure on a top surface of the first chip, the first dielectric structure covering the first re-wiring structure;

[0026] Step S102: forming a first metal structure penetrating the first dielectric structure and connecting the first re-wiring structure and the second re-wiring structure;

[0027] Step S103: forming a second plastic encapsulation structure above the first dielectric structure, and the second plastic encapsulation structure wrapping the second chip.

[0028] Further, the step of forming the microfluidic channel comprises:

[0029] Step S104: etching a first microfluidic channel in the first plastic encapsulation structure on both sides of the first chip, a gap existing between the first microfluidic channel and both sides of the first chip, and a bottom surface of the first microfluidic channel being in close contact with a top surface of the microfluidic channel cover plate;

[0030] Step S105: etching a second microfluidic channel in the second plastic encapsulation structure on both sides of the second chip, a gap existing between the second microfluidic channel and both sides of the second chip, and the second microfluidic channel penetrating the first dielectric structure and being in communication with the first microfluidic channel.

[0031] Further, after the step S103, further comprising:

[0032] Step S106: forming a second medium structure on the top surface of the second plastic encapsulation structure, and in close contact with the top surface of the second plastic encapsulation structure.

[0033] Step S107: etching the second medium structure to lead out the micro-flow channel through the second medium structure.

[0034] The scheme provided by the present application has the following beneficial effects:

[0035] 1. The multi-chip stacked packaging structure provided by the present application forms a heat dissipation structure surrounding the chip by forming a micro-flow channel in the plastic encapsulation structure on both sides of the first chip and the second chip, which can quickly lead out the heat generated by the chip to the outside of the overall packaging structure, avoids the accumulation of heat in the plastic encapsulation structure, and ensures the reliability and service life of the device.

[0036] 2. The multi-chip stacked packaging structure provided by the present application forms a complete heat dissipation structure that can circulate the heat dissipation liquid by setting a micro-flow channel cover plate on the back of the first chip, and the micro-flow channel cover plate and the micro-flow channel constitute a complete heat dissipation structure that can circulate the heat dissipation liquid, which can realize active heat dissipation of the overall packaging structure; and the size of the micro-flow channel is small, which can be directly integrated inside the packaging structure, and the heat dissipation liquid in the micro-flow channel cover plate can spontaneously take away the heat generated by the chip when circulating in the micro-flow channel, further reducing the junction temperature of the chip and prolonging the service life of the device.

[0037] 3. The multi-chip stacked packaging structure provided by the present application can improve the integration of the semiconductor packaging structure by integrating multiple chips in the vertical direction, which can integrate more functional chips such as processors and memory chips in the same or smaller packaging area, is more conducive to integration in devices with smaller size, and realizes the diversification of functions without increasing the size of the device.

[0038] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0040] Figure 1 The cross-sectional schematic of the multi-chip stacked packaging structure provided by the embodiments of the present application Figure 1This figure shows a first chip, a second chip, a first molding compound, a second molding compound, a first dielectric structure, a second dielectric structure, a microfluidic channel located in and connected within the first molding compound and the second molding compound, and a microfluidic channel cover plate disposed on the back of the first chip.

[0041] Figure 2 Schematic cross-sectional view of a multi-chip stacked package structure provided in another embodiment of this application. Figure 2 ,and Figure 1 In contrast, this figure shows heat sinks located on both sides of the first chip and connected to the microfluidic channels;

[0042] Figure 3 A cross-sectional view of the multi-chip stacked package structure provided in the embodiments of this application. Figure 3 This figure shows a first chip, a second chip, a first rewiring structure, a second rewiring structure, a first metal structure, a first molding compound structure, a second molding compound structure, a first dielectric structure, a second dielectric structure, and a microchannel cover plate located on the back of the first chip.

[0043] Figure 4 A flowchart illustrating the fabrication method of the multi-chip stacked packaging structure provided in this application embodiment;

[0044] Figure 5 This is a cross-sectional schematic diagram of the first chip and the second chip provided in step S11 of this application;

[0045] Figure 6 A cross-sectional schematic diagram of the multi-chip stacked package structure formed after performing step S101, as provided in an embodiment of this application.

[0046] Figure 7 A cross-sectional schematic diagram of the multi-chip stacked package structure formed after performing step S104, as provided in an embodiment of this application.

[0047] Figure 8 A cross-sectional schematic diagram of the multi-chip stacked package structure formed after performing step S105, as provided in an embodiment of this application.

[0048] Figure 9 A cross-sectional schematic diagram of the multi-chip stacked package structure formed after performing step S106, as provided in an embodiment of this application.

[0049] Figure 10 This is a cross-sectional schematic diagram of the multi-chip stacked package structure formed after performing step S107, as provided in the embodiments of this application.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100 - first chip; 101 - first rewiring structure; 102 - first dielectric structure; 200 - second chip; 201 - second rewiring structure; 202 - second dielectric structure; 300 - first plastic sealing structure; 400 - second plastic sealing structure; 500 - heat dissipation structure; 501 - microfluidic channel; 502 - microfluidic channel cover plate; 503 - heat dissipation block; 600 - first metal structure. DETAILED DESCRIPTION

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will be a clear and complete description of the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0054] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0055] In the description of the present application, it should be noted that the terms "inner", "outer", "upper", "lower", "vertical", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used for differentiation, and cannot be understood as indicating or implying relative importance.

[0056] The following will be a detailed description of some embodiments of the present application with reference to the drawings. The features in the following embodiments can be combined with each other without conflict.

[0057] In view of the defects of the prior art, the technical solutions of the present application are proposed. The technical solutions of the present application will be described in detail below.

[0058] Please refer to Figure 1 , Figure 1A cross-sectional view of a multi-chip stacked package structure according to an embodiment of the present application Figure 1 The first chip, the second chip, the first encapsulation structure, the second encapsulation structure, the first dielectric structure, the second dielectric structure, the microfluidic channel located in the first encapsulation structure and the second encapsulation structure and the microfluidic channel cover plate arranged on the back surface of the first chip are shown in the figure. The multi-chip stacked package structure comprises a first chip 100, a second chip 200 and a heat dissipation structure 500.

[0059] The first chip 100 is distributed on a substrate (not shown in the figure), and the side surface thereof is covered by the first encapsulation structure 300. The substrate can be a Si substrate, a SiC substrate, a GaAs substrate or other compound semiconductor materials such as GaN, etc. The first chip 100 is fixed on the substrate by solder bumps or die bonding glue, and is electrically connected with the circuit (not shown in the figure) on the substrate. The first encapsulation structure 300 is formed by a transfer molding process, and is composed of epoxy molding compound (EMC). The first encapsulation structure 300 wraps all the side surfaces and the bottom surface of the first chip 100, and completely fills the gap between the first chip 100 and the substrate. After the first encapsulation structure 300 is formed, it is ground to form a flat plane on the bottom surface thereof. The second chip 200 is stacked on the first chip 100, and the side surface and the bottom surface of the second chip 200 are covered by the second encapsulation structure 400. The second chip 200 is stacked on the first chip 100, and the front surface of the second chip 200 is arranged in the same direction as the front surface of the first chip 100. The second encapsulation structure 400 is also formed by a transfer molding process, and the material of the second encapsulation structure 400 is the same as that of the first encapsulation structure 300. The second encapsulation structure 400 completely covers the bottom surface and all the side surfaces of the second chip 200, and completely fills all the gaps between the bottom surface of the second chip 200 and the underlying structure. After the second encapsulation structure 400 is formed, it is ground to form a flat plane on the top surface thereof.

[0060] The heat dissipation structure 500 comprises: a micro flow channel 501, which is located on both sides of the first chip 100 and the second chip 200, penetrates the top surface of the second plastic package structure 400 and extends to the bottom surface of the first plastic package structure 300, and the side surface of the micro flow channel 501 is covered by the first plastic package structure 300 and the second plastic package structure 400. The micro flow channel 501 is located on both sides of the first chip 100 and is spaced apart from the two side surfaces of the first chip 100, and the spacing is about 20um-500um; similarly, the micro flow channel 501 is also spaced apart from the two side surfaces of the second chip 200, and the spacing is about 20um-500um; the size of the micro flow channel 501 is sub-micron, the micro flow channel 501 penetrates the top surface of the second plastic package structure 400 covering the side surface of the second chip 200 and extends along the stacking direction of the first chip 100 and the second chip 200, and then extends along the stacking direction of the first chip 100 and the second chip 200, and finally extends to the bottom surface of the first plastic package structure 300. The part of the micro flow channel 501 located on both sides of the second chip 200 is completely covered by the second plastic package structure 400, and the part of the micro flow channel 501 located on both sides of the first chip 100 is completely covered by the first plastic package structure 300, that is, the micro flow channel 501 is completely formed in the plastic package structure. Figure 1 As can be seen, the extension of the first chip 100 in the direction perpendicular to the stacking direction is greater than the extension of the second chip 200 in the direction perpendicular to the stacking direction, so in this direction, the micro flow channel 501 will form a bend perpendicular to the stacking direction and parallel to the stacking direction, and finally continue to extend downward along the stacking direction and finally extend to the bottom surface of the first plastic package structure 300. The part of the micro flow channel 501 located on both sides of the second chip 200 is completely covered by the second plastic package structure 400, and the part of the micro flow channel 501 located on both sides of the first chip 100 is completely covered by the first plastic package structure 300, that is, the micro flow channel 501 is completely formed in the plastic package structure.

[0061] In this embodiment, by arranging the first plastic package structure 300 around the first chip 100, mechanical support and protection can be provided for the overall multi-chip stacked package structure; by arranging the second plastic package structure 400 around the second chip 200, the second plastic package structure 400 and the first plastic package structure 300 are made of the same material, which can buffer the mechanical stress of the stacking interface of the first chip 100 and the second chip 200, further improving the stability of the package structure; by arranging the communicating sub-micron micro flow channel 501 in the plastic package structure on both sides of the first chip 100 and the second chip 200, a heat dissipation structure around the chip can be formed, which can quickly conduct the heat generated by the chip to the outside of the overall multi-chip stacked package structure, avoid the accumulation of heat in the plastic package structure, and ensure the reliability and service life of the device.

[0062] In one embodiment, the heat dissipation structure 500 further comprises: a micro-channel cover plate 502; the micro-channel cover plate 502 is arranged on the back surface of the first chip 100 and is in close contact with the bottom surface of the first plastic package structure 300, and the bottom surface of the micro-flow channel 501 is in close contact with the top surface of the micro-channel cover plate 502 to form a bottom-sealed micro-flow channel; the micro-channel cover plate 502 contains injected heat dissipation liquid. The micro-channel cover plate 502 is preferably a material with high thermal conductivity, such as oxygen-free copper (OFC) or silicon alloy, and the top surface of the micro-channel cover plate 502 is subjected to precision polishing treatment to ensure that the part in contact with the bottom surface of the micro-flow channel 501 can be closely attached to form a reliable metal-metal sealed interface; at the same time, the top surface of the micro-channel cover plate 502 is in close contact with the bottom surface of the first plastic package structure 300, and the two are permanently air-tightly sealed by thermal compression bonding or eutectic bonding, so that the micro-flow channel is completely enclosed in the cavity formed by the micro-flow channel 501 and the micro-channel cover plate 502. The part of the micro-flow channel 501 beyond the second plastic package structure 400 is provided with a micro-injection hole (not shown in the figure), through which the heat dissipation liquid is injected into the micro-flow channel 501 and the micro-channel cover plate 502, and the heat dissipation liquid can circulate in the heat dissipation structure 500 formed by the micro-flow channel 501 and the micro-channel cover plate 502, thereby timely removing the heat generated by the chip. There are many choices for heat dissipation liquid, such as electronic fluorination liquid, deionized water or glycol solution. The electronic fluorination liquid has high insulation and is non-flammable, and has low surface tension; the specific heat capacity of deionized water is high, and the cost is low and easy to obtain; the glycol solution can lower the freezing point and increase the boiling point; due to their characteristics, these materials can be selected as heat dissipation liquid, which is not limited in this application.

[0063] In this embodiment, by arranging the micro-channel cover plate 502 in close contact with the bottom surface of the first plastic package structure 300 on the back surface of the first chip 100, the micro-channel cover plate 502 can form a sealed heat dissipation structure 500 with the micro-flow channel 501, and inject heat dissipation liquid into the heat dissipation structure 500, finally forming a self-cooling and circulating heat dissipation structure. Such arrangement can achieve active cooling of the overall packaging structure; and the micro-flow channel 501 has a small size and can be directly integrated inside the packaging structure, and the heat dissipation liquid in the micro-channel cover plate 502 can spontaneously remove the heat generated by the chip when circulating in the micro-flow channel 501, further reducing the junction temperature of the chip and prolonging the service life of the device.

[0064] In another embodiment, the heat dissipation structure 500 further includes a heat sink 503; the heat sink 503 is disposed on both sides of the first chip 100 and connected to the microfluidic channel 501, and there is a gap between the heat sink 503 and the first chip 100. See also Figure 2 , Figure 2 Schematic cross-sectional view of a multi-chip stacked package structure provided in another embodiment of this application. Figure 2 ,and Figure 1 In contrast, this figure shows heat sinks located on both sides of the first chip and connected to the microfluidic channels. The heat sinks 503 are symmetrically arranged on both sides of the first chip 100 and embedded in the first molding compound 300. Their bottom surface may or may not be bonded to the top surface of the microfluidic channel cover plate 502. Figure 2 The diagram shows the case where the heat sink 503 is not bonded to the top surface of the microchannel cover plate 502. The shape of the heat sink 503 is rectangular in this embodiment, but it can also be other shapes, such as trapezoids; this application does not limit its shape. One side of the heat sink 503 is bonded to the microchannel 501, thereby forming a structure that bridges the microchannel 501 and the microchannel cover plate 502 in a direction parallel to the stacking direction, ultimately creating a more efficient heat conduction path. The heat sink 503 has a gap of 20µm to 500µm with the first chip 100, and this gap is completely filled by the first molding compound 300.

[0065] In this embodiment, by providing heat sinks 503 embedded in the first plastic encapsulation structure 300 on both sides of the first chip 100, the heat dissipation area of ​​the heat dissipation structure 500 can be increased, further removing the heat generated by the chip, reducing the junction temperature, and ensuring the reliability and lifespan of the device.

[0066] In one embodiment, the top surfaces of the first chip 100 and the second chip 200 are respectively provided with a first redistribution structure 101 and a second redistribution structure 201, the first redistribution structure 101 and the second redistribution structure 201 are connected by a first metal structure 600, and the side surface of the first metal structure 600 is covered by the second encapsulation structure 400. The top surface of the first chip 100 is provided with the first redistribution structure 101, the first redistribution structure 101 is provided with a pad (not shown in the figure) on the side close to the first chip 100, and the pad is electrically connected to the inside of the first chip 100; the side away from the first chip 100 of the first redistribution structure 101 is provided with a redistribution pad (not shown in the figure), which is used to fix the first metal structure 600. The top surface of the second chip 200 is provided with the second redistribution structure 201, the second redistribution structure 201 is provided with a pad (not shown in the figure) on the side close to the second chip 200, and the pad is electrically connected to the inside of the second chip 200; the second redistribution structure 201 is electrically connected to the first redistribution structure 101 through the first metal structure 600. The side surface of the first metal structure 600 is covered by the second encapsulation structure 400, and the height of the first metal structure 600 is greater than the thickness of the second chip 200, so as to ensure that the first metal structure 600 can penetrate the second encapsulation structure 400.

[0067] In this embodiment, the first redistribution structure 101 on the top surface of the first chip 100 and the second redistribution structure 201 on the top surface of the second chip 200 are connected through the first metal structure 600, which can shorten the connection distance, save space, and improve the packaging density; it can also reduce the signal delay and transmission loss, and improve the signal integrity; at the same time, the first metal structure 600 is completely covered by the second encapsulation structure 400, which can provide mechanical support and protection for the first metal structure 600, and prevent the first metal structure 600 from bending or even breaking during subsequent use.

[0068] In one embodiment, the first redistribution structure 101 and the second redistribution structure 201 are respectively covered by a first dielectric structure 102 and a second dielectric structure 202, the first dielectric structure 102 is disposed between the first plastic package structure 300 and the second plastic package structure 400, the first redistribution structure 101 is connected to the first metal structure 600 at a position not covered by the first dielectric structure 102, and the second redistribution structure 201 is provided with a bump at an end portion beyond the second dielectric structure 202. The first dielectric structure 102 and the second dielectric structure 202 are selected from the group consisting of epoxy, polyimide, bismaleimide-triazine, build-up insulating film, polyphenyl ether, polypropylene, polymethyl acrylate, a combination of the above materials, or other suitable insulating materials; these materials have high mechanical strength, high modulus, good thermal stability, and high adhesion to various substrates and metals, and can provide good support for the first redistribution structure 101 and the second redistribution structure 201; the first dielectric structure 102 is disposed between the first plastic package structure 300 and the second plastic package structure 400, is patterned by a photolithography process, forms an opening exposing the first redistribution structure 101 connected to the first metal structure 600, and covers other surfaces of the first redistribution structure 101 to play a role of electrical insulation and physical protection. The second dielectric structure 202 covers the wiring area of the second redistribution structure 201, remains complete coverage near the center of the second chip 200, and is selectively opened at the edge of the second chip 200 to expose the underlying solder pad (not shown in the figure) of the second redistribution structure 201, thereby providing an interface for bump preparation.

[0069] Specifically, the multi-chip stacked package structure can further include a third chip (not shown in the figure), a fourth chip (not shown in the figure), or more chips. The third chip and the fourth chip can be stacked on the second chip 200, or can be respectively located on the two sides of the first chip 100. If the third chip and the fourth chip are stacked on the second chip 200, the second chip 200 and the third chip are interconnected through the same first metal structure 600 to realize the redistribution structure on the top surfaces of the two chips, and similarly, the fourth chip and the third chip are also interconnected through the same first metal structure 600 to realize the redistribution structure on the top surfaces of the two chips; similar to the micro-flow channels 501 on the two sides of the first chip 100 and the second chip 200, the same micro-flow channels 501 can be arranged on the two sides of the third chip and the fourth chip for heat dissipation, or the same heat dissipation blocks 503 as those on the two sides of the first chip 100 can be arranged on the two sides of the second chip 200 and the third chip to further increase the heat dissipation area and improve the heat dissipation efficiency. If the third chip and the fourth chip are respectively located on the two sides of the first chip 100, the micro-flow channels 501 can be arranged between the first chip 100 and the third chip and between the first chip 100 and the fourth chip, and then extended to the two sides of the second chip 200 and led out through the second plastic package structure 400; or the micro-flow channels 501 can be arranged on the sides of the third chip and the fourth chip away from the first chip 100, and finally extended upward to communicate with the micro-flow channels 501 on the two sides of the second chip 200.

[0070] In the embodiment, the first redistribution structure 101 and the second redistribution structure 201 are respectively coated by the first medium structure 102 and the second medium structure 202 to form electrical insulation and physical protection, so as to avoid bending or even breaking of the first redistribution structure 101 and the second redistribution structure 201 in the subsequent use process.

[0071] The application further provides a preparation method of a multi-chip stacked package structure for forming the multi-chip stacked package structure. Figure 5 , Figure 5 The preparation method of the multi-chip stacked package structure provided by the embodiment of the application is shown in a flowchart. The preparation method of the multi-chip stacked package structure includes the following steps:

[0072] Step S11: providing a first chip 100 and a second chip 200, the second chip 200 is stacked on the first chip 100, and the top surfaces of the first chip 100 and the second chip 200 are respectively provided with a first redistribution structure 101 and a second redistribution structure 201, and the first chip 100 is covered by a first encapsulation structure 300. Please refer to Figure 5 , Figure 5 The first chip 100 and the second chip 200 provided in this step. The first redistribution structure 101 and the second redistribution structure 201 are respectively formed on the top surfaces of the first chip 100 and the second chip 200 by processes such as photolithography and electroplating. By transfer molding process, the first encapsulation structure 300 covering the first chip 100 is formed on both sides of the first chip 100. After the first encapsulation structure 300 is formed, it is ground to make its upper and lower surfaces form a flat plane.

[0073] Step S12: forming a continuous microfluidic channel 501 on both sides of the first chip 100 and the second chip 200, and the microfluidic channel 501 has a gap between the first chip 100 and the second chip 200. By photolithography, laser ablation molding and other processes, the second encapsulation structure 400 and the first encapsulation structure 300 on both sides of the second chip 200 and the first chip 100 are scanned by ablation, respectively, to form the microfluidic channel 501. The microfluidic channel 501 has a gap of 20um-500um between the first chip 100 and the second chip 200.

[0074] In this embodiment, by setting the first encapsulation structure 300 around the first chip 100, mechanical support and protection can be provided for the overall multi-chip stacked packaging structure; by setting the second encapsulation structure 400 around the second chip 200, the second encapsulation structure 400 and the first encapsulation structure 300 are made of the same material, which can buffer the mechanical stress of the stacking interface between the first chip 100 and the second chip 200, and further improve the stability of the packaging structure; by setting the continuous sub-micron microfluidic channel 501 in the encapsulation structure on both sides of the first chip 100 and the second chip 200, a heat dissipation structure around the chip can be formed. This structure can quickly conduct the heat generated by the chip to the outside of the overall multi-chip stacked packaging structure, avoid the accumulation of heat in the encapsulation structure, and ensure the reliability and service life of the device.

[0075] In one embodiment, after the step S12, it further includes:

[0076] Step S13: Forming a micro-channel cover plate 502 on the bottom surface of the first chip 100, the micro-channel cover plate 502 is in close contact with the bottom surface of the first plastic package structure 300, and the top surface of the micro-channel cover plate 502 is in close contact with the bottom surface of the micro-flow channel 501, both of which constitute a complete heat dissipation structure 500. The micro-channel cover plate 502 is preferably made of high-thermal-conductivity material, such as oxygen-free copper or silicon alloy, and its size is matched with the area of the bottom surface of the first plastic package structure 300, and its thickness is controlled within the range of 100-300 um; the top surface of the micro-channel cover plate 502 is polished to improve its smoothness, so as to ensure that it can be in close contact with the bottom surface of the micro-flow channel 501 located above it, and a sealed metal-metal interface is formed therebetween; the top surface of the micro-channel cover plate 502 is in close contact with the bottom surface of the first plastic package structure 300 by means of thermal compression bonding or eutectic bonding process, so that a permanent air-tight seal is formed therebetween, thereby completely enclosing the micro-channel in the cavity formed by the micro-flow channel 501 and the micro-channel cover plate 502. The part of the micro-flow channel 501 beyond the second plastic package structure 400 is provided with a micro-liquid injection hole (not shown in the figure), through which the heat dissipation liquid is injected into the micro-flow channel 501 and the micro-channel cover plate 502, and the heat dissipation liquid can circulate in the heat dissipation structure 500 formed by the micro-flow channel 501 and the micro-channel cover plate 502, thereby timely removing the heat generated by the chip.

[0077] In this embodiment, by arranging the micro-channel cover plate 502 in close contact with the bottom surface of the first plastic package structure 300 on the back surface of the first chip 100, the micro-channel cover plate 502 can form the sealed heat dissipation structure 500 with the micro-flow channel 501, and inject heat dissipation liquid into the heat dissipation structure 500, thereby finally forming a circulating heat dissipation structure capable of autonomous heat dissipation, and such arrangement can realize active heat dissipation of the overall packaging structure; and the size of the micro-flow channel 501 is small, and it can be directly integrated inside the packaging structure, and the heat dissipation liquid in the micro-channel cover plate 502 can spontaneously remove the heat generated by the chip when circulating in the micro-flow channel 501, thereby further reducing the junction temperature of the chip and prolonging the service life of the device.

[0078] In one embodiment, after the step S13, it further includes:

[0079] Step S101: Forming a first dielectric structure 102 on the top surface of the first chip 100, the first dielectric structure 102 covers the first re-wiring structure 101. Please refer to Figure 6 , Figure 6A schematic diagram of the multi-chip stacked package structure formed after step S101. The first dielectric structure 102 is formed by spin coating, exposure, development and other processes, and its material is selected from the group consisting of epoxy resin, polyimide, bismaleimide-triazine, build-up insulating film, polyphenyl ether, polypropylene, polymethyl acrylate, a combination of the above materials or other suitable insulating materials. These materials have high mechanical strength, high modulus, good thermal stability and high adhesion to various substrates and metals, and can provide good support for the first redistribution structure 101. The first dielectric structure 102 covers the wiring area of the first redistribution structure 101, but exposes the redistribution pad area of the first redistribution structure 101 through a lithographic opening for subsequent connection.

[0080] Step S102: Form a first metal structure 600 that penetrates the first dielectric structure 102 and connects the first redistribution structure 101 and the second redistribution structure 201. The first metal structure 600 is formed by an electroplating process, with its bottom surface connected to the redistribution pads on the top surface of the first redistribution structure 101, and its top surface connected to the pads on the top surface of the second redistribution structure 201, finally realizing electrical interconnection between the first redistribution structure 101 and the second redistribution structure 201.

[0081] Step S103: Form a second plastic package structure 400 above the first dielectric structure 102, and the second plastic package structure 400 wraps the second chip 200. The second plastic package structure 400 is formed by a transfer molding process using epoxy molding compound, and is formed above the first dielectric structure 102 and completely covers the side surface of the second chip 200. The second plastic package structure 400 also completely covers the side surface of the first metal structure 600. After forming the second plastic package structure 400, it needs to be ground to form a flat top surface.

[0082] In this embodiment, the first redistribution structure 101 is wrapped by the first dielectric structure 102 to form electrical insulation and physical protection; the first metal structure 600 is completely wrapped by the second plastic package structure 400, which can provide mechanical support and protection for the first metal structure 600, preventing the first metal structure 600 from bending or even breaking during subsequent use.

[0083] In one embodiment, the step of forming the microfluidic channel 501 includes:

[0084] Step S104: etching a first microfluidic channel in the first encapsulation structure 300 on both sides of the first chip 100, the first microfluidic channel being spaced apart from both sides of the first chip 100, and the bottom surface of the first microfluidic channel being in close contact with the top surface of the microfluidic channel cover plate 502. Please refer to Figure 7 , Figure 7 A schematic diagram of a multi-chip stacked package structure formed after the step S104 is performed. The first microfluidic channel is formed in the first encapsulation structure 300 on both sides of the first chip 100 by a laser ablation or ion etching process, and the bottom surface of the first microfluidic channel is in close contact with the microfluidic channel cover plate 502. The spacing between the first microfluidic channel and both sides of the first chip 100 is 20um-500um.

[0085] Step S105: etching a second microfluidic channel in the second encapsulation structure 400 on both sides of the second chip 200, the second microfluidic channel being spaced apart from both sides of the second chip 200, and the second microfluidic channel penetrating the first dielectric structure 102 and communicating with the first microfluidic channel. Please refer to Figure 8 , Figure 8 A schematic diagram of a multi-chip stacked package structure formed after the step S105 is performed. The second microfluidic channel is formed in the second encapsulation structure 400 on both sides of the second chip 200 by the same etching process as the first microfluidic channel, and the second microfluidic channel completely penetrates the first dielectric structure 102 and communicates with the first microfluidic channel. The spacing between the second microfluidic channel and both sides of the second chip 200 is 20um-500um.

[0086] In one embodiment, after the step S103, it further includes:

[0087] Step S106: forming a second dielectric structure 202 on the top surface of the second encapsulation structure 400, and the second dielectric structure 202 being in close contact with the top surface of the second encapsulation structure 400. Please refer to Figure 9 , Figure 9 A schematic diagram of a multi-chip stacked package structure formed after the step S106 is performed. The second dielectric structure 202 is made of the same process and the same material as the first dielectric structure 102, and the second dielectric structure 202 covers the second redistribution structure 201 to provide electrical insulation and physical protection for the second redistribution structure 201.

[0088] Step S107: etching the second dielectric structure 202 to lead out the microfluidic channel 501 through the second dielectric structure 202. Please refer to Figure 10 , Figure 10A schematic view of the multi-chip stacked package structure formed after the step S107 is performed. The second dielectric structure 202 is selectively etched using photolithography and reactive ion etching or laser ablation process. First, an etching pattern is defined by a photolithography mask, which is aligned with the microfluidic channel 501, ensuring that the etching window is directly above the microfluidic channel 501. The etching depth penetrates the thickness of the second dielectric structure 202 until the top surface of the microfluidic channel 501 is exposed, forming a via or trench structure. Finally, the top surface of the microfluidic channel 501 is exposed from the top surface of the second dielectric structure 202.

[0089] By using the preparation method of the multi-chip stacked package structure provided in the present application, most of the process flow can be applied to advanced packaging at the wafer level, the processing precision can be higher, the size can be thinner, and the thickness of the package can be thinner. The multi-chip stacked package structure provided in the present application can timely and quickly export the heat generated by the chip to the outside of the overall package structure, avoid the accumulation of heat in the plastic package structure, and ensure the reliability and service life of the device.

[0090] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0091] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0091] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

Claims

1. A multi-chip stacked package structure, comprising: a first chip (100) distributed on a substrate, a side surface of the first chip (100) being covered by a first plastic package structure (300) ; a second chip (200) stacked on the first chip (100), a side surface and a bottom surface of the second chip (200) being covered by a second plastic package structure (400) ; characterized in that the multi-chip stacked package structure further comprises a heat dissipation structure (500) ; the heat dissipation structure (500) comprises a micro-flow channel (501), a micro-flow channel cover plate (502) and a heat dissipation block (503) ; the micro-flow channel (501) is located on both sides of the first chip (100) and the second chip (200), penetrates a top surface of the second plastic package structure (400) and extends to a bottom surface of the first plastic package structure (300), and a side surface of the micro-flow channel (501) is covered by the first plastic package structure (300) and the second plastic package structure (400) ; wherein the micro-flow channel (501) comprises a first micro-flow channel and a second micro-flow channel, the first micro-flow channel being etched in the first plastic package structure (300) on both sides of the first chip (100), and the second micro-flow channel being etched in the second plastic package structure (400) on both sides of the second chip (200) ; the micro-flow channel cover plate (502) is arranged on a back surface of the first chip (100), in close contact with a bottom surface of the first plastic package structure (300), and a bottom surface of the micro-flow channel (501) is in close contact with a top surface of the micro-flow channel cover plate (502) ; the heat dissipation block (503) is symmetrically arranged on both sides of the first chip (100) and embedded in the first plastic package structure (300) ; one side of the heat dissipation block (503) is bonded to the micro-flow channel (501), there is a gap between the heat dissipation block (503) and the first chip (100), and a bottom surface of the heat dissipation block (503) is bonded to a top surface of the micro-flow channel cover plate (502) ; the heat dissipation block (503) forms a structure bridging the micro-flow channel (501) and the micro-flow channel cover plate (502) in a direction parallel to the stacking direction.

2. The multi-chip stacked package structure of claim 1, wherein, a heat dissipation liquid is injected into the micro-flow channel cover plate (502).

3. The multi-chip stacked package structure of claim 1, wherein, a first redistribution structure (101) and a second redistribution structure (201) are arranged on top surfaces of the first chip (100) and the second chip (200) respectively, the first redistribution structure (101) and the second redistribution structure (201) are connected by a first metal structure (600), and a side surface of the first metal structure (600) is covered by the second plastic package structure (400).

4. The multi-chip stacked package structure of claim 3, wherein, The first redistribution structure (101) and the second redistribution structure (201) are covered by a first dielectric structure (102) and a second dielectric structure (202) respectively, the first dielectric structure (102) is arranged between the first plastic package structure (300) and the second plastic package structure (400), the position of the first redistribution structure (101) not covered by the first dielectric structure (102) is connected with the first metal structure (600), and the second redistribution structure (201) is provided with a bump at the end beyond the second dielectric structure (202).

5. A method for producing a multi-chip stacked package structure for forming the multi-chip stacked package structure according to any one of claims 1 to 4, characterized by, The preparation method of the multi-chip stacked package structure comprises the following steps: Step S11: providing a first chip (100) and a second chip (200), the second chip (200) is arranged on the first chip (100) in a stacked manner, and the top surfaces of the first chip (100) and the second chip (200) are respectively provided with a first redistribution structure (101) and a second redistribution structure (201), and the first chip (100) is covered by a first plastic package structure (300); Step S12: forming a micro-flow channel (501) in communication on both sides of the first chip (100) and the second chip (200), and the micro-flow channel (501) is spaced apart from the first chip (100) and the second chip (200).

6. The method of claim 5, wherein the method further comprises: After the step S12, it further comprises: Step S13: forming a micro-flow channel cover plate (502) on the bottom surface of the first chip (100), the micro-flow channel cover plate (502) is in close contact with the bottom surface of the first plastic package structure (300), and the top surface of the micro-flow channel cover plate (502) is in close contact with the bottom surface of the micro-flow channel (501), and the two constitute a complete heat dissipation structure (500).

7. The method of claim 6, wherein the method further comprises: forming a plurality of through-silicon vias (TSVs) in the substrate; and forming a plurality of redistribution layers (RDLs) on the substrate. After the step S13, it further comprises: Step S101: forming a first dielectric structure (102) on the top surface of the first chip (100), and the first dielectric structure (102) covers the first redistribution structure (101); Step S102: forming a first metal structure (600), the first metal structure (600) penetrates the first dielectric structure (102) and is connected with the first redistribution structure (101) and the second redistribution structure (201); Step S103: forming a second plastic package structure (400), the second plastic package structure (400) is formed above the first dielectric structure (102), and the second plastic package structure (400) wraps the second chip (200).

8. The method of claim 7, wherein the method further comprises: The step of forming the micro-flow channel (501) comprises: Step S104: etching a first micro-flow channel in the first plastic package structure (300) on both sides of the first chip (100), the first micro-flow channel is spaced apart from both sides of the first chip (100), and the bottom surface of the first micro-flow channel is in close contact with the top surface of the micro-flow channel cover plate (502); Step S104: etching a first micro-flow channel in the first plastic package structure (300) on both sides of the first chip (100), the first micro-flow channel is spaced apart from both sides of the first chip (100), and the bottom surface of the first micro-flow channel is in close contact with the top surface of the micro-flow channel cover plate (502); Step S105: etching a second microfluid channel in the second plastic package structure (400) on both sides of the second chip (200), the second microfluid channel being spaced apart from both sides of the second chip (200), and the second microfluid channel penetrating the first medium structure (102) and communicating with the first microfluid channel.

9. The method of claim 7, wherein the method further comprises: forming a plurality of through-silicon vias (TSVs) in the substrate; and forming a plurality of redistribution layers (RDLs) on the substrate. After the step S103, further comprising: Step S106: forming a second medium structure (202) on the top surface of the second plastic package structure (400), and the second medium structure (202) being in close contact with the top surface of the second plastic package structure (400); Step S107: etching the second medium structure (202) to lead the microfluid channel (501) out of the second medium structure (202).

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