Common-mode compensation and offset calibration circuit, chip and equipment
By injecting a constant common-mode compensation current into the differential amplifier and dynamically adjusting the current, the problems of current mirror replication error and insufficient dynamic response are solved, ensuring stable output common-mode voltage, improving signal sampling accuracy and reducing bit error rate.
Patent Information
- Application Number
- CN202510956307.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2025-11-28
AI Technical Summary
In existing technologies, large replication errors, insufficient dynamic response, and transistor operating region offsets in current mirrors lead to unstable common-mode voltage, affecting signal sampling accuracy and bit error rate.
A common-mode compensation and offset calibration circuit is adopted. A constant common-mode compensation current is injected into the output node of the differential amplifier, and the tap current and offset calibration current are dynamically adjusted by the equalizer tap and offset calibration circuit to ensure that the sum of the currents is always equal to the injection current of the cascode current mirror, thereby stabilizing the output common-mode voltage.
It achieves stable output common-mode voltage when the channel attenuation changes, thereby improving signal sampling accuracy and reducing bit error rate.
Smart Images
Figure CN121036713A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a common-mode compensation and offset calibration circuit, chip, and device. Background Technology
[0002] Figure 1 For the summer circuit of an existing wired receiver, Figure 2 The diagram shows the circuit details for common-mode compensation, offset calibration, and the DFE taps. The summer uses resistive load current-mode logic. The DFE has two taps, each consisting of three tap units, with currents It for each unit. DFE1 and I DFE2 To ensure the stability of the common-mode output level of the summer, all tap currents are summed and mirrored to the common-mode compensation module, which injects compensation current I into the summing node. CMP and I CMN To cover a wide range of channel attenuation variations, the DFE's tap current is designed to be programmable and adjustable, thus the common-mode compensation current varies with the tap current. Furthermore, Figure 2 The offset calibration circuit in the middle adjusts the offset compensation current I injected into the summing node by detecting the link offset voltage. OSN and I OSP accomplish.
[0003] To cover I DFE1 / I DFE2 For larger variations, the size of the current mirror needs to be fixed to be "maximum current compatible". Currently, the mirror current has the following limitations when the mirror current varies over a large range:
[0004] 1) Current replication error increases significantly: In practical circuits, the output impedance of the current mirror is finite, resulting in a channel length modulation effect. When I CMP / I CMN When the current mirror changes, its replication accuracy will change with the change in output impedance, resulting in a change in the output common-mode voltage.
[0005] 2) Insufficient dynamic response of the current mirror: Channel changes may cause I DFE1 / I DFE2 Changes, which in turn cause I CMP / I CMN Changes. Due to the presence of parasitic capacitance, the current mirror transistor has a limited charging and discharging speed, making it unable to track I in a timely manner. CMP and I CMN Changes in dynamic response can lead to delays in common-mode compensation current injection, causing transient fluctuations in the common-mode voltage at the summing node, introducing timing errors, and affecting the sampling accuracy of subsequent decision circuits.
[0006] 3) Transistor operating region offset: When I CMP / I CMN Significant changes may cause the transistor's operating region to shift from the saturation region to the linear region. In this case, the image accuracy of the current mirror will decrease significantly, directly affecting the stability of the output common-mode voltage. Summary of the Invention
[0007] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a common-mode compensation and offset calibration circuit, chip and device.
[0008] The first technical solution adopted in this invention is:
[0009] A common-mode compensation and offset calibration circuit, comprising:
[0010] The common-mode compensation circuit is used to inject a constant first common-mode compensation current into the output node ON of the differential amplifier and a constant second common-mode compensation current into the output node OP of the differential amplifier.
[0011] The equalizer taps are used to adjust the tap current (i.e., tap tail current or tail current) according to the control word TAP. The tap current is connected to two nodes ON and OP respectively through two switching transistors. The two switching transistors are controlled by the feedback signals Dn and Dp output by the decision unit.
[0012] The offset calibration circuit includes a first current branch connected to node ON and a second current branch connected to node OP; wherein the current in the two current branches is adjusted according to the magnitude of the tap current so that the sum of the tap current and the current in the offset calibration circuit is equal to the current injected by the common-mode compensation circuit.
[0013] Furthermore, the equalizer taps include a tail current array and a third transistor and a fourth transistor as switching transistors;
[0014] The drain of the third transistor is connected to node ON, the gate inputs feedback signal Dn, and the source is connected to the tail current array; the drain of the fourth transistor is connected to node OP, the gate inputs feedback signal Dp, and the source is connected to the tail current array.
[0015] The tail current array consists of n parallel tail current units, with current values of Io, 2Io, 4Io…2 n-1 Io, controlled by the TAP word <n-1:0>The conduction and cutoff of each tail current unit are controlled separately to adjust the tap current magnitude from 0 to (2). n -1) The current varies between I0 and I0; where I0 represents the minimum unit tap current.
[0016] Furthermore, the offset calibration circuit includes a fifth transistor, a sixth transistor, a first current array, and a second current array;
[0017] The drain of the fifth transistor is connected to node ON, the gate is connected to the bias voltage, and the source is connected to the first current array; the drain of the sixth transistor is connected to node OP, the gate is connected to the bias voltage, and the source is connected to the second current array.
[0018] Both the first and second current arrays are composed of n current units, and are controlled by the OFF_ON control word. <n-1:0>Off-Off <n-1:0>Control, thereby adjusting the magnitude of the offset calibration current.
[0019] Furthermore, the current values on the n current units are 1 / 2Io, Io, 2Io…2 n-2 Io.
[0020] Furthermore, the common-mode compensation circuit includes a first cascode current mirror and a second cascode current mirror, both of which output currents (2...). n -1)I0 / 2.
[0021] Furthermore, the common-mode compensation circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; wherein the seventh transistor and the eighth transistor are NMOS transistors, and the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are PMOS transistors;
[0022] The gate of the seventh transistor is used to connect to an external mirror source, the source is grounded, and the drain is connected to the source of the eighth transistor; the gate of the eighth transistor is connected to a bias voltage, and the drain is connected to the source and gate of the tenth transistor; the drain of the tenth transistor is connected to the source and gate of the ninth transistor; the drain of the ninth transistor is connected to the power supply voltage.
[0023] The drain of the eleventh transistor is connected to the power supply voltage, the gate is connected to the gate of the ninth transistor, and the source is connected to the drain of the twelfth transistor; the gate of the twelfth transistor is connected to the gate of the tenth transistor, and the source is connected to node ON.
[0024] The drain of the thirteenth transistor is connected to the power supply voltage, the gate is connected to the gate of the ninth transistor, and the source is connected to the drain of the fourteenth transistor; the gate of the fourteenth transistor is connected to the gate of the tenth transistor, and the source is connected to node OP.
[0025] Furthermore, the differential amplifier includes a first transistor, a second transistor, and a current source;
[0026] The drain of the first transistor is connected to the power supply voltage through the load, the gate is connected to the first input signal, and the source is connected to the input terminal of the current source; the drain of the second transistor is connected to the power supply voltage through the load, the gate is connected to the second input signal, and the source is connected to the input terminal of the current source; the output terminal of the current source is grounded.
[0027] The output common-mode voltage is:
[0028] AVDD-1 / 2R L (I n +I p )
[0029] Where AVDD is the power supply voltage, R L For load, I n I is the current flowing through the second transistor. p This represents the current flowing through the first transistor.
[0030] The second technical solution adopted in this invention is:
[0031] A chip comprising the common-mode compensation and offset calibration circuit described above.
[0032] The third technical solution adopted in this invention is:
[0033] An electronic device comprising the chip described above.
[0034] The beneficial effects of this invention are: by dynamically adjusting the current on the offset calibration circuit, this invention ensures that the sum of the tap tail current and the offset calibration tail current is always equal to the injection current of the common source cascode current mirror, thereby achieving that the magnitude of the common mode compensation current does not change with the tap current of the equalizer. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a circuit diagram of an existing wired receiver summer;
[0037] Figure 2 This is a schematic diagram of an existing common-mode compensation and offset calibration circuit;
[0038] Figure 3 This is a schematic diagram of the common-mode compensation and offset calibration circuit provided in an embodiment of the present invention. Detailed Implementation
[0039] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.
[0040] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the embodiments of this application. The singular forms "a," "described," and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise expressly limited, terms such as "set," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0041] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0042] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0043] In the description of this application, "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship.
[0044] Terminology Explanation:
[0045] DFE: an abbreviation for Decision Feedback Equalizer, is a digital communication technology used to eliminate inter-symbol interference (ISI).
[0046] OSC: Abbreviation for Misalignment calibration circuit.
[0047] MOSFET: an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.
[0048] In high-speed wired receivers, common-mode compensation and offset calibration are crucial for ensuring signal integrity and system performance. Signals enter the receiver after attenuation through the wired channel, and the equalizer in the receiver compensates for channel attenuation. However, different channels have different attenuations, leading to varying equalizer compensation strengths. This causes common-mode voltage shifts at the summing node, affecting the sampling accuracy of subsequent decision circuits. Common-mode compensation technology dynamically adjusts the injected current to counteract common-mode voltage fluctuations caused by varying equalization strengths, maintaining a stable common-mode level at the summing node. Another important issue is offset calibration. Offset mismatch prevents effective compensation of the accumulated DC offset in the wired receiver's summer, reducing the equivalent eye height. Both of these non-ideal conditions can lead to increased receiver bit error rate or eye closure problems.
[0049] Based on this, and addressing existing technical issues, such as Figure 3 As shown, this embodiment provides a common-mode compensation and offset calibration circuit, including:
[0050] The common-mode compensation circuit is used to inject a constant first common-mode compensation current into the output node ON of the differential amplifier and a constant second common-mode compensation current into the output node OP of the differential amplifier.
[0051] The equalizer tap is used to adjust the tap current according to the control word TAP. The tap current is connected to two nodes ON and OP through two switching transistors respectively. The two switching transistors are controlled by the feedback signals Dn and Dp output by the decision unit.
[0052] The offset calibration circuit includes a first current branch connected to node ON and a second current branch connected to node OP; wherein the current in the two current branches is adjusted according to the magnitude of the tap current so that the sum of the tap current and the current in the offset calibration circuit is equal to the current injected by the common-mode compensation circuit.
[0053] In some embodiments, the differential amplifier includes a first transistor M1, a second transistor M2, and a current source. The drain of the first transistor M1 is connected to a power supply voltage through a load, the gate is connected to a first input signal, and the source is connected to the input terminal of the current source; the drain of the second transistor M2 is connected to a power supply voltage through a load, the gate is connected to a second input signal, and the source is connected to the input terminal of the current source; the output terminal of the current source is grounded.
[0054] It should be noted that the differential amplifier in this embodiment is not limited to the circuit structure described above, and can also be other differential amplifier structures, such as a common source cascode structure, or a two-stage amplifier structure.
[0055] In some embodiments, the equalizer taps include a tail current array and a third transistor M3 and a fourth transistor M4 as switching transistors; the drain of the third transistor M3 is connected to node ON, the gate receives a feedback signal Dn, and the source is connected to the tail current array; the drain of the fourth transistor M4 is connected to node OP, the gate receives a feedback signal Dp, and the source is connected to the tail current array; the tail current array is composed of n parallel tail current units, and the current values of the n tail current units are Io, 2Io, 4Io…2 n-1 Io, controlled by the TAP word <n-1:0>Each tail current unit is controlled to turn on and off separately.
[0056] In some embodiments, the offset calibration circuit includes a fifth transistor M5, a sixth transistor M6, a first current array, and a second current array; the drain of the fifth transistor M5 is connected to node ON, its gate is connected to a bias voltage, and its source is connected to the first current array; the drain of the sixth transistor M6 is connected to node OP, its gate is connected to a bias voltage, and its source is connected to the second current array; both the first and second current arrays are composed of n current units, each controlled by the control word OFF_ON. <n-1:0>Off-Off <n-1:0>Control, thereby adjusting the magnitude of the offset calibration current.
[0057] In some embodiments, the common-mode compensation circuit includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M1. 10 11th transistor M 11 Twelfth transistor M 12 Thirteenth transistor M 13 and the fourteenth transistor M 14 The gate of the seventh transistor M7 is used to connect to an external mirror source, its source is grounded, and its drain is connected to the source of the eighth transistor M8; the gate of the eighth transistor M8 is connected to a bias voltage, and its drain is connected to the tenth transistor M... 10 The source and gate of the tenth transistor M; 10 The drain of the eleventh transistor M9 is connected to the source and gate of the ninth transistor; the drain of the ninth transistor M9 is connected to the power supply voltage; the drain of the eleventh transistor M9 is connected to the source and gate of the ninth transistor M9. 11 The drain is connected to the power supply voltage, the gate is connected to the gate of the ninth transistor M9, and the source is connected to the twelfth transistor M1. 12 The drain of the twelfth transistor M; 12 The gate of the tenth transistor M is connected 10 The gate and source are connected to node ON; the thirteenth transistor M 13 The drain is connected to the power supply voltage, the gate is connected to the gate of the ninth transistor M9, and the source is connected to the fourteenth transistor M1. 14 The drain of the fourteenth transistor M; 14 The gate of the tenth transistor M is connected 10 The gate and source are connected to the OP node.
[0058] The following combination Figure 3 The working principle of the circuit in this embodiment is described as follows: transistors M1 and M2, and two load resistors R. L The tail current source and the tail current source form a differential input amplifier stage, where VP and VN are differential input signals, and I D The current source is the tail current. Ip and In are the currents flowing through transistors M1 and M2, respectively. OP and ON are the differential output nodes. The area within the red dashed box is the common-mode compensation circuit (CMC), M9 to M... 14 A common-source, common-gate current mirror is formed, flowing through M. 11 and M 12 The common-mode compensation current of the branch is directly injected into the ON node and flows through M. 13 and M 14 The common-mode compensation current of the branch is directly injected into the OP node. Unlike existing technologies, in this embodiment, the M-channel current flows through the circuit. 11 and M 12 Branch roads and M 13 and M 14 The magnitude of the common-mode compensation current in the branch does not change with the tap current of the equalizer, remaining constant (2). n -1)I0 / 2 ensures the replication accuracy of the current mirror.
[0059] The green dashed box represents the equalizer taps. Feedback signals Dn and Dp are the output digital signals of the decision circuit, with levels equal to the power supply voltage or 0V. Therefore, M3 and M4 act as switching transistors, being either on or off, and the tail current flows entirely through M3 or M4. The tail current array of the taps consists of n circuits within the black solid boxes, with current magnitudes of Io, 2Io, 4Io…2. n- 1 Io, controlled by the TAP word <n-1:0>The conduction and cutoff of each tail current unit are controlled separately, thereby adjusting the tap current from 0 to (2). n -1) Changes between I0 and I0.
[0060] The area within the blue dashed box represents the offset calibration circuit (OSC). The gate input voltages of M5 and M6 are always the power supply voltage (1V), therefore M5 and M6 are always on. The tail current array of the offset calibration circuit consists of n circuits within the black solid boxes, controlled by the OFF_ON control word. <n-1:0>Off-Off <n-1:0>Control is used to adjust the magnitude of the offset calibration current, with the offset calibration tail current of each chip being equal to half the tap tail current of each chip.
[0061] The following theoretical analysis illustrates the effectiveness of this scheme. The currents flowing through the input differential pair transistors are Ip and In, respectively. Assuming the feedback signals Dn equal "0" and Dp equal "1", if the tap-tail current array controls the switch TAP... <n-1:0>If all taps are closed, the total tap current (2) n -1) I0 flows through transistor M4. Without common-mode compensation and offset calibration modules, the output common-mode output is:
[0062]
[0063] From equation (1), we can see that the output common-mode output varies with the tap current. The output differential-mode output is:
[0064] V diff =R L [I n -I p +(2 n -1)I0] (2)
[0065] In existing technology, the cascode current mirror replicates half of the tap current, i.e., I... com =(2 n -1) A common-mode compensation current of magnitude I0 / 2 is injected into the summer's output nodes ON and OP, respectively. The output common-mode current after common-mode compensation is:
[0066]
[0067] As can be seen from equation (3), the output common-mode current is independent of the tap current and is a fixed value. The compensated output differential-mode current remains unchanged, which is R. L [I n -I p +(2 n -1)I0]. However, when the equalization intensity of the equalizer changes, that is, when the tap and tail currents change, the current replicated by the current mirror will also change, thereby deteriorating the stability of the output common mode.
[0068] To avoid a series of problems caused by the fixed-size current mirror flowing through an adjustable current in the prior art, the common-mode compensation current in this embodiment is fixed at (2 n -1)I0 / 2, based on which common-mode compensation and offset calibration circuits are combined. Its working principle is to perform offset calibration before the receiver starts working. The receiver differential input is shorted to the input common-mode, at which point the tap current is 0, and the current flowing through M5 and M6 in the offset calibration module is 1 / 2(2 n -1) I0, offset calibration is performed based on the output signal "1" or "0" of the decision circuit. If the output is continuously "1", the current flowing through M5 is reduced; if the output is continuously "0", the current flowing through M6 is reduced, until the output is alternating between "0" and "1". When the receiver is working, the offset calibration circuit needs to reduce the current flowing through M5 and M6 by an equal amount according to the tap current. For example, if the tap current is 4I0, the current flowing through M5 and M6 in the offset calibration circuit will be reduced by 2I0 respectively. The purpose is to ensure that the sum of the tap tail current and the offset calibration tail current is equal to the cascode current mirror injection current, and to stabilize the output common mode at AVDD-1 / 2R. L (I n +I p ).
[0069] In the description of this specification, the references to "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0070] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A common-mode compensation and offset calibration circuit, characterized in that, include: The common-mode compensation circuit is used to inject a constant first common-mode compensation current into the output node ON of the differential amplifier and a constant second common-mode compensation current into the output node OP of the differential amplifier. The equalizer tap is used to adjust the tap current according to the control word TAP. The tap current is connected to two nodes ON and OP through two switching transistors respectively. The two switching transistors are controlled by the feedback signals Dn and Dp output by the decision unit. The offset calibration circuit includes a first current branch connected to node ON and a second current branch connected to node OP; in Adjust the current in the two current branches according to the magnitude of the tap current so that the sum of the tap current and the current in the offset calibration circuit is equal to the current injected by the common-mode compensation circuit.
2. The common-mode compensation and offset calibration circuit according to claim 1, characterized in that, The equalizer taps include a tail current array and a third transistor and a fourth transistor as switching transistors. The drain of the third transistor is connected to node ON, the gate inputs feedback signal Dn, and the source is connected to the tail current array; the drain of the fourth transistor is connected to node OP, the gate inputs feedback signal Dp, and the source is connected to the tail current array. The tail current array consists of n parallel tail current units, with current values of Io, 2Io, 4Io…2 n-1 Io, controlled by the TAP word <n-1:0>The conduction and cutoff of each tail current unit are controlled separately to adjust the tap current magnitude from 0 to (2). n -1) The current varies between I0 and I0; where I0 represents the minimum unit tap current.
3. The common-mode compensation and offset calibration circuit according to claim 1, characterized in that, The offset calibration circuit includes a fifth transistor, a sixth transistor, a first current array, and a second current array; The drain of the fifth transistor is connected to node ON, the gate is connected to the bias voltage, and the source is connected to the first current array; the drain of the sixth transistor is connected to node OP, the gate is connected to the bias voltage, and the source is connected to the second current array. Both the first and second current arrays are composed of n current units, and are controlled by the OFF_ON control word. <n-1:0>Off-Off <n-1:0> Control, thereby adjusting the magnitude of the offset calibration current.
4. The common-mode compensation and offset calibration circuit according to claim 3, characterized in that, The current values on the n current units are 1 / 2Io, Io, 2Io…2 n-2 Io.
5. The common-mode compensation and offset calibration circuit according to claim 1, characterized in that, The common-mode compensation circuit includes a first common-source cascode current mirror and a second common-source cascode current mirror, and the output current of both common-source cascode current mirrors is (2... n -1)I0 / 2.
6. The common-mode compensation and offset calibration circuit according to claim 1, characterized in that, The common-mode compensation circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; wherein the seventh and eighth transistors are NMOS transistors, and the ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth transistors are PMOS transistors. The gate of the seventh transistor is used to connect to an external mirror source, the source is grounded, and the drain is connected to the source of the eighth transistor; the gate of the eighth transistor is connected to a bias voltage, and the drain is connected to the source and gate of the tenth transistor; the drain of the tenth transistor is connected to the source and gate of the ninth transistor; the drain of the ninth transistor is connected to the power supply voltage. The drain of the eleventh transistor is connected to the power supply voltage, the gate is connected to the gate of the ninth transistor, and the source is connected to the drain of the twelfth transistor; the gate of the twelfth transistor is connected to the gate of the tenth transistor, and the source is connected to node ON. The drain of the thirteenth transistor is connected to the power supply voltage, the gate is connected to the gate of the ninth transistor, and the source is connected to the drain of the fourteenth transistor; the gate of the fourteenth transistor is connected to the gate of the tenth transistor, and the source is connected to node OP.
7. The common-mode compensation and offset calibration circuit according to claim 1, characterized in that, The differential amplifier includes a first transistor, a second transistor, and a current source; The drain of the first transistor is connected to the power supply voltage through the load, the gate is connected to the first input signal, and the source is connected to the input terminal of the current source; the drain of the second transistor is connected to the power supply voltage through the load, the gate is connected to the second input signal, and the source is connected to the input terminal of the current source; the output terminal of the current source is grounded. The output common-mode voltage is: AVDD-1 / 2R L (IN n +I p ) Where AVDD is the power supply voltage, R L For load, I n I is the current flowing through the second transistor. p This represents the current flowing through the first transistor.
8. A chip, characterized in that, Includes a common-mode compensation and offset calibration circuit as described in any one of claims 1-7.
9. An electronic device, characterized in that, Includes the chip described in claim 8.