A current drive mode differential output driver

Abstract

The application relates to the field of differential output drivers, in particular to a current driving mode differential output driver which comprises an enabling module and a driving module, the driving module comprises an H-bridge branch, the H-bridge branch comprises MOS tubes N5, N6, N7 and N8; the first signal output end of the enabling module is electrically connected with the gate of the MOS tube N5 and the gate of the MOS tube N8, the second signal output end of the enabling module is electrically connected with the gate of the MOS tube N7 and the gate of the MOS tube N6, the source of the MOS tube N5 and the drain of the MOS tube N6 are connected with the outside as an output end D-, the source of the MOS tube N7 and the drain of the MOS tube N8 are connected with the outside as an output end D+, the positive differential voltage or the differential voltage is adjusted by changing the high level or the low level output by the first signal output end, and the constant current is guided to pass through the external load by the H-bridge branch to form the differential voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of differential output driver, in particular to a current drive mode differential output driver. BACKGROUND

[0002] The differential output driver is an electronic device that can convert single-ended or differential signals into differential signal output, and its core function is to generate a pair of signals with equal amplitude and 180° phase difference through complementary output mechanism, so as to effectively suppress common-mode noise and electromagnetic interference during transmission. This kind of driver is usually realized by differential amplifier or special driving circuit, and has high speed characteristics, and its output swing is usually twice that of single-ended driver.

[0003] In analog / digital video transmission, the differential driver can replace the traditional transformer scheme, retain low frequency and DC information while reducing line attenuation; in the ADC driving scene, its fixed gain characteristic and level conversion capability can simplify circuit design.

[0004] The traditional differential output driver uses voltage mode driving, which needs to charge and discharge the load capacitor to change the voltage level, and needs larger driving current to obtain faster edges, slower switching speed and dramatic increase of power consumption and heat. SUMMARY

[0005] The purpose of the present application is to provide a current drive mode differential output driver, which aims to improve the problem of the traditional differential output driver using voltage mode driving, which needs to charge and discharge the load capacitor to change the voltage level, and needs larger driving current to obtain faster edges, slower switching speed and dramatic increase of power consumption and heat.

[0006] To achieve the above purpose, the present application adopts the following technical solutions:

[0007] A current drive mode differential output driver, comprising an enable module, a reference current source module and a driving module, the driving module comprising an H-bridge branch, the H-bridge branch comprising MOS tube N5, MOS tube N6, MOS tube N7, MOS tube N8 and resistors R5 and R6.

[0008] The first signal output end of the enable module is electrically connected with the gate of MOS tube N5 and the gate of MOS tube N8, the second signal output end of the enable module is electrically connected with the gate of MOS tube N7 and the gate of MOS tube N6, the reference current source module outputs driving current to one end of resistor R5, the other end of the resistor R5 is electrically connected with the drain of MOS tube N5 and the drain of MOS tube N7; the source of the MOS tube N5 and the drain of MOS tube N6 are electrically connected and connected with the outside as output end D-, the source of the MOS tube N7 and the drain of MOS tube N8 are electrically connected and connected with the outside as output end D+, and the external load is connected between the output end D- and the output end D+;

[0009] The source of the MOS tube N6 and the source of the MOS tube N8 are both electrically connected with one end of resistor R6, and the other end of the resistor R6 is grounded.

[0010] Further, the enable module comprises MOS tube P10, MOS tube P11, MOS tube P12, MOS tube P13, MOS tube P14, MOS tube P15, MOS tube P16, MOS tube P17, MOS tube P18, MOS tube P19, MOS tube P20, MOS tube P21, MOS tube N11, MOS tube N12, MOS tube N13, MOS tube N14, MOS tube N15, MOS tube N16, MOS tube N17, MOS tube N18;

[0011] The external power supply outputs VCC to the source of MOS tube P10, the source of MOS tube P11, the source of MOS tube P12, the source of MOS tube P13, the source of MOS tube P16, the source of MOS tube P17, the source of MOS tube P18, the source of MOS tube P19;

[0012] The external input signal DIN is input to the gate of MOS tube P10 and the gate of MOS tube N11, the drain of the MOS tube P10 and the drain of the MOS tube N11 are both electrically connected with the gate of MOS tube P11, the gate of MOS tube N12, the gate of MOS tube P16 and the gate of MOS tube N15; the drain of the MOS tube P11 and the drain of the MOS tube N12 are both electrically connected with the gate of MOS tube P14, the gate of MOS tube P15 and the gate of MOS tube N13; the drain of the MOS tube P14 and the drain of the MOS tube N13 are both electrically connected with the drain of MOS tube P15, the drain of MOS tube N14, and as a first signal output end, electrically connected with the gate of MOS tube N5 and the gate of MOS tube N8;

[0013] An external low-level enable signal EN is input to the gate of MOS transistor P12, the gate of MOS transistor P13, the gate of MOS transistor N14, the gate of MOS transistor P18, the gate of MOS transistor P19 and the gate of MOS transistor N18; the drain of MOS transistor P12 is electrically connected to the source of MOS transistor P14, and the drain of MOS transistor P13 is electrically connected to the source of MOS transistor P15;

[0014] The drain of MOS transistor P16 and the drain of MOS transistor N15 are electrically connected to the gate of MOS transistor P17 and the gate of MOS transistor N16, and the drain of MOS transistor P17 and the drain of MOS transistor N16 are electrically connected to the gate of MOS transistor P20, the gate of MOS transistor P21 and the gate of MOS transistor N17; the drain of MOS transistor P18 is electrically connected to the source of MOS transistor P20, and the drain of MOS transistor P19 is electrically connected to the source of MOS transistor P21; the drain of MOS transistor P20 and the drain of MOS transistor N17 are electrically connected to the drain of MOS transistor P21 and the drain of MOS transistor N18, and are electrically connected to the gate of MOS transistor N7 and the gate of MOS transistor N6 as a second signal output end;

[0015] The source of MOS transistor N11, the source of MOS transistor N12, the source of MOS transistor N13, the source of MOS transistor N14, the source of MOS transistor N15, the source of MOS transistor N16, the source of MOS transistor N17 and the source of MOS transistor N18 are all grounded.

[0016] Further, the reference current source module comprises an operational amplifier U100, MOS transistors P0, P1, P2, P3, MOS transistors N0, N1, triodes Q0, Q1, Q2 and resistors R1, R2, R3, R4;

[0017] An external power supply outputs VCC to the source of MOS transistor P0, the source of MOS transistor P1, the source of MOS transistor P2 and the source of MOS transistor P3;

[0018] The gate and drain of MOS transistor P1 are electrically connected to the drain of MOS transistor N0, the gate of MOS transistor P1, the gate of MOS transistor P2 and the gate of MOS transistor P3; the drain of MOS transistor P1 is electrically connected to one end of resistor R1 and one end of resistor R3, the other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input end of operational amplifier U100, the other end of resistor R3 is electrically connected to the emitter of triode Q1 and the non-inverting input end of operational amplifier U100; the other end of resistor R2 is electrically connected to the emitter of triode Q0, and the output end of operational amplifier U100 is electrically connected to the gate of MOS transistor N0;

[0019] The drain of the MOS tube P2 is electrically connected with one end of the resistor R4, and electrically connected with the driving module as a first current output end, and the other end of the resistor R4 is electrically connected with the emitter of the transistor Q2; the drain of the MOS tube P3 is electrically connected with the drain and the gate of the MOS tube N1, and electrically connected with the driving module as a second current output end;

[0020] The source of the MOS tube N0, the source of the MOS tube N1, the base of the transistor Q0, the emitter of the transistor Q0, the base of the transistor Q1, the emitter of the transistor Q1, the base of the transistor Q2, and the emitter of the transistor Q2 are grounded.

[0021] Further, the driving module further comprises a driving branch, a feedback branch and a control branch;

[0022] The reference current source module outputs a reference current to the driving branch and the feedback branch, the output end of the driving branch is electrically connected with the input end of the H-bridge branch and the input end of the feedback branch, and the control branch is connected between the ground end of the H-bridge branch and the control end of the feedback branch.

[0023] Further, the driving branch comprises a MOS tube P4, a MOS tube P5, a MOS tube P6 and a MOS tube N2;

[0024] An external power supply outputs VCC to the source of the MOS tube P4, the source of the MOS tube P5 and the source of the MOS tube P6, and the drain of the MOS tube P6 is electrically connected with the control branch;

[0025] The reference current source module outputs a reference current to the gate of the MOS tube N2, and the drain of the MOS tube N2 is electrically connected with the gate, the drain of the MOS tube P4, the gate of the MOS tube P5 and the gate of the MOS tube P6; the drain of the MOS tube P5 is electrically connected with one end of the resistor R5 and the feedback branch;

[0026] The source of the MOS tube N2 is grounded.

[0027] Further, the feedback branch comprises an operational amplifier U101, a MOS tube P8, a MOS tube N3 and a MOS tube N4;

[0028] An external power supply outputs VCC to the source of the MOS tube P8;

[0029] The reference current source module outputs reference current to the non-inverting input terminal of the operational amplifier U101, the output terminal of the driving branch is electrically connected with the drain of the MOS tube N4 and the inverting input terminal of the operational amplifier U101, the output terminal of the operational amplifier U101 is electrically connected with the gate of the MOS tube P8, the drain of the MOS tube P8 is electrically connected with the gate, the drain of the MOS tube N3 and the gate of the MOS tube N4.

[0030] The source of the MOS tube N3 and the source of the MOS tube N4 are grounded.

[0031] Further, the control branch comprises the MOS tube P7, the MOS tube P9 and the MOS tube N9, the MOS tube N10;

[0032] The external power supply outputs VCC to the source of the MOS tube P7 and the source of the MOS tube P9;

[0033] The source of the MOS tube N6 and the source of the MOS tube N8 are electrically connected with the gate of the MOS tube N9, the output terminal of the driving branch is electrically connected with the drain of the MOS tube N9, the gate of the MOS tube P9 and the gate of the MOS tube N10, the drain of the MOS tube P9 and the drain of the MOS tube N10 are electrically connected with the gate of the MOS tube P7, the drain of the MOS tube P7 is electrically connected with the control terminal of the feedback branch;

[0034] The source of the MOS tube N9 and the source of the MOS tube N10 are grounded.

[0035] Further, the following conditional expressions are met,

[0036] (W / L) N5 (W / L) N6 (W / L) N7 (W / L) N8 ;

[0037] Wherein, (W / L) NX is the width-length ratio of the MOS tube NX, (W / L) N5 is the width-length ratio of the MOS tube N5, (W / L) N6 is the width-length ratio of the MOS tube N6, (W / L) N7 is the width-length ratio of the MOS tube N7, (W / L) N8 is the width-length ratio of the MOS tube N8.

[0038] Further, the following conditional expressions are met,

[0039] (W / L) P0 (W / L) P1 (W / L) P2 (W / L) P3=1:M:N:1;

[0040] R1=R3;

[0041] Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P0 The width-to-length ratio (W / L) of MOSFET P0 P1 The width-to-length ratio (W / L) of MOSFET P1 P2 The width-to-length ratio (W / L) of MOSFET P2 P3 R1 is the width-to-length ratio of MOSFET P3; M and N are proportionality coefficients; R1 is the resistance value of resistor R1, and R3 is the resistance value of resistor R3.

[0042] Furthermore, the following condition is satisfied:

[0043] (W / L) P4 (W / L) P5 =K:J;

[0044] R5=R6;

[0045] Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P4 The width-to-length ratio (W / L) of MOSFET P4 P5 R5 is the width-to-length ratio of MOSFET P5; K and J are proportionality coefficients; R5 is the resistance value of resistor R5, and R6 is the resistance value of resistor R6.

[0046] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0047] The second signal output terminal of the enable module stably outputs a low-level signal. By changing the output level of the first signal output terminal to high or low level, the positive differential voltage or differential voltage can be adjusted to achieve current control and generate a differential signal. The constant current is guided through the H-bridge branch to form a differential voltage through the external load. The current direction can be switched with a small current, without the need to provide a large transient current for charging and discharging the capacitor, which effectively improves the switching speed and reduces the heat generation of power consumption. Attached Figure Description

[0048] Figure 1 This is a circuit diagram of the differential output driver in the current-driven mode described in this invention.

[0049] Figure 2 This is a signal simulation diagram of the differential output driver in the current-driven mode described in this invention;

[0050] Figure 3 This is a simulation diagram of the power supply rejection ratio (PSRR) of the differential output driver in the current-driven mode described in this invention. DETAILED DESCRIPTION

[0051] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0052] In addition, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are based on the orientation or positional relationship shown in the drawings and are merely used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements of the present application must have a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0053] When an element is referred to as being "fixed to" or "set to" or "provided on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0054] Unless otherwise clearly defined and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. EMBODIMENT

[0055] Please refer to Figures 1-3 The embodiment provides a current driving mode differential output driver, which comprises an enabling module, a reference current source module and a driving module. The driving module comprises an H-bridge branch, and the H-bridge branch comprises MOS tubes N5, N6, N7, N8 and resistors R5 and R6.

[0056] The first signal output end of the enable module is electrically connected with the gate of MOS tube N5 and the gate of MOS tube N8, the second signal output end of the enable module is electrically connected with the gate of MOS tube N7 and the gate of MOS tube N6, the reference current source module outputs driving current to the drain of MOS tube N5 and the drain of MOS tube N7, that is, the output end of the reference current source module is electrically connected with one end of resistor R5, the other end of resistor R5 is electrically connected with the drain of MOS tube N5 and the drain of MOS tube N7. The source of MOS tube N5 and the drain of MOS tube N6 are electrically connected and connected with the outside as output end D-, the source of MOS tube N7 and the drain of MOS tube N8 are electrically connected and connected with the outside as output end D+, and an external load is connected between output end D- and output end D+.

[0057] The source of MOS tube N6 and the source of MOS tube N8 are electrically connected with one end of resistor R6, and the other end of resistor R6 is grounded. In this embodiment, resistor R7 is an external load circuit, which refers to an external load.

[0058] The second signal output end of the enable module stably outputs a low-level signal, the positive differential voltage or the differential voltage is adjusted by changing the output of the first signal output end to high level or low level, the differential signal is generated by current control, the differential voltage is formed by the constant current passing through the external load guided by the H-bridge branch, and the current direction can be switched by a small current, without providing a large transient current for charging and discharging the capacitor, thereby effectively improving the switching speed and reducing the power consumption and heat.

[0059] Please refer to Figure 1 The enable module includes MOS tubes P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, N11, N12, N13, N14, N15, N16, N17 and N18.

[0060] An external power supply outputs VCC to the source of MOS tube P10, the source of MOS tube P11, the source of MOS tube P12, the source of MOS tube P13, the source of MOS tube P16, the source of MOS tube P17, the source of MOS tube P18, and the source of MOS tube P19.

[0061] The external input signal DIN is input to the gate of MOS transistor P10 and the gate of MOS transistor N11, and the drain of MOS transistor P10 and the drain of MOS transistor N11 are both electrically connected to the gate of MOS transistor P11, the gate of MOS transistor N12, the gate of MOS transistor P16 and the gate of MOS transistor N15. The drain of MOS transistor P11 and the drain of MOS transistor N12 are both electrically connected to the gate of MOS transistor P14, the gate of MOS transistor P15 and the gate of MOS transistor N13. The drain of MOS transistor P14 and the drain of MOS transistor N13 are both electrically connected to the drain of MOS transistor P15 and the drain of MOS transistor N14, and are electrically connected to the gate of MOS transistor N5 and the gate of MOS transistor N8 as a first signal output terminal.

[0062] The external low-level enable signal EN is input to the gate of MOS transistor P12, the gate of MOS transistor P13, the gate of MOS transistor N14, the gate of MOS transistor P18, the gate of MOS transistor P19 and the gate of MOS transistor N18; the drain of MOS transistor P12 is electrically connected to the source of MOS transistor P14, and the drain of MOS transistor P13 is electrically connected to the source of MOS transistor P15.

[0063] The drain of MOS transistor P16 and the drain of MOS transistor N15 are both electrically connected to the gate of MOS transistor P17 and the gate of MOS transistor N16, and the drain of MOS transistor P17 and the drain of MOS transistor N16 are both electrically connected to the gate of MOS transistor P20, the gate of MOS transistor P21 and the gate of MOS transistor N17; the drain of MOS transistor P18 is electrically connected to the source of MOS transistor P20, and the drain of MOS transistor P19 is electrically connected to the source of MOS transistor P21. The drain of MOS transistor P20 and the drain of MOS transistor N17 are both electrically connected to the drain of MOS transistor P21 and the drain of MOS transistor N18, and are electrically connected to the gate of MOS transistor N7 and the gate of MOS transistor N6 as a second signal output terminal.

[0064] The source of MOS transistor N11, the source of MOS transistor N12, the source of MOS transistor N13, the source of MOS transistor N14, the source of MOS transistor N15, the source of MOS transistor N16, the source of MOS transistor N17 and the source of MOS transistor N18 are all grounded.

[0065] Please refer to Figure 2 the attached Figure 2 is a signal simulation diagram, and the attached Figure 2It can be seen that when the external low level enable signal EN outputs low level and the external input signal DIN outputs high level, the drain of MOS transistor P15 and MOS transistor N14 outputs low level, and the drain of MOS transistor P21 and MOS transistor N18 outputs high level. The driving MOS transistor N6 and MOS transistor N7 are turned on, the driving MOS transistor N5 and MOS transistor N8 are turned off, and the driving current flows from the output terminal D+ to the output terminal D- to the ground, V D+ -V D- >0 generates a positive differential voltage, wherein V D+ is the voltage value at the output terminal D+, and V D- is the voltage value at the output terminal D-.

[0066] When the external low level enable signal EN outputs low level and the external input signal DIN outputs low level: the drain of MOS transistor P15 and MOS transistor N14 outputs high level, and the drain of MOS transistor P21 and MOS transistor N18 outputs low level. The driving MOS transistor N5 and MOS transistor N8 are turned on, the driving MOS transistor N6 and MOS transistor N7 are turned off, and the driving current flows from the output terminal D- to the output terminal D+ to the ground, V D+ -V D- <0 generates a negative differential voltage. When the external low level enable signal EN outputs high level, the circuit does not output a differential level.

[0067] Please refer to Figure 1 , the reference current source module includes operational amplifier U100, MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor N0, MOS transistor N1, triode Q0, triode Q1, triode Q2 and resistors R1, R2, R3, R4.

[0068] The external power supply outputs VCC to the source of MOS transistor P0, the source of MOS transistor P1, the source of MOS transistor P2 and the source of MOS transistor P3.

[0069] The gate and drain of MOS transistor P1 are electrically connected to the drain of MOS transistor N0, the gate of MOS transistor P1, the gate of MOS transistor P2 and the gate of MOS transistor P3. The drain of MOS transistor P1 is electrically connected to one end of resistor R1 and one end of resistor R3, the other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input terminal of operational amplifier U100, the other end of resistor R3 is electrically connected to the emitter of triode Q1 and the non-inverting input terminal of operational amplifier U100. The other end of resistor R2 is electrically connected to the emitter of triode Q0, and the output terminal of operational amplifier U100 is electrically connected to the gate of MOS transistor N0.

[0070] The drain of the MOS tube P2 is electrically connected with one end of the resistor R4, and is electrically connected with the driving module as a first current output end, and the other end of the resistor R4 is electrically connected with the emitter of the transistor Q2. The drain of the MOS tube P3 is electrically connected with the drain and the gate of the MOS tube N1, and is electrically connected with the driving module as a second current output end.

[0071] The source of the MOS tube N0, the source of the MOS tube N1, the base of the transistor Q0, the emitter of the transistor Q0, the base of the transistor Q1, the emitter of the transistor Q1, the base of the transistor Q2, and the emitter of the transistor Q2 are grounded.

[0072] The gate and the drain of the MOS tube P0 are shorted to generate a reference current I REF , and are output to the driving module through the first current output end and the second current output end. The reference current I REF is regulated by the operational amplifier U100. When the current flowing through the MOS tube P1 increases, the voltages at the X node and the Y node increase, the output voltage of the operational amplifier U100 decreases, and the current flowing through the MOS tube N0 decreases, thereby controlling the reference current I REF to decrease. In the embodiment, the X node is located at the non-inverting input end of the operational amplifier U100, and the Y node is located at the inverting input end of the operational amplifier U100.

[0073] Please refer to Figure 1 , the driving module further includes a driving branch, a feedback branch, and a control branch; the reference current source module outputs the reference current to the driving branch and the feedback branch, the output end of the driving branch is electrically connected with the input end of the H-bridge branch and the input end of the feedback branch, and the control branch is connected between the ground end of the H-bridge branch and the control end of the feedback branch. The driving branch provides a driving current for the H-bridge branch; the feedback branch performs negative feedback on the driving circuit to ensure that the driving current maintains a standard value; and the control branch controls the working state of the driving module, so that the driving module is in an off state in the case that no current passes through the H-bridge branch, i.e., in the case of no load, the driving module enters a low-power consumption state, thereby reducing energy consumption.

[0074] Specifically, the driving branch includes a MOS tube P4, a MOS tube P5, a MOS tube P6, and a MOS tube N2.

[0075] An external power supply outputs VCC to the source of the MOS tube P4, the source of the MOS tube P5, and the source of the MOS tube P6, and the drain of the MOS tube P6 is electrically connected with the control branch.

[0076] The reference current source module outputs a reference current to the gate of MOS N2, that is, the drain of MOS P3 and the drain and gate of MOS N1 are electrically connected to the gate of MOS N2. The drain of MOS N2 is electrically connected to the gate and drain of MOS P4, the gate of MOS P5 and the gate of MOS P6; the drain of MOS P5 is electrically connected to one end of resistor R5 and a feedback branch. The source of MOS N2 is grounded.

[0077] MOS N2 and MOS P4 copy the reference current I REF , and the reference current I REF is amplified by MOS P5 and output to the H-bridge branch, the feedback branch and the control branch as a driving circuit.

[0078] Specifically, the feedback branch includes operational amplifier U101, MOS P8 and MOS N3, MOS N4; an external power supply outputs VCC to the source of MOS P8.

[0079] The reference current source module outputs a reference current to the non-inverting input terminal of operational amplifier U101, that is, the drain of MOS P2 is electrically connected to the non-inverting input terminal of operational amplifier U101. The output end of the driving branch is electrically connected to the drain of MOS N4 and the inverting input terminal of operational amplifier U101, that is, the drain of MOS P5 is electrically connected to the drain of MOS N4 and the inverting input terminal of operational amplifier U101. The output end of operational amplifier U101 is electrically connected to the gate of MOS P8, and the drain of MOS P8 is electrically connected to the gate and drain of MOS N3 and the gate of MOS N4;

[0080] The source of MOS N3 and the source of MOS N4 are both grounded.

[0081] MOS P2 copies the reference current I REFThe input voltage VP of the non-inverting input terminal of the operational amplifier U101 is formed by the resistance R4 and the transistor Q2, and the input voltage VP of the non-inverting input terminal of the operational amplifier U101 is raised by the transistor Q2, so as to avoid that the resistance R4 consumes more current to reach the required current. The drain voltage of the MOS tube P5 and the MOS tube N4 is the input voltage VN of the inverting input terminal of the operational amplifier U101. The MOS tube N4 is a sampling tube. When the driving current is too large, the drain voltage of the MOS tube N4 rises, the output voltage of the operational amplifier U101 drops, the gate voltage of the MOS tube N4 is raised, so as to increase the sampling current of the MOS tube N4, and the size of the driving current returns to the standard value. When the driving current is too small, the sampling current of the MOS tube N4 decreases, so that the current flowing through the MOS tube P5 is as much as possible as the driving current, and the size of the driving circuit returns to the standard value.

[0082] Specifically, the control branch includes the MOS tube P7, the MOS tube P9, the MOS tube N9 and the MOS tube N10. The external power supply output VCC is connected to the source of the MOS tube P7 and the source of the MOS tube P9.

[0083] The source of the MOS tube N6 and the source of the MOS tube N8 are electrically connected to the gate of the MOS tube N9. The output end of the driving branch is electrically connected to the drain of the MOS tube N9, the gate of the MOS tube P9 and the gate of the MOS tube N10, that is, the drain of the MOS tube P6 is electrically connected to the drain of the MOS tube N9, the gate of the MOS tube P9 and the gate of the MOS tube N10. The drain of the MOS tube P9 and the drain of the MOS tube N10 are electrically connected to the gate of the MOS tube P7. The drain of the MOS tube P7 is electrically connected to the control end of the feedback branch, that is, the drain of the MOS tube P7 is electrically connected to the output end of the operational amplifier U101. The source of the MOS tube N9 and the source of the MOS tube N10 are grounded.

[0084] In the normal working state, that is, in the state of having a load, the MOS tube N9 is in the open state, and the drain of the MOS tube P9 and the drain of the MOS tube N10 output a high level to close the MOS tube P7. If there is no load, because there is no current path in the H-bridge branch, the resistance R6 does not produce a voltage drop, so that the MOS tube N9 is in the closed state, the drain of the MOS tube P9 and the drain of the MOS tube N10 output a low level to open the MOS tube N7. The MOS tube N7 is turned on to introduce a high level of external VCC, and the MOS tube P8 is closed, so that the driving module is turned off, and the power consumption is effectively reduced.

[0085] Further, the following condition is met,

[0086] (W / L) N5 = (W / L) N6 = (W / L)N7 = (W / L) N8 ;

[0087] (W / L) P0 : (W / L) P1 : (W / L) P2 : (W / L) P3 = 1 : M : N : 1;

[0088] (W / L) P4 : (W / L) P5 = K : J;

[0089] (W / L) N1 = (W / L) N2 ;

[0090] R1 = R3;

[0091] R5 = R6;

[0092] Wherein, (W / L) NX is the width-length ratio of MOS tube NX, i.e. (W / L) N1 is the width-length ratio of MOS tube N1, (W / L) N2 is the width-length ratio of MOS tube N2, (W / L) N5 is the width-length ratio of MOS tube N5, (W / L) N6 is the width-length ratio of MOS tube N6, (W / L) N7 is the width-length ratio of MOS tube N7, (W / L) N8 is the width-length ratio of MOS tube N8.

[0093] Wherein, (W / L) PX is the width-length ratio of MOS tube PX, i.e. (W / L) P0 is the width-length ratio of MOS tube P0, (W / L) P1 is the width-length ratio of MOS tube P1, (W / L) P2 is the width-length ratio of MOS tube P2, (W / L) P3 is the width-length ratio of MOS tube P3, (W / L) P4 is the width-length ratio of MOS tube P4, (W / L) P5 is the width-length ratio of MOS tube P5; M and N are proportional coefficients, K and J are proportional coefficients; R1 is the resistance value of resistor R1, R3 is the resistance value of resistor R3, R5 is the resistance value of resistor R5, and R6 is the resistance value of resistor R6.

[0094] According to the specific circuit in the attached Figure 1 , the current IQ1 flowing through the transistor Q1 is equal to the current flowing through R3, i.e.

[0095] ;

[0096] where V Z is the voltage at the Z node, V X is the voltage at the X node, where the Z node is located at the drain of the MOS P1.

[0097] The open loop gain of the operational amplifier U100 is,

[0098] ;

[0099] where V out is the output voltage of the operational amplifier U100, A OL is the open loop gain of the operational amplifier, and V Y is the voltage at the Y node.

[0100] Due to the negative feedback regulation, i.e.,

[0101] ;

[0102] where β is a feedback coefficient less than 1.

[0103] It can be derived that,

[0104] ;

[0105] Since the A OL of the operational amplifier approaches infinity,

[0106] i.e.,

[0107] ;

[0108] The voltage drop of the resistor R2 can be expressed as,

[0109] ;

[0110] where V BE0 is the base-emitter voltage of the transistor Q0, V BE1 is the base-emitter voltage of the transistor Q1, n is the ratio of the number of transistors Q1 to the number of transistors Q2 in parallel, and V T is the thermal voltage.

[0111] According to the specific circuit in the attached Figure 1 , the current I Q0 flowing through the transistor Q0 is equal to the current flowing through the resistor R2, and because of the negative feedback regulation of the operational amplifier U100, it is,

[0112] ;

[0113] According to the current mirror ratio, the current I flowing through the MOS transistor P1 is M times the current I flowing through the MOS transistor P0 P1 . REF P1 Q0 Q1 Thus, it can be obtained that

[0114] .

[0115] According to the current mirror ratio, the current I flowing through the MOS transistor P2 is N times the current I flowing through the MOS transistor P0 P2 . REF , that is,

[0116] .

[0117] Thus, the input voltage VP of the non-inverting input terminal of the operational amplifier U101 is:

[0118] .

[0119] wherein V BE2 is the base-emitter voltage of the transistor Q2.

[0120] According to the current mirror ratio, the current flowing through the MOS transistor P3 is equal to the current flowing through the MOS transistor P0, and the current I flowing through the MOS transistor P5 is: P5

[0121] .

[0122] Let the driving current flowing through the resistor R5 be I D , and the on-voltage drops of the MOS transistor N5, the MOS transistor N6, the MOS transistor N7 and the MOS transistor N8 can be ignored, then the input voltage VN of the inverting input terminal of the operational amplifier U101 is:

[0123] .

[0124] wherein R7 is the resistance value of the resistor R7.

[0125] Due to the negative feedback regulation of the operational amplifier U101, the driving current I D satisfies the following condition:

[0126] .

[0127] Thus, the differential output voltage V DIFF is:

[0128] .

[0129] ​​​​Therefore, the differential output voltage V DIFF Irrespective of the external voltage VCC, i.e. less affected by power supply noise.

[0130] Please refer to Figure 3 the attached Figure 3 Power Supply Rejection Ratio (PSRR) simulation diagram, from Figure 3 It can be seen that the PSRR of the differential output driver disclosed in the embodiment can reach 86dB, i.e. a large amount of noise on the input power supply only has a negligible effect on the output end. It can be seen that the output level of the differential output driver is determined by the driving current and the load resistance, and is irrelevant to the power supply voltage, thus having a very high power supply rejection ratio.

[0131] The above description is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A current driven mode differential output driver, characterized by, The application comprises an enabling module, a reference current source module and a driving module, wherein the driving module comprises an H-bridge branch, and the H-bridge branch comprises MOS tubes N5, N6, N7, N8 and resistors R5 and R6. The first signal output end of the enabling module is electrically connected with the gate of the MOS tube N5 and the gate of the MOS tube N8, the second signal output end of the enabling module is electrically connected with the gate of the MOS tube N7 and the gate of the MOS tube N6, the reference current source module outputs a driving current to one end of the resistor R5, the other end of the resistor R5 is electrically connected with the drain of the MOS tube N5 and the drain of the MOS tube N7, the source of the MOS tube N5 and the drain of the MOS tube N6 are electrically connected and connected with the outside as an output end D-, the source of the MOS tube N7 and the drain of the MOS tube N8 are electrically connected and connected with the outside as an output end D+, and an external load is connected between the output end D- and the output end D+. The source of the MOS tube N6 and the source of the MOS tube N8 are electrically connected with one end of the resistor R6, and the other end of the resistor R6 is grounded. The second signal output end of the enabling module stably outputs a low-level signal, the positive differential voltage or the differential voltage is adjusted by changing the high-level or low-level output of the first signal output end, the differential signal is generated by current control, the differential voltage is formed by the H-bridge branch directing and guiding the constant current through the external load, and the current direction is switched by a small current, and a large transient current for charging and discharging the capacitor does not need to be provided.

2. The current-mode differential output driver of claim 1, wherein: The enabling module comprises MOS tubes P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, N11, N12, N13, N14, N15, N16, N17 and N18. An external power supply outputs VCC to the source of the MOS tube P10, the source of the MOS tube P11, the source of the MOS tube P12, the source of the MOS tube P13, the source of the MOS tube P16, the source of the MOS tube P17, the source of the MOS tube P18 and the source of the MOS tube P19. The external input signal DIN is input to the gate of MOS tube P10 and the gate of MOS tube N11, the drain of MOS tube P10 and the drain of MOS tube N11 are both electrically connected to the gate of MOS tube P11, the gate of MOS tube N12, the gate of MOS tube P16 and the gate of MOS tube N15; the drain of MOS tube P11 and the drain of MOS tube N12 are both electrically connected to the gate of MOS tube P14, the gate of MOS tube P15 and the gate of MOS tube N13; the drain of MOS tube P14 and the drain of MOS tube N13 are both electrically connected to the drain of MOS tube P15 and the drain of MOS tube N14, and are electrically connected to the gate of MOS tube N5 and the gate of MOS tube N8 as a first signal output end; The external low-level enable signal EN is input to the gate of MOS tube P12, the gate of MOS tube P13, the gate of MOS tube N14, the gate of MOS tube P18, the gate of MOS tube P19 and the gate of MOS tube N18; the drain of MOS tube P12 is electrically connected to the source of MOS tube P14, and the drain of MOS tube P13 is electrically connected to the source of MOS tube P15; The drain of MOS tube P16 and the drain of MOS tube N15 are both electrically connected to the gate of MOS tube P17 and the gate of MOS tube N16, the drain of MOS tube P17 and the drain of MOS tube N16 are both electrically connected to the gate of MOS tube P20, the gate of MOS tube P21 and the gate of MOS tube N17; the drain of MOS tube P18 is electrically connected to the source of MOS tube P20, and the drain of MOS tube P19 is electrically connected to the source of MOS tube P21; the drain of MOS tube P20 and the drain of MOS tube N17 are both electrically connected to the drain of MOS tube P21 and the drain of MOS tube N18, and are electrically connected to the gate of MOS tube N7 and the gate of MOS tube N6 as a second signal output end; The source of MOS tube N11, the source of MOS tube N12, the source of MOS tube N13, the source of MOS tube N14, the source of MOS tube N15, the source of MOS tube N16, the source of MOS tube N17 and the source of MOS tube N18 are all grounded.

3. The current-mode differential output driver of claim 1, wherein: The reference current source module comprises an operational amplifier U100, MOS tubes P0, P1, P2, P3, MOS tubes N0, N1, triodes Q0, Q1, Q2, and resistors R1, R2, R3 and R4; An external power supply output VCC is input to the source of MOS tube P0, the source of MOS tube P1, the source of MOS tube P2 and the source of MOS tube P3; The gate and the drain of the MOS tube P1 are electrically connected with the drain of the MOS tube N0, the gate of the MOS tube P1, the gate of the MOS tube P2 and the gate of the MOS tube P3; the drain of the MOS tube P1 is electrically connected with one end of the resistor R1 and one end of the resistor R3, the other end of the resistor R1 is electrically connected with one end of the resistor R2 and the inverting input terminal of the operational amplifier U100, the other end of the resistor R3 is electrically connected with the emitter of the transistor Q1 and the non-inverting input terminal of the operational amplifier U100; the other end of the resistor R2 is electrically connected with the emitter of the transistor Q0, and the output terminal of the operational amplifier U100 is electrically connected with the gate of the MOS tube N0; The drain of the MOS tube P2 is electrically connected with one end of the resistor R4 and electrically connected with the driving module as a first current output terminal, and the other end of the resistor R4 is electrically connected with the emitter of the transistor Q2; the drain of the MOS tube P3 is electrically connected with the drain and the gate of the MOS tube N1 and electrically connected with the driving module as a second current output terminal; The source of the MOS tube N0, the source of the MOS tube N1, the base of the transistor Q0, the emitter of the transistor Q0, the base of the transistor Q1, the emitter of the transistor Q1, the base of the transistor Q2, and the emitter of the transistor Q2 are grounded.

4. The current-mode differential output driver of claim 1, wherein: The driving module further comprises a driving branch, a feedback branch and a control branch; The reference current source module outputs a reference current to the driving branch and the feedback branch, the output terminal of the driving branch is electrically connected with the input terminal of the H-bridge branch and the input terminal of the feedback branch, and the control branch is connected between the ground terminal of the H-bridge branch and the control terminal of the feedback branch.

5. The current-mode differential output driver of claim 4, wherein: The driving branch comprises MOS tubes P4, P5, P6 and N2; An external power supply outputs VCC to the source of the MOS tube P4, the source of the MOS tube P5 and the source of the MOS tube P6, and the drain of the MOS tube P6 is electrically connected with the control branch; The reference current source module outputs a reference current to the gate of the MOS tube N2, and the drain of the MOS tube N2 is electrically connected with the gate, the drain of the MOS tube P4, the gate of the MOS tube P5 and the gate of the MOS tube P6; the drain of the MOS tube P5 is electrically connected with one end of the resistor R5 and the feedback branch; The source of the MOS tube N2 is grounded.

6. The current-mode differential output driver of claim 4, wherein: The feedback branch comprises an operational amplifier U101, MOS tubes P8, N3 and N4; An external power supply outputs VCC to the source of the MOS tube P8; The reference current source module outputs a reference current to the non-inverting input terminal of the operational amplifier U101, the output terminal of the driving branch is electrically connected with the drain of the MOS tube N4 and the inverting input terminal of the operational amplifier U101, the output terminal of the operational amplifier U101 is electrically connected with the gate of the MOS tube P8, and the drain of the MOS tube P8 is electrically connected with the gate, the drain of the MOS tube N3 and the gate of the MOS tube N4; The source of the MOS tube N3 and the source of the MOS tube N4 are grounded.

7. The current-mode differential output driver of claim 4, wherein: The control branch comprises MOS P7, MOS P9 and MOS N9, MOS N10; An external power supply outputs VCC to the source of MOS P7 and the source of MOS P9; The source of MOS N6 and the source of MOS N8 are electrically connected with the gate of MOS N9, the output end of the drive branch is electrically connected with the drain of MOS N9, the gate of MOS P9 and the gate of MOS N10, the drain of MOS P9 and the drain of MOS N10 are electrically connected with the gate of MOS P7, and the drain of MOS P7 is electrically connected with the control end of the feedback branch; The source of MOS N9 and the source of MOS N10 are grounded.

8. The current-mode differential output driver of claim 1, wherein: The following conditional expression is satisfied, (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 ; wherein (W / L) NX is the width-to-length ratio of MOS transistor NX, i.e. (W / L) N5 is the width-to-length ratio of MOS transistor N5, (W / L) N6 is the width-to-length ratio of MOS transistor N6, (W / L) N7 is the width-to-length ratio of MOS transistor N7, (W / L) N8 is the width-to-length ratio of MOS transistor N8.

9. The current-mode differential output driver of claim 3, wherein: The following conditional expression is satisfied, (W / L) P0 : (W / L) P1 : (W / L) P2 : (W / L) P3 = 1 : M : N : 1; R1=R3; wherein (W / L) PX is the width-length ratio of the MOS transistor PX, i.e. (W / L) P0 is the width-length ratio of the MOS transistor P0, (W / L) P1 is the width-length ratio of the MOS transistor P1, (W / L) P2 is the width-length ratio of the MOS transistor P2, (W / L) P3 is the width-length ratio of the MOS transistor P3; M and N are proportional coefficients; R1 is the resistance value of the resistor R1, and R3 is the resistance value of the resistor R3.

10. The current-mode differential output driver of claim 5, wherein: The following conditional expression is satisfied, (W / L) P4 : (W / L) P5 = K: J; R5=R6; wherein (W / L) PX is the width-length ratio of the MOS transistor PX, i.e. (W / L) P4 is the width-length ratio of the MOS transistor P4, (W / L) P5 is the width-length ratio of the MOS transistor P5; K and J are proportional coefficients; R5 is the resistance value of the resistor R5, and R6 is the resistance value of the resistor R6.

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