Overcurrent protection circuit and chip
Patent Information
- Application Number
- CN202511149735.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2025-11-28
Smart Images
Figure CN121036740A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of integrated circuits, and in particular, to an over-current protection circuit and a chip. BACKGROUND
[0002] An over-current protection (OCP) circuit is a key module for protecting a load in an electronic system. The OCP circuit monitors the current input to the load in real time, and when the load current exceeds a preset current limit threshold, triggers over-current protection, for example, limits the output current or directly cuts off the power supply path, to protect the load from over-current damage.
[0003] At present, over-current protection adopts a feedback loop control strategy, and a closed-loop regulation system is formed by using elements such as an operational amplifier to limit the output current to achieve over-current protection.
[0004] However, when the load rapidly jumps and exceeds the current limit threshold, due to the bandwidth limitation of the feedback loop, the OCP response speed is slow, and the current may continue to rise to produce a large transient peak current during the current limit response. SUMMARY
[0005] Therefore, embodiments of the present application provide an over-current protection circuit and a chip to at least partially solve the above problems.
[0006] According to a first aspect of embodiments of the present application, an over-current protection circuit is provided, comprising: a power NMOS tube, a sampling circuit and a first over-current protection unit; a drain of the power NMOS tube is configured to be electrically connected with a power supply end, a source of the power NMOS tube is configured to be electrically connected with an output end, and the first over-current protection unit is electrically connected with the sampling circuit and a gate of the power NMOS tube, respectively; the sampling circuit is configured to generate a feedback voltage positively correlated with a first current flowing through the power NMOS tube according to the first current; the first over-current protection unit comprises: a comparator, an NMOS tube and a first resistor; a positive input end of the comparator is electrically connected with the sampling circuit, a negative input end of the comparator inputs a first reference voltage, and an output end of the comparator is electrically connected with a gate of the NMOS tube; a drain of the NMOS tube is electrically connected with the gate of the power NMOS tube, a source of the NMOS tube is electrically connected with a first end of the first resistor, and a second end of the first resistor is grounded.
[0007] In a possible implementation, the sampling circuit comprises a sampling unit and a second resistor; an input end of the sampling unit is configured to be electrically connected to the power supply end; an output end of the sampling unit is electrically connected to a first end of the second resistor; the first end of the second resistor is electrically connected to the positive input end of the comparator; and a second end of the second resistor is grounded; the sampling unit is configured to output a second current according to the first current, so that the voltage at the first end of the second resistor is the feedback voltage, where a ratio of the first current to the second current is 1:K.
[0008] In a possible implementation, the first over-current protection unit further comprises an operational amplifier; a negative input end of the operational amplifier is electrically connected to the first end of the second resistor; a positive input end of the operational amplifier inputs a second reference voltage; and an output end of the operational amplifier is electrically connected to the gate of the power NMOS tube, where the second reference voltage is less than the first reference voltage.
[0009] In a possible implementation, the first reference voltage corresponds to a first current threshold where VREF1 is a voltage value of the first reference voltage, and RSET is a resistance value of the second resistor; the second reference voltage corresponds to a second current threshold where VREF2 is a voltage value of the second reference voltage.
[0010] In a possible implementation, the over-current protection circuit further comprises a charge pump; and the charge pump is electrically connected to the gate of the power NMOS tube.
[0011] According to a second aspect of the present application, an over-current protection circuit is provided, comprising a power PMOS tube, a sampling circuit and a second over-current protection unit; a source of the power PMOS tube is configured to be electrically connected to a power supply end; a drain of the power PMOS tube is configured to be electrically connected to an output end; the second over-current protection unit is electrically connected to the sampling circuit and a gate of the power PMOS tube respectively; the sampling circuit is configured to generate a feedback voltage positively related to a first current flowing through the power PMOS tube according to the first current; the second over-current protection unit comprises a comparator, a PMOS tube and a third resistor; a positive input end of the comparator inputs a first reference voltage; a negative input end of the comparator is electrically connected to the sampling circuit; an output end of the comparator is electrically connected to a gate of the PMOS tube; a drain of the PMOS tube is electrically connected to the gate of the power PMOS tube; a source of the PMOS tube is electrically connected to a first end of the third resistor; and a second end of the third resistor is electrically connected to the source of the power PMOS tube.
[0012] In one possible implementation, the sampling circuit includes: a sampling unit and a second resistor; the input terminal of the sampling unit is electrically connected to the power supply terminal, the output terminal of the sampling unit is electrically connected to the first terminal of the second resistor, the first terminal of the second resistor is electrically connected to the negative inverting input terminal of the comparator, and the second terminal of the second resistor is grounded; the sampling unit is configured to output a second current based on the first current, such that the voltage at the first terminal of the second resistor is the feedback voltage, wherein the ratio of the first current to the second current is 1:K.
[0013] In one possible implementation, the second overcurrent protection unit further includes: an operational amplifier; the positive input terminal of the operational amplifier is electrically connected to the first terminal of the second resistor, the negative input terminal of the operational amplifier receives a second reference voltage, and the output terminal of the operational amplifier is electrically connected to the gate of the power NMOS transistor, wherein the second reference voltage is less than the first reference voltage.
[0014] In one possible implementation, the first reference voltage corresponds to a first current threshold. Where VREF1 is the voltage value of the first reference voltage, and RSET is the resistance value of the second resistor; the second current threshold corresponding to the second reference voltage. Wherein, VREF2 is the voltage value of the second reference voltage.
[0015] According to a third aspect of the present application, a chip is provided, including a load circuit and an overcurrent protection circuit as described in the first and / or second aspects of the present application; the input terminal of the overcurrent protection circuit is electrically connected to the power supply terminal, and the output terminal of the overcurrent protection circuit is electrically connected to the load circuit.
[0016] According to the overcurrent protection circuit provided in the embodiments of this application, the overcurrent protection circuit includes a power NMOS transistor, a sampling circuit, and a first overcurrent protection unit. The drain of the power NMOS transistor is electrically connected to the power supply terminal, and the source of the power NMOS transistor is electrically connected to the output terminal. The first overcurrent protection unit is electrically connected to both the sampling circuit and the gate of the power NMOS transistor. The sampling circuit generates a feedback voltage positively correlated with the first current flowing through the power NMOS transistor. The first overcurrent protection unit includes a comparator, an NMOS transistor, and a first resistor. The non-inverting input terminal of the comparator is electrically connected to the sampling circuit, the negative-inverting input terminal of the comparator receives a first reference voltage, the output terminal of the comparator is electrically connected to the gate of the NMOS transistor, the drain of the NMOS transistor is electrically connected to the gate of the power NMOS transistor, the source of the NMOS transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded. This allows for real-time monitoring of current changes in the circuit. When the current exceeds the current-limiting threshold, the gate voltage of the power NMOS transistor is adjusted to reduce the current flowing through it. This ensures that the output load operates within the normal current range, reducing the risk of overcurrent damage to the downstream load. Compared to existing technologies, this solution utilizes a faster-responding and more powerful open-loop path for overcurrent protection, improving the overcurrent protection response speed and avoiding large transient peak currents, thereby enhancing the circuit's safety and reliability. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0018] Figure 1 This is a circuit diagram of an existing overcurrent protection circuit;
[0019] Figure 2 This is a circuit diagram of an overcurrent protection circuit provided in an embodiment of this application;
[0020] Figure 3 This is a circuit diagram of another overcurrent protection circuit provided in an embodiment of this application;
[0021] Figure 4 This is a simulation result diagram of the overcurrent response of an existing overcurrent protection circuit;
[0022] Figure 5 This is a simulation result diagram of the overcurrent response of the overcurrent protection circuit according to an embodiment of this application;
[0023] Figure 6This is a comparison chart of simulation results of the overcurrent response of existing overcurrent protection circuits and the overcurrent protection circuits of the embodiments of this application;
[0024] Figure 7 This is a schematic diagram of an overcurrent protection response process provided in an embodiment of this application;
[0025] Figure 8 This is a circuit diagram of another overcurrent protection circuit provided in the embodiments of this application;
[0026] Figure 9 This is a circuit diagram of another overcurrent protection circuit provided in the embodiments of this application;
[0027] Figure 10 This is a schematic diagram of a chip provided in an embodiment of this application. Detailed Implementation
[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.
[0029] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0030] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0031] As mentioned earlier, the OCP circuit is a key module in electronic systems for ensuring load safety. The OCP circuit monitors the current input to the load in real time. When the load current exceeds a preset current limiting threshold, it triggers overcurrent protection, such as limiting the output current or directly cutting off the power supply to protect the load from overcurrent damage. Currently, overcurrent protection employs a feedback loop control strategy, using operational amplifiers and other components to form a closed-loop regulation system to limit the output current and achieve overcurrent protection. Figure 1 This is a circuit diagram of an existing overcurrent protection circuit, such as... Figure 1 As shown, overcurrent protection is achieved by constructing a closed-loop regulation system using operational amplifiers. To avoid oscillation, divergence, or overshoot and ensure the stability of the feedback loop, measures such as sacrificing bandwidth (e.g., reducing loop gain, increasing phase margin), or introducing compensation networks (e.g., pole compensation, zero compensation) are typically used to suppress high-frequency noise or resonance. However, when the load changes rapidly and exceeds the current limiting threshold, the OCP response is slow due to the bandwidth limitation of the feedback loop, and the current may continue to rise during the current limiting response, generating a large transient peak current.
[0032] In this embodiment, the overcurrent protection circuit includes a power NMOS transistor, a sampling circuit, and a first overcurrent protection unit. The drain of the power NMOS transistor is electrically connected to the power supply terminal, and the source of the power NMOS transistor is electrically connected to the output terminal. The first overcurrent protection unit is electrically connected to both the sampling circuit and the gate of the power NMOS transistor. The sampling circuit generates a feedback voltage positively correlated with the first current flowing through the power NMOS transistor. The first overcurrent protection unit includes a comparator, an NMOS transistor, and a first resistor. The non-inverting input of the comparator is electrically connected to the sampling circuit, the negative input of the comparator receives a first reference voltage, the output of the comparator is electrically connected to the gate of the NMOS transistor, the drain of the NMOS transistor is electrically connected to the gate of the power NMOS transistor, the source of the NMOS transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded. This allows for real-time monitoring of current changes in the circuit. When the current exceeds the current limiting threshold, the gate voltage of the power NMOS transistor is adjusted to reduce the current flowing through it, thereby ensuring the normal current range for the downstream load at the output terminal and reducing the risk of overcurrent damage to the downstream load. Compared with existing technologies, this solution improves the overcurrent protection response speed by constructing an open-loop path with faster response speed and stronger driving capability, thus avoiding the generation of large transient peak currents and improving the safety and reliability of the circuit.
[0033] The overcurrent protection circuit provided in this application is illustrated below through examples.
[0034] Figure 2 This is a circuit diagram of an overcurrent protection circuit provided in an embodiment of this application, such as... Figure 2As shown, the overcurrent protection circuit 100 includes a power NMOS transistor 101, a sampling circuit 102, and a first overcurrent protection unit 103. The drain of the power NMOS transistor 101 is electrically connected to the power supply terminal, and the source of the power NMOS transistor 101 is electrically connected to the output terminal. The first overcurrent protection unit 103 is electrically connected to both the sampling circuit 102 and the gate of the power NMOS transistor 101. The sampling circuit 102 generates a feedback voltage positively correlated with the first current flowing through the power NMOS transistor 101. The first overcurrent protection unit 103 includes a comparator COMP, an NMOS transistor NM, and a first resistor R1. The non-inverting input of comparator COMP is electrically connected to sampling circuit 102, the negative input of comparator COMP is input with the first reference voltage VREF1, the output of comparator COMP is electrically connected to the gate of NMOS transistor NM, the drain of NMOS transistor NM is electrically connected to the gate of power NMOS transistor 101, the source of NMOS transistor NM is electrically connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded.
[0035] The drain of power NMOS transistor 101 serves as the voltage input terminal VIN, used for electrical connection to the power supply terminal. The source of power NMOS transistor 101 serves as the voltage output terminal VOUT, used for electrical connection to the output terminal, providing current to the subsequent load at the output terminal. By changing the gate voltage of power NMOS transistor 101, the first current flowing through power NMOS transistor 101 can be adjusted, thereby adjusting the current flowing into the output terminal through power NMOS transistor 101. Specifically, when power NMOS transistor 101 is operating, i.e., when the gate-source voltage difference of power NMOS transistor 101 is higher than the turn-on threshold voltage, and it is operating in the saturation region or linear region, the gate-source voltage of power NMOS transistor 101 is positively correlated with the first current flowing through power NMOS transistor 101. When the source voltage of power NMOS transistor 101 is fixed, increasing the gate voltage of power NMOS transistor 101 will increase the current flowing through power NMOS transistor 101, and decreasing the gate voltage of power NMOS transistor 101 will decrease the current flowing through power NMOS transistor 101.
[0036] The sampling circuit 102 can sample the current flowing through the power NMOS transistor 101 in real time when the power NMOS transistor 101 is working, and generate a feedback voltage positively correlated with the first current based on the sampled first current flowing through the power NMOS transistor 101. Since the feedback voltage is positively correlated with the first current, the current flowing through the power NMOS transistor 101 can be reflected in real time through the feedback voltage. That is, the larger the feedback voltage, the larger the current flowing through the power NMOS transistor 101 to the output terminal, and the smaller the feedback voltage, the smaller the current flowing through the power NMOS transistor 101 to the output terminal.
[0037] The first overcurrent protection unit 103 is electrically connected to both the sampling circuit 102 and the gate of the power NMOS transistor 101. The first overcurrent protection unit 103 receives the feedback voltage signal from the sampling circuit 102. If the feedback voltage is greater than the first reference voltage VREF1, the first overcurrent protection unit 103 lowers the gate voltage of the power NMOS transistor 101, thereby reducing the current flowing through the power NMOS transistor 101 and achieving overcurrent protection. The first reference voltage VREF1 is a preset current-limiting protection threshold to prevent damage to the downstream load at the output terminal from excessive current. It is understood that since the feedback voltage is positively correlated with the first current flowing through the power NMOS transistor 101, a feedback voltage greater than the first reference voltage VREF1 indicates that the output current of the first current flowing through the power NMOS transistor 101 is greater than the current-limiting threshold.
[0038] The implementation of the overcurrent protection function of the first overcurrent protection unit 103 is described below in conjunction with its specific circuit structure:
[0039] The sampling circuit 102 samples the first current of the power NMOS transistor 101 and outputs a feedback voltage to the non-inverting input of the comparator COMP. The comparator COMP compares the feedback voltage with the first reference voltage VREF1. If the feedback voltage is greater than the first reference voltage VREF1, the comparator COMP outputs a high-level signal to the gate of the NMOS transistor NM. Upon receiving the high-level signal, the gate of the NMOS transistor NM changes from the off state to the on state, forming a path between the gate of the power NMOS transistor 101 and ground. This allows the gate of the power NMOS transistor 101 to discharge to ground through the first resistor R1, causing the gate voltage of the power NMOS transistor 101 to drop rapidly. Consequently, the current flowing through the power NMOS transistor 101 decreases rapidly, achieving overcurrent protection. The value of the first resistor R1 can be set as needed; adjusting the value of the first resistor R1 adjusts the magnitude of the discharge current to match the current-limiting protection requirements of power NMOS transistors 101 of different sizes.
[0040] In this embodiment, the overcurrent protection circuit 100 includes a power NMOS transistor 101, a sampling circuit 102, and a first overcurrent protection unit 103. The drain of the power NMOS transistor 101 is electrically connected to the power supply terminal, and the source of the power NMOS transistor 101 is electrically connected to the output terminal. The first overcurrent protection unit 103 is electrically connected to both the sampling circuit 102 and the gate of the power NMOS transistor 101. The sampling circuit 102 generates a feedback voltage positively correlated with the first current flowing through the power NMOS transistor 101. The first overcurrent protection unit 103 includes a comparator COMP, an NMOS transistor NM, and a first resistor R1. The non-inverting input of comparator COMP is electrically connected to sampling circuit 102, and the negative input of comparator COMP receives the first reference voltage VREF1. The output of comparator COMP is electrically connected to the gate of NMOS transistor NM, the drain of NMOS transistor NM is electrically connected to the gate of power NMOS transistor 101, and the source of NMOS transistor NM is electrically connected to the first terminal of the first resistor R1, with the second terminal of the first resistor R1 grounded. This allows for real-time monitoring of current changes in the circuit. When the current exceeds the current limiting threshold, the gate voltage of power NMOS transistor 101 is adjusted to reduce the current flowing through it, thus ensuring the normal current range for the downstream load and reducing the risk of overcurrent damage to the downstream load. Compared to existing technologies, this solution utilizes a faster-responding and more powerful open-loop path for overcurrent protection, improving the overcurrent protection response speed and avoiding large transient peak currents, thereby enhancing the circuit's safety and reliability.
[0041] Figure 3 This is a circuit diagram of another overcurrent protection circuit provided in an embodiment of this application, such as... Figure 3 As shown, the sampling circuit 102 includes a sampling unit 1021 and a second resistor R2. The input terminal of the sampling unit 1021 is electrically connected to the power supply terminal, the output terminal of the sampling unit 1021 is electrically connected to the first terminal of the second resistor R2, the first terminal of the second resistor R2 is electrically connected to the non-inverting input terminal of the comparator COMP, and the second terminal of the second resistor R2 is grounded. The sampling unit 1021 is used to output a second current based on a first current, so that the voltage at the first terminal of the second resistor R2 is the feedback voltage, wherein the ratio of the first current to the second current is 1:K.
[0042] The sampling unit 1021 samples the first current flowing into the power NMOS transistor 101 through the sampling power supply terminal, and outputs a second current ISNS proportionally to the first terminal of the second resistor R2, where the ratio of the first current to the second current is 1:K. The second current flowing through the second resistor R2 generates a feedback voltage signal at the first terminal of the second resistor R2. This feedback voltage signal is transmitted to the non-inverting input of the comparator COMP, which is electrically connected to the first terminal of the second resistor R2, so that the comparator COMP compares the feedback voltage with the first reference voltage VREF1. The value of the feedback voltage is the product of the second current and the resistance of the second resistor R2. The resistance value of the second resistor R2 can be set according to the actual current limiting requirements to ensure the flexibility of overcurrent protection.
[0043] It should be noted that the specific circuit structure of the sampling unit 1021 can be set with reference to the prior art, and the embodiments of this application are not limited thereto. In one example, the sampling unit 1021 includes a sampling transistor, and the size ratio of the power NMOS transistor 101 to the sampling transistor is 1:K.
[0044] In this embodiment, the sampling circuit 102 includes a sampling unit 1021 and a second resistor R2. The input terminal of the sampling unit 1021 is electrically connected to the power supply terminal, and the output terminal of the sampling unit 1021 is electrically connected to the first terminal of the second resistor R2. The first terminal of the second resistor R2 is electrically connected to the non-inverting input terminal of the comparator COMP, and the second terminal of the second resistor R2 is grounded. The sampling unit 1021 outputs a second current based on a first current, making the voltage at the first terminal of the second resistor R2 a feedback voltage, wherein the ratio of the first current to the second current is 1:K. The sampling unit 1021 converts the first current flowing through the power NMOS transistor 101 into a positively correlated feedback voltage signal, which is then used by the first overcurrent protection unit 103 to determine and execute overcurrent protection based on the feedback voltage signal. This allows the overcurrent protection action to be triggered promptly when the first current exceeds a preset current limiting threshold, protecting the load from overcurrent damage and improving the reliability and safety of the system.
[0045] In one possible implementation, such as Figure 3 As shown, the first overcurrent protection unit 103 includes an operational amplifier A1. The negative input terminal of the operational amplifier A1 is electrically connected to the first terminal of the second resistor R2. The positive input terminal of the operational amplifier A1 is input with a second reference voltage VREF2. The output terminal of the operational amplifier A1 is electrically connected to the gate of the power NMOS transistor 101. The second reference voltage VREF2 is less than the first reference voltage VREF1.
[0046] The non-inverting input of operational amplifier A1 receives a second reference voltage VREF2, and the inverting input is electrically connected to the first terminal of the second resistor R2 to receive a feedback voltage signal. Due to the negative feedback adjustment mechanism of operational amplifier A1, it continuously compares the voltages at the non-inverting and inverting inputs. If the feedback voltage is not equal to the second reference voltage VREF2, an error voltage is generated at the output of operational amplifier A1 and output to the gate of power NMOS transistor 101 to adjust the first current flowing through power NMOS transistor 101, thereby adjusting the feedback voltage positively correlated with the first current until the feedback voltage equals the second reference voltage VREF2. The second reference voltage VREF2 is set according to the maximum operating current requirement of the load to ensure long-term operation of the system within safe power consumption, and the second reference voltage VREF2 is less than the first reference voltage VREF1.
[0047] When the feedback voltage is greater than the second reference voltage VREF2 and less than the first reference voltage VREF1, the output voltage of the operational amplifier A1 decreases, which reduces the gate voltage of the power NMOS transistor 101, thereby reducing the first current flowing through the power NMOS transistor 101, and the feedback voltage decreases accordingly.
[0048] In scenarios with rapid current changes, such as a transition from light load to heavy load at the output or a short circuit at the output, if the feedback voltage is greater than the first reference voltage VREF1, the comparator COMP responds quickly. It forms a low-impedance bleed path between the gate of the power NMOS transistor 101 and ground through the NMOS transistor MN and the first resistor R1, causing the gate voltage of the power NMOS transistor 101 to decrease rapidly. Simultaneously, the operational amplifier A1 assists in reducing the gate voltage drive, causing the first current flowing through the power NMOS transistor 101 to decrease rapidly. When the feedback voltage falls below the first reference voltage VREF1 due to the decrease in the first current, the comparator COMP outputs a low level, turning off the NMOS transistor MN and disconnecting the gate-to-ground bleed path of the power NMOS transistor 101. At the same time, the operational amplifier A1 stabilizes the feedback voltage at the second reference voltage VREF2.
[0049] To more intuitively demonstrate the effect of the overcurrent protection circuit in the embodiments of this application on improving the overcurrent protection response speed, simulations were performed on the existing overcurrent protection circuit and the overcurrent protection circuit in the embodiments of this application. Figure 4 This is a simulation result diagram of the overcurrent response of an existing overcurrent protection circuit, such as... Figure 4As shown, VOUT is the output voltage, VGS-PWR is the gate-source voltage difference of the power NMOS transistor 101, VSNS is the feedback voltage, IOUT is the output current, and I is the current flowing from the gate of the power NMOS transistor 101 into the operational amplifier during the overcurrent response. The second voltage threshold is set to 0.5V. When the output voltage changes, the transient peak current is 6.3589A, and the overcurrent response time is close to 50µs. Figure 5 This is a simulation result diagram of the overcurrent response of the overcurrent protection circuit according to an embodiment of this application, as shown in the figure. Figure 5 As shown in Figure I, the dashed line represents the current flowing into the operational amplifier from the gate of the power NMOS transistor 101 during the overcurrent response, and the solid line represents the current discharging through ground from the gate of the power NMOS transistor 101 during the overcurrent response. The first voltage threshold is set to 1V, and the second voltage threshold is set to 0.5V. The transient peak current generated during the output voltage transition is 1.9513A, and the overcurrent response time is less than 4µs. Figure 6 This is a comparison chart of simulation results of the overcurrent response of existing overcurrent protection circuits and the overcurrent protection circuit of the embodiment of this application, as shown in the figure. Figure 6 As shown, when the output voltage jumps, the dashed line in the figure represents the simulation result of the overcurrent protection circuit of the existing overcurrent protection circuit, and the solid line represents the simulation result of the overcurrent protection circuit of the embodiment of this application. It can be seen that the overcurrent protection circuit of the embodiment of this application can improve the overcurrent protection response speed and reduce the transient peak current.
[0050] In this embodiment, the first overcurrent protection unit 103 includes an operational amplifier A1. The negative input terminal of operational amplifier A1 is electrically connected to the first terminal of the second resistor R2, and the non-inverting input terminal of operational amplifier A1 receives a second reference voltage VREF2. The output terminal of operational amplifier A1 is electrically connected to the gate of the power NMOS transistor 101, wherein the second reference voltage VREF2 is less than the first reference voltage VREF1. Through the negative feedback regulation mechanism of operational amplifier A1, continuous current regulation can be achieved, ensuring that the downstream load at the output operates within the optimal power consumption range. Furthermore, during rapid current changes, it works in conjunction with the comparator COMP to provide overcurrent protection, preventing excessive transient peak current from damaging the downstream load at the output. After the overcurrent is eliminated, the current can be accurately restored to the current required for the downstream load at the output, thereby improving the system's shock resistance and continuous operation stability.
[0051] Figure 7 This is a schematic diagram of an overcurrent protection response process provided in an embodiment of this application, as shown below. Figure 7 As shown, the first current threshold corresponding to the first reference voltage Where VREF1 is the voltage value of the first reference voltage VREF1, and RSET is the resistance value of the second resistor R2. The second current threshold corresponding to the second reference voltage... Wherein, VREF2 is the voltage value of the second reference voltage VREF2.
[0052] When the system is operating normally, the negative feedback regulation mechanism of operational amplifier A1 stabilizes the first current flowing through power NMOS transistor 101 to the second current threshold I. Lim2 The second reference voltage VREF1 corresponds to the second current threshold I. Lim2 :
[0053]
[0054] Where VREF2 is the voltage value of the second reference voltage VREF2, RSET is the resistance value of the second resistor R2, and K is the ratio of the first current and the second current.
[0055] If the current changes rapidly, the first current exceeds the first current threshold I. Lim1 At this time, the comparator COMP responds quickly, reducing the first current. Then, the operational amplifier A1 stabilizes the first current flowing through the power NMOS transistor 101 to the second current threshold I. Lim2 To avoid excessive transient current ( Figure 7 (As shown by the dashed line spike). The first reference voltage VREF1 corresponds to the first current threshold I. Lim1 :
[0056]
[0057] Where VREF1 is the voltage value of the first reference voltage VREF1, RSET is the resistance value of the second resistor R2, and k is the ratio of the first current and the second current.
[0058] The resistance value RSET of the second resistor R2 can be flexibly set according to the actual current limiting requirements to ensure the flexibility of overcurrent protection.
[0059] In this embodiment, the first current threshold corresponding to the first reference voltage Where VREF1 is the voltage value of the first reference voltage VREF1, and RSET is the resistance value of the second resistor R2. The second current threshold corresponding to the second reference voltage... VREF2 is the voltage value of the second reference voltage VREF2. This clarifies the current threshold required for normal system operation and the current threshold for overcurrent protection. Furthermore, the current threshold can be flexibly set by adjusting the resistance value of the second resistor R2, enabling the system to adapt to various operating conditions and improving its flexibility and adaptability.
[0060] In one possible implementation, such as Figure 1As shown, the overcurrent protection circuit 100 also includes a charge pump 104. The charge pump 104 is electrically connected to the gate of the power NMOS transistor 101.
[0061] After the comparator COMP in the first overcurrent protection unit 103 finishes its overcurrent protection action and the discharge path is disconnected, the gate voltage of the power transistor NMOS 101 is reduced to a certain level, which may cause the first current flowing into the power NMOS 101 to be insufficient to meet the current required by the output stage load. The charge pump 104 can provide a stable drive voltage to the gate of the power transistor NMOS 101, thereby raising the gate voltage of the power NMOS 101 to a suitable level, so that the current output through the power NMOS 101 meets the operating current required by the output stage load.
[0062] In this embodiment, the overcurrent protection circuit 100 further includes a charge pump 104. The charge pump 104 is electrically connected to the gate of the power NMOS transistor 101. The charge pump 104 can provide a stable drive voltage to the gate of the power NMOS transistor 101, ensuring that the power NMOS transistor 101 can reliably turn on and off during normal operation. Furthermore, after the overcurrent protection ends, it can quickly boost the gate voltage of the power NMOS transistor 101 to a suitable level required by the output stage, restoring sufficient conduction capability to the power transistor. This ensures that the current output through the power NMOS transistor 101 meets the operating current required by the output stage load, thereby guaranteeing the continuous and stable operation of the output stage load and improving the stability and overall reliability of the system. This ensures the safety of the system.
[0063] Figure 8 This is a circuit diagram of another overcurrent protection circuit provided in the embodiments of this application, such as... Figure 8 As shown, the overcurrent protection circuit 200 includes a power PMOS transistor 201, a sampling circuit 202, and a second overcurrent protection unit 203. The source of the power PMOS transistor 201 is electrically connected to the power supply terminal, and the drain of the power PMOS transistor 201 is electrically connected to the output terminal. The second overcurrent protection unit 203 is electrically connected to the sampling circuit 202 and the gate of the power PMOS transistor 201, respectively. The sampling circuit 202 generates a feedback voltage positively correlated with the first current flowing through the power PMOS transistor 201. The second overcurrent protection unit 203 includes a comparator COMP, a PMOS transistor PM, and a third resistor R3. The non-inverting input terminal of the comparator COMP receives a first reference voltage VREF1, the non-inverting input terminal of the comparator COMP is electrically connected to the sampling circuit 202, and the output terminal of the comparator COMP is electrically connected to the gate of the PMOS transistor PM. The drain of PMOS transistor PM is electrically connected to the gate of power PMOS transistor 201, the source of PMOS transistor PM is electrically connected to the first end of the third resistor R3, and the second end of the third resistor R3 is electrically connected to the source of power PMOS transistor 201.
[0064] The source of the power PMOS transistor 201 serves as the voltage input terminal (VIN), which is electrically connected to the power supply terminal. The drain of the power PMOS transistor 201 serves as the voltage output terminal (VOUT), which is electrically connected to the output terminal, providing current to the subsequent load. By changing the gate voltage of the power PMOS transistor 201, the first current flowing through the power PMOS transistor 201 can be adjusted, thereby regulating the current flowing into the output terminal through the power PMOS transistor 201. Specifically, when the power PMOS transistor 201 is operating, i.e., when the absolute value of the gate-source voltage difference of the power PMOS transistor 201 is higher than the absolute value of the turn-on threshold voltage, and it is operating in the saturation region or linear region, the gate-source voltage difference of the power PMOS transistor 201 is positively correlated with the first current flowing through the power PMOS transistor 201. When the source voltage of the power PMOS transistor 201 is fixed, adjusting the gate voltage of the power PMOS transistor 201 to decrease (making it more negative relative to the source voltage) will increase the gate-source voltage difference of the power PMOS transistor 201, thereby increasing the current flowing through the power PMOS transistor 201. Increasing the gate voltage of the power PMOS transistor 201 (making its negative voltage difference relative to the source voltage smaller) will reduce the gate-source voltage difference of the power PMOS transistor 201, thereby reducing the current flowing through the power PMOS transistor 201.
[0065] The sampling circuit 202 can sample the current flowing through the power PMOS transistor 201 in real time when the power PMOS transistor 201 is working, and generate a feedback voltage positively correlated with the first current based on the sampled first current flowing through the power PMOS transistor 201. Since the feedback voltage is positively correlated with the first current, the current flowing through the power PMOS transistor 201 can be reflected in real time through the feedback voltage. That is, the larger the feedback voltage, the larger the current flowing through the power PMOS transistor 201 to the output terminal, and the smaller the feedback voltage, the smaller the current flowing through the power PMOS transistor 201 to the output terminal.
[0066] The second overcurrent protection unit 203 is electrically connected to both the sampling circuit 202 and the gate of the power PMOS transistor 201. The second overcurrent protection unit 203 can receive the feedback voltage signal from the sampling circuit 202. If the feedback voltage is greater than the first reference voltage VREF1, the second overcurrent protection unit 203 increases the gate voltage of the power PMOS transistor 201, thereby reducing the current flowing through the power PMOS transistor 201 and achieving overcurrent protection. The first reference voltage VREF1 is a preset current-limiting protection threshold to prevent damage to the downstream load at the output terminal from excessive current. It is understandable that since the feedback voltage is positively correlated with the first current flowing through the power PMOS transistor 201, a feedback voltage greater than the first reference voltage VREF1 indicates that the output current of the first current flowing through the power PMOS transistor 201 is greater than the current-limiting threshold.
[0067] The implementation of the overcurrent protection function of the second overcurrent protection unit 203 is described below in conjunction with its specific circuit structure:
[0068] The sampling circuit 202 samples the first current of the power PMOS transistor 201 and outputs a feedback voltage to the negative input of the comparator COMP. The comparator COMP compares the feedback voltage with the first reference voltage VREF1. If the feedback voltage is greater than the first reference voltage VREF1, the comparator COMP outputs a low-level signal to the gate of the PMOS transistor PM. After receiving the low-level signal, the PMOS transistor PM changes from the off state to the on state. A path is formed between the gate and source of the power PMOS transistor 201 through the PMOS transistor PM and the third resistor R3. This path pulls up the gate potential of the power PMOS transistor 201, bringing it closer to the source potential. Therefore, the absolute value of the gate-source voltage of the power PMOS transistor 201 decreases rapidly, thereby rapidly reducing the current flowing through the power PMOS transistor 201, achieving overcurrent protection. The value of the third resistor R3 can be set as needed. The magnitude of the discharge current can be adjusted by adjusting the value of the third resistor R3 to match the current limiting protection requirements of different sized power PMOS transistors 201.
[0069] In this embodiment, the overcurrent protection circuit 200 includes a power PMOS transistor 201, a sampling circuit 202, and a second overcurrent protection unit 203. The source of the power PMOS transistor 201 is electrically connected to the power supply terminal, and the drain of the power PMOS transistor 201 is electrically connected to the output terminal. The second overcurrent protection unit 203 is electrically connected to the sampling circuit 202 and the gate of the power PMOS transistor 201, respectively. The sampling circuit 202 generates a feedback voltage positively correlated with the first current flowing through the power PMOS transistor 201. The second overcurrent protection unit 203 includes a comparator COMP, a PMOS transistor PM, and a third resistor R3. The non-inverting input terminal of the comparator COMP receives a first reference voltage VREF1, the non-inverting input terminal of the comparator COMP is electrically connected to the sampling circuit 202, and the output terminal of the comparator COMP is electrically connected to the gate of the PMOS transistor PM. The drain of PMOS transistor PM is electrically connected to the gate of power PMOS transistor 201, and the source of PMOS transistor PM is electrically connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is electrically connected to the source of power PMOS transistor 201. This allows for real-time monitoring of current changes in the circuit. When the current exceeds the current limiting threshold, the gate voltage of power PMOS transistor 201 is adjusted to reduce the current flowing through it, thus ensuring the normal current range for the downstream load and reducing the risk of overcurrent damage. Compared to existing technologies, this solution utilizes a faster-responding and more powerful open-loop path for overcurrent protection, improving the overcurrent protection response speed and avoiding large transient peak currents, thereby enhancing the circuit's safety and reliability.
[0070] Figure 9 This is a circuit diagram of another overcurrent protection circuit provided in the embodiments of this application, such as... Figure 9 As shown, the sampling circuit 202 includes a sampling unit 2021 and a second resistor R2. The input terminal of the sampling unit 2021 is electrically connected to the power supply terminal, the output terminal of the sampling unit 2021 is electrically connected to the first terminal of the second resistor R2, the first terminal of the second resistor R2 is electrically connected to the negative inverting input terminal of the comparator COMP, and the second terminal of the second resistor R2 is grounded. The sampling unit 2021 is used to output a second current based on a first current, making the voltage at the first terminal of the second resistor R2 the feedback voltage, wherein the ratio of the first current to the second current is 1:K.
[0071] The sampling unit 1021 samples the first current flowing into the power PMOS transistor 201 through the sampling power supply terminal, and outputs a second current ISNS proportionally to the first terminal of the second resistor R2, where the ratio of the first current to the second current is 1:K. The second current flowing through the second resistor R2 generates a feedback voltage signal at the first terminal of the second resistor R2. This feedback voltage signal is transmitted to the negative input terminal of the comparator COMP, which is electrically connected to the first terminal of the second resistor R2, so that the comparator COMP compares the feedback voltage with the first reference voltage VREF1. The value of the feedback voltage is the product of the second current and the resistance of the second resistor R2. The resistance value of the second resistor R2 can be set according to the actual current limiting requirements to ensure the flexibility of overcurrent protection.
[0072] It should be noted that the specific circuit structure of the sampling unit 1021 can be set with reference to the prior art, and the embodiments of this application are not limited thereto. In one example, the sampling unit 1021 includes a sampling transistor, and the size ratio of the power PMOS transistor 201 to the sampling transistor is 1:K.
[0073] In this embodiment, the sampling circuit 202 includes a sampling unit 2021 and a second resistor R2. The input terminal of the sampling unit 2021 is electrically connected to the power supply terminal, and the output terminal of the sampling unit 2021 is electrically connected to the first terminal of the second resistor R2. The first terminal of the second resistor R2 is electrically connected to the negative inverting input terminal of the comparator COMP, and the second terminal of the second resistor R2 is grounded. The sampling unit 2021 outputs a second current based on a first current, making the voltage at the first terminal of the second resistor R2 a feedback voltage, wherein the ratio of the first current to the second current is 1:K. The sampling unit 2021 converts the first current flowing through the power PMOS transistor 201 into a positively correlated feedback voltage signal, which is then used by the second overcurrent protection unit 203 to determine and execute overcurrent protection based on the feedback voltage signal. This allows the overcurrent protection action to be triggered promptly when the first current exceeds a preset current limiting threshold, protecting the load from overcurrent damage and improving the reliability and safety of the system.
[0074] In one possible implementation, such as Figure 9 As shown, the second overcurrent protection unit 203 includes an operational amplifier A2. The non-inverting input terminal of the operational amplifier A2 is electrically connected to the first terminal of the second resistor R2. The negative-inverting input terminal of the operational amplifier A2 is input with a second reference voltage VREF2. The output terminal of the operational amplifier A2 is electrically connected to the gate of the power PMOS transistor 201. The second reference voltage VREF2 is less than the first reference voltage VREF1.
[0075] The non-inverting input of operational amplifier A2 is electrically connected to the first end of the second resistor R2 to input a feedback voltage signal, while the negative input of operational amplifier A2 receives a second reference voltage VREF2. Due to the negative feedback adjustment mechanism of operational amplifier A2, it continuously compares the voltages at the non-inverting and negative inputs. If the feedback voltage is not equal to the second reference voltage VREF2, an error voltage is generated at the output of operational amplifier A2 and output to the gate of power PMOS transistor 201 to adjust the first current flowing through power PMOS transistor 201, thereby adjusting the feedback voltage positively correlated with the first current until the feedback voltage equals the second reference voltage VREF2. The second reference voltage VREF2 is set according to the maximum operating current requirement of the load to ensure long-term operation of the system within safe power consumption, and the second reference voltage VREF2 is less than the first reference voltage VREF1.
[0076] When the feedback voltage is greater than the second reference voltage VREF2 and less than the first reference voltage VREF1, the output voltage of the operational amplifier A2 increases, which increases the gate voltage of the power PMOS transistor 201 to reduce the first current flowing through the power PMOS transistor 201, and the feedback voltage decreases accordingly.
[0077] In scenarios with rapid current changes, such as a transition from light load to heavy load at the output or a short circuit at the output, if the feedback voltage is greater than the first reference voltage VREF1, the comparator COMP responds quickly. It forms a low-impedance pull-up path between the gate and source of the power PMOS transistor 201 through the PMOS transistor PM and the third resistor R3, causing the gate voltage of the power PMOS transistor 201 to rise rapidly. Simultaneously, the operational amplifier A2 assists in increasing the gate voltage drive, causing the first current flowing through the power PMOS transistor 201 to decrease rapidly. When the feedback voltage falls below the first reference voltage VREF1 due to the decrease in the first current, the comparator COMP outputs a high level, turning off the PMOS transistor PM and disconnecting the pull-up path from the gate to the source of the power PMOS transistor 201. At the same time, the operational amplifier A2 stabilizes the feedback voltage at the second reference voltage VREF2.
[0078] In this embodiment, the second overcurrent protection unit 203 includes an operational amplifier A2. The non-inverting input terminal of operational amplifier A2 is electrically connected to the first terminal of the second resistor R2, and the negative-inverting input terminal of operational amplifier A2 receives a second reference voltage VREF2. The output terminal of operational amplifier A2 is electrically connected to the gate of the power PMOS transistor 201, wherein the second reference voltage VREF2 is less than the first reference voltage VREF1. Through the negative feedback regulation mechanism of operational amplifier A2, continuous current regulation can be achieved, ensuring that the downstream load at the output operates within the optimal power consumption range. Furthermore, during rapid current fluctuations, it works in conjunction with the comparator COMP to provide overcurrent protection, preventing excessive transient peak current from damaging the downstream load at the output. After the overcurrent is eliminated, the current can be accurately restored to the current required for the downstream load at the output, thereby improving the system's shock resistance and continuous operation stability.
[0079] In one possible implementation, the first reference voltage corresponds to a first current threshold. Where VREF1 is the voltage value of the first reference voltage VREF1, and RSET is the resistance value of the second resistor R2. The second current threshold corresponding to the second reference voltage... Wherein, VREF2 is the voltage value of the second reference voltage VREF2.
[0080] When the system is operating normally, the negative feedback regulation mechanism of operational amplifier A2 stabilizes the first current flowing through power PMOS transistor 201 to the second current threshold I. Lim2 The second reference voltage VREF1 corresponds to the second current threshold I. Lim2 :
[0081]
[0082] Where VREF2 is the voltage value of the second reference voltage VREF2, RSET is the resistance value of the second resistor R2, and K is the ratio of the first current and the second current.
[0083] If the current changes rapidly, the first current exceeds the first current threshold I. Lim1 At this time, the comparator COMP responds quickly, reducing the first current. Then, the operational amplifier A2 stabilizes the first current flowing through the power PMOS transistor 201 to the second current threshold I. Lim2 To avoid excessive transient current ( Figure 7 (As shown by the dashed line spike). The first reference voltage VREF1 corresponds to the first current threshold I. Lim1 :
[0084]
[0085] Where VREF1 is the voltage value of the first reference voltage VREF1, RSET is the resistance value of the second resistor R2, and K is the ratio of the first current and the second current.
[0086] The resistance value RSET of the second resistor R2 can be flexibly set according to the actual current limiting requirements to ensure the flexibility of overcurrent protection.
[0087] In this embodiment, the first current threshold corresponding to the first reference voltage Where VREF1 is the voltage value of the first reference voltage VREF1, and RSET is the resistance value of the second resistor R2. The second current threshold corresponding to the second reference voltage... VREF2 is the voltage value of the second reference voltage VREF2. This clarifies the current threshold required for normal system operation and the current threshold for overcurrent protection. Furthermore, the current threshold can be flexibly set by adjusting the resistance value of the second resistor R2, enabling the system to adapt to various operating conditions and improving its flexibility and adaptability.
[0088] Figure 10 This is a schematic diagram of a chip provided in an embodiment of this application, such as... Figure 10 As shown, the chip 10 includes a load circuit and an overcurrent protection circuit 100 and / or an overcurrent protection circuit 200 as described in any of the above embodiments.
[0089] The input terminals of overcurrent protection circuit 100 and / or overcurrent protection circuit 200 are used to be electrically connected to the power supply terminal, and the output terminals of overcurrent protection circuit 100 and / or overcurrent protection circuit 200 are electrically connected to the load circuit.
[0090] In the embodiments of this application, the overcurrent protection circuit 100 can be the overcurrent protection circuit 100 in any of the above embodiments, and the overcurrent protection circuit 200 can be the overcurrent protection circuit 200 in any of the above embodiments. Since they are based on the same inventive concept as the foregoing embodiments, they can achieve the same effect. The specific implementation process can be referred to the description in the foregoing embodiments, and will not be repeated here.
[0091] It should be noted that the chip 10 can be an overcurrent protection chip or other chips with overcurrent protection function, all of which are within the protection scope of the embodiments of this application.
[0092] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.
[0093] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.
[0094] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.
Claims
1. An overcurrent protection circuit, characterized in that, include: Power NMOS transistor, sampling circuit and first overcurrent protection unit; The drain of the power NMOS transistor is electrically connected to the power supply terminal, the source of the power NMOS transistor is electrically connected to the output terminal, and the first overcurrent protection unit is electrically connected to the sampling circuit and the gate of the power NMOS transistor respectively. The sampling circuit is used to generate a feedback voltage that is positively correlated with the first current flowing through the power NMOS transistor. The first overcurrent protection unit includes: a comparator, an NMOS transistor, and a first resistor; The positive input terminal of the comparator is electrically connected to the sampling circuit, the negative input terminal of the comparator receives the first reference voltage, and the output terminal of the comparator is electrically connected to the gate of the NMOS transistor. The drain of the NMOS transistor is electrically connected to the gate of the power NMOS transistor, the source of the NMOS transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded.
2. The overcurrent protection circuit according to claim 1, characterized in that, The sampling circuit includes: a sampling unit and a second resistor; The input terminal of the sampling unit is electrically connected to the power supply terminal, the output terminal of the sampling unit is electrically connected to the first terminal of the second resistor, the first terminal of the second resistor is electrically connected to the non-inverting input terminal of the comparator, and the second terminal of the second resistor is grounded. The sampling unit is used to output a second current based on the first current, so that the voltage at the first end of the second resistor is the feedback voltage, wherein the ratio of the first current to the second current is 1:K.
3. The overcurrent protection circuit according to claim 2, characterized in that, The first overcurrent protection unit further includes: an operational amplifier; The negative input terminal of the operational amplifier is electrically connected to the first terminal of the second resistor, the non-inverting input terminal of the operational amplifier receives a second reference voltage, and the output terminal of the operational amplifier is electrically connected to the gate of the power NMOS transistor, wherein the second reference voltage is less than the first reference voltage.
4. The overcurrent protection circuit according to claim 3, characterized in that, The first current threshold corresponding to the first reference voltage Wherein, VREF1 is the voltage value of the first reference voltage, and RSET is the resistance value of the second resistor; The second current threshold corresponding to the second reference voltage Wherein, VREF2 is the voltage value of the second reference voltage.
5. The overcurrent protection circuit according to any one of claims 1-4, characterized in that, The overcurrent protection circuit also includes: a charge pump; The charge pump is electrically connected to the gate of the power NMOS transistor.
6. An overcurrent protection circuit, characterized in that, include: Power PMOS transistor, sampling circuit, and second overcurrent protection unit; The source of the power PMOS transistor is electrically connected to the power supply terminal, the drain of the power PMOS transistor is electrically connected to the output terminal, and the second overcurrent protection unit is electrically connected to the sampling circuit and the gate of the power PMOS transistor respectively. The sampling circuit is used to generate a feedback voltage that is positively correlated with the first current based on the first current flowing through the power PMOS transistor. The second overcurrent protection unit includes: a comparator, a PMOS transistor, and a third resistor; The first reference voltage is input to the non-inverting input terminal of the comparator, the negative input terminal of the comparator is electrically connected to the sampling circuit, and the output terminal of the comparator is electrically connected to the gate of the PMOS transistor. The drain of the PMOS transistor is electrically connected to the gate of the power PMOS transistor, the source of the PMOS transistor is electrically connected to the first end of the third resistor, and the second end of the third resistor is electrically connected to the source of the power PMOS transistor.
7. The overcurrent protection circuit according to claim 6, characterized in that, The sampling circuit includes: a sampling unit and a second resistor; The input terminal of the sampling unit is electrically connected to the power supply terminal, the output terminal of the sampling unit is electrically connected to the first terminal of the second resistor, the first terminal of the second resistor is electrically connected to the negative input terminal of the comparator, and the second terminal of the second resistor is grounded. The sampling unit is used to output a second current based on the first current, so that the voltage at the first end of the second resistor is the feedback voltage, wherein the ratio of the first current to the second current is 1:K.
8. The overcurrent protection circuit according to claim 7, characterized in that, The second overcurrent protection unit further includes: an operational amplifier; The non-inverting input terminal of the operational amplifier is electrically connected to the first terminal of the second resistor, the negative-inverting input terminal of the operational amplifier receives a second reference voltage, and the output terminal of the operational amplifier is electrically connected to the gate of the power NMOS transistor, wherein the second reference voltage is less than the first reference voltage.
9. The overcurrent protection circuit according to claim 8, characterized in that, The first current threshold corresponding to the first reference voltage Wherein, VREF1 is the voltage value of the first reference voltage, and RSET is the resistance value of the second resistor; The second current threshold corresponding to the second reference voltage Wherein, VREF2 is the voltage value of the second reference voltage.
10. A chip, characterized in that, Includes a load circuit and an overcurrent protection circuit as described in any one of claims 1-9; The input terminal of the overcurrent protection circuit is electrically connected to the power supply terminal, and the output terminal of the overcurrent protection circuit is electrically connected to the load circuit.