Multifunctional driving state feedback signal processing circuit

Abstract

The invention relates to an IGBT driving state feedback circuit, in particular to a multifunctional driving state feedback signal processing circuit. Comprising a VCE state monitoring circuit, a fault feedback circuit and a fault feedback circuit with latch protection, and feedback signals can be selected to be independently used according to actual operation requirements; a VCE state monitoring signal monitors the operation state of an IGBT, a fault feedback signal transmission drive board is in fault states such as short circuit and undervoltage, a fault feedback signal with latch protection can achieve latch blocking of faults such as short circuit and power supply, and latch blocking time can be adjusted by modifying resistance and capacitor values of corresponding pins of a timer. And meanwhile, the driving board is controlled to input a pulse signal, the gate pulse of the driving board is blocked, the safe turn-off of the IGBT is effectively controlled, and the safe and reliable operation of the IGBT is protected.

Description

TECHNICAL FIELD

[0001] The present application relates to an IGBT drive state feedback circuit, in particular to a multifunctional drive state feedback signal processing circuit. BACKGROUND

[0002] Power semiconductor devices IGBT are applied more and more widely in many research fields, however, in the actual application process, various fault conditions are often encountered, such as short circuit, overcurrent, undervoltage, etc. The IGBT drive circuit is one of the core technologies of IGBT application technology, and an ideal IGBT drive circuit should have perfect protection function and state feedback transmission function in addition to controlling the normal turn-on and turn-off of IGBT. The IGBT drive state feedback circuit needs to transmit IGBT operating state information, and when a fault occurs, it can quickly and effectively identify the fault state, feed back the fault information, control the safe and reliable turn-off of IGBT, and if necessary, latch and take protective measures within a certain lockout time, block the pulse signal, and ensure the safe and stable operation of the system.

[0003] The traditional drive circuit, especially the medium and high power IGBT drive circuit applied in high voltage conditions, mostly uses the drive protection and state feedback mode of the integrated drive core (PI drive core and other manufacturers' drive core), which is relatively closed in technology and cannot be used alone. The state feedback mode is basically fixed and cannot be adjusted according to the actual operating conditions, and the fault pulse cannot be latched or the fault pulse latching time cannot be adjusted in a wide range.

[0004] And the digital IGBT drive uses programmable logic device chips such as CPLD, FPGA, etc., which can design various drive state feedback modes. Through programming, various state feedback signals and fault latching can be flexibly realized, and the turn-off of IGBT can be controlled to realize the protection of the entire system. However, the drive state feedback circuit designed by using programmable logic device chip scheme is mostly used in digital control circuit, which has complex structure and high cost, and needs to burn and write programs additionally, so it is not suitable for analog control drive circuit. SUMMARY

[0005] In order to solve the problems that the existing drive protection and state feedback mode cannot be used alone, the fault pulse cannot be latched or the fault pulse latching time cannot be adjusted in a wide range, the present application provides a multifunctional drive state feedback signal processing circuit.

[0006] The application is implemented by adopting the following technical scheme: a multifunctional drive state feedback signal processing circuit, characterized by comprising a VCE state monitoring circuit, a fault feedback circuit and a fault feedback circuit with latch protection; the VCE state monitoring circuit generates a VCE state monitoring signal VCE-Sat, the fault feedback circuit generates a fault feedback signal FAILb, and the fault feedback circuit with latch protection generates a fault feedback signal FAILb-lat with latch protection; when the feedback signal SO uploaded to the upper computer is selected as the VCE state monitoring signal VCE-Sat, the VCE state monitoring signal VCE-Sat is uploaded to the upper computer through the resistor R51, and the fault feedback signal FAILb and the fault feedback signal FAILb-lat with latch protection are not uploaded; when the feedback signal SO uploaded to the upper computer is selected as the fault feedback signal FAILb, the fault feedback signal FAILb is uploaded to the upper computer through the resistor R52, and the VCE state monitoring signal VCE-Sat and the fault feedback signal FAILb-lat with latch protection are not uploaded; when the feedback signal SO uploaded to the upper computer is selected as the fault feedback signal FAILb-lat with latch protection, the fault feedback signal FAILb-lat with latch protection is uploaded to the upper computer through the resistor R53, and the VCE state monitoring signal VCE-Sat and the fault feedback signal FAILb are not uploaded.

[0007] The multifunctional drive state feedback signal processing circuit has the resistors R51, R52 and R53 with a resistance of 0.

[0008] The multifunctional drive state feedback signal processing circuit has the VCE state monitoring circuit comprising an operational amplifier chip U21 with a model number of TL081 and a comparator U22 with a model number of LM2903, the 3 pin of the operational amplifier chip U21 is grounded through the resistor R22 and connected with the VCE through the resistor R31 and the resistor R21, the middle of the resistor R31 and the resistor R21 is further connected with the anode of a diode D21, the cathode of the diode D21 is connected with the power voltage of an IGBT drive board, the 2 pin of the operational amplifier chip U21 is grounded through the resistor R23 and connected with the 6 pin through the resistor R24, the 6 pin of the operational amplifier chip U21 is connected with the 3 pin of the comparator U22 through the resistor R25, the 3 pin of the comparator U22 is further connected with the 1 pin through the resistor R27, the 2 pin of the comparator U22 is grounded through the resistor R28 and connected with the power voltage of the IGBT drive board through the resistor R26, the 1 pin of the comparator U22 is connected with the power voltage of the IGBT drive board through the resistor R29, the 1 pin is further connected with one end of a resistor R30, the other end of the resistor R30 outputs the VCE state monitoring signal VCE-Sat, the other end of the resistor R30 is further connected with the cathode of a diode D22, the anode of the diode D22 is grounded, and the VCE is the voltage between the CE of the controlled IGBT.

[0009] The aforementioned multifunctional drive status feedback signal processing circuit includes a power fault monitoring circuit and a short-circuit fault monitoring and feedback circuit.

[0010] The power fault monitoring circuit includes a voltage monitoring chip U61 (model TPS3809), an N-MOS transistor Q61, and an N-MOS transistor Q62. Pin 3 of the voltage monitoring chip U61 is grounded through resistor R62, with capacitor C62 connected in parallel across resistor R62. Pin 3 is also connected to the power supply voltage of the IGBT driver board through resistor R61, with capacitor C61 connected in parallel across resistor R61. Pin 1 of the voltage monitoring chip U61 is grounded. Pin 2 is connected to the gate of the N-MOS transistor Q61 through resistor R63. The source of the N-MOS transistor Q61 is grounded. The drain is connected to the power supply voltage of the IGBT driver board through resistor R64. The drain is also connected to the cathode of the Zener diode D61. The anode of the Zener diode D61 is grounded. The cathode of the Zener diode D61 is connected to the gate of the N-MOS transistor Q62. The source of the N-MOS transistor Q62 is grounded. The drain is connected to the power supply voltage of the IGBT driver board through resistor R65. The drain outputs a power fault signal UV-FAILb.

[0011] The short-circuit fault monitoring and feedback circuit includes Schmitt NAND gates U41 and U42, model HCF4093. Pins 1 and 2 of Schmitt NAND gate U41 are connected to the VCE status monitoring signal VCE-Sat and the pulse input signal PWM, respectively. Pin 3 of Schmitt NAND gate U41 outputs the short-circuit fault signal SC-FAILb. Pins 1 and 2 of Schmitt NAND gate U42 are connected to the power supply fault signal UV-FAILb and the short-circuit fault signal SC-FAILb, respectively. Pin 3 outputs the fault feedback signal FAILb.

[0012] In the aforementioned multifunctional drive status feedback signal processing circuit, the power supply voltage of the IGBT driver board is connected to pin 2 of the Schmitt NAND gate U42 through resistor R41, and diode D41 is also connected in reverse parallel across resistor R41; this part of the circuit serves as a protection to prevent overvoltage of the SC_FAILb signal.

[0013] The aforementioned multi-functional drive status feedback signal processing circuit includes a fault feedback circuit with latch protection. This circuit comprises a TLC555 555 timer U4, an HCF4023 Schmitt NAND gate U1, an HCF4093 Schmitt NAND gate U2, an HCF4093 Schmitt NAND gate U3, and an HCF4093 Schmitt NAND gate U5. Pins 1 and 2 of Schmitt NAND gate U1 are connected to the short-circuit fault signal SC-FAILb and the power fault signal UV-FAILb, respectively. Pin 3 is connected to pins 1 of Schmitt NAND gates U2 and U3. Pin 2 of Schmitt NAND gate U2 is connected to its pin 1. Pin 3 of the circuit is connected to pin 2 of Schmitt NAND gate U3 via resistor R1. Pin 2 of Schmitt NAND gate U3 is also grounded via capacitor C1. Pin 3 of Schmitt NAND gate U3 is connected to pin 2 of 555 timer U4. Pin 1 of 555 timer U4 is grounded. Pin 4 is connected to P15V. Pin 5 is grounded via capacitor C3. Pins 6 and 7 are connected. Pin 6 is connected to P15V via resistor R2 and is also grounded via capacitor C2. Pin 8 is connected to P15V. Pin 3 is connected to the anode of LED1 via resistor R3. The cathode of LED1 is grounded. Pin 3 is also connected to pins 1 and 2 of Schmitt NAND gate U5. Pin 3 of Schmitt NAND gate U5 outputs a fault feedback signal FAILb-lat with latch protection.

[0014] The aforementioned multi-functional drive status feedback signal processing circuit, including a fault feedback circuit with latch protection, further comprises an enable signal circuit. This enable signal circuit includes HCF4093 Schmitt NAND gates U6, U7, U8, U9, and U10. Pins 1 and 2 of Schmitt NAND gate U6 are connected to the pulse input signal PWM and the fault feedback signal FAILb-lat with latch protection, respectively. Pin 3 of Schmitt NAND gate U6 is connected to pins 1 and 2 of Schmitt NAND gate U7. Pin 3 of Schmitt NAND gate U7 is connected to pin 2 of Schmitt NAND gate U8 and pin 1 of Schmitt NAND gate U9. Pin 1 of Schmitt NAND gate U8 is connected to the power fault signal UV_FAILb. Pin 2 of Schmitt NAND gate U9 is connected to the short-circuit fault signal SC_FAILb. Pin 3 of Schmitt NAND gate U8 is connected to pin 1 of Schmitt NAND gate U10. Pin 3 of Schmitt NAND gate U9 is connected to pin 2 of Schmitt NAND gate U10. Pin 3 of Schmitt NAND gate U10 outputs the input pulse enable signal PWM_EN. The input pulse enable signal PWM_EN is combined with the pulse input signal PWM and input to the IGBT driver board. The pulse input signal PWM is only received by the IGBT driver board when the input pulse enable signal PWM_EN is high.

[0015] The fault latching time TB of the aforementioned multi-functional drive status feedback signal processing circuit can be flexibly selected according to the actual situation. This time TB is determined by the values ​​of resistor R2 and capacitor C2.

[0016] This invention provides a drive status feedback signal circuit for analog drive circuits operating under high voltage. The circuit is built using discrete logic devices, allowing for flexible selection of three feedback signals based on actual operational needs: the VCE status monitoring signal VCE-Sat, the fault feedback signal FAILb, or the fault feedback signal FAILb-lat with latching protection. The VCE status monitoring signal VCE-Sat dynamically monitors the voltage across the CE terminals of the IGBT, and combined with the IGBT switching status, it can determine the IGBT's fault condition. The fault feedback signal FAILb monitors IGBT short circuits and power supply faults in real time and sends out fault signals. The fault feedback signal FAILb-lat with latching protection latches faults such as short circuits and power supply faults, while simultaneously controlling the input pulse signal to the drive board and blocking the drive board gate pulse, effectively controlling the safe shutdown of the IGBT and protecting its safe and reliable operation. The drive fault latching time of this technical solution can be adjusted over a wide range according to system needs. The adjustment method is to modify the resistor and capacitor values ​​of the corresponding pins of the 555 timer, providing greater flexibility to adapt to various system requirements. Attached Figure Description

[0017] Figure 1 Diagram showing the implementation methods of feedback signals for different driving states.

[0018] Figure 2 This is a circuit diagram for VCE status monitoring.

[0019] Figure 3 This is a circuit diagram for power supply fault monitoring.

[0020] Figure 4 This is a fault feedback circuit diagram.

[0021] Figure 5 This is a waveform diagram of the fault feedback signal under normal operating conditions.

[0022] Figure 6 This is a circuit diagram for a fault feedback signal with latching protection.

[0023] Figure 7 This is a fault feedback timing diagram with latch protection.

[0024] Figure 8 This is a circuit diagram for the input pulse enable signal.

[0025] Figure 9 This is the timing diagram for the input pulse enable signal. Detailed Implementation

[0026] The drive status feedback signal proposed in this invention can be selected from the following three feedback signals according to the actual operation and upper computer logic protection requirements: VCE status monitoring signal VCE-Sat, fault feedback signal FAILb, or fault feedback signal FAILb-lat with latching protection. The specific implementation method is as follows: Figure 1 As shown.

[0027] Figure 1 In the diagram, R51, R52, and R53 are all 0R resistors. When the status feedback signal is selected as the VCE status monitoring signal VCE-Sat, R51 is soldered, and R52 and R53 are not soldered. The feedback signal SO is VCE-Sat. When the status feedback signal is the fault feedback signal FAILb, R52 is soldered, and R51 and R53 are not soldered. The feedback signal SO is FAILb. When the status feedback signal is the fault feedback signal FAILb-lat with latching protection, R53 is soldered, and R51 and R52 are not soldered. The feedback signal SO is FAILb-lat.

[0028] When the drive status feedback signal is the VCE status monitoring signal VCE-Sat, the feedback signal dynamically monitors the real-time status of VCE. Its circuit diagram is as follows: Figure 2 As shown.

[0029] Figure 2This is a circuit diagram for VCE status monitoring, including operational amplifier chip U21 and comparator U22. Pin 3 of operational amplifier chip U21 is grounded through resistor R22 and connected to VCE via resistor R31 and resistor R21. The midpoint between resistors R31 and R21 is also connected to the anode of diode D21. The cathode of diode D21 is connected to P15V. Pin 2 of operational amplifier chip U21 is grounded through resistor R23 and connected to pin 6 via resistor R24. Pin 6 of operational amplifier chip U21 is connected to pin 3 of comparator U22 via resistor R25. Pins 7 and 4 of operational amplifier chip U21 are connected to P15V and N12V respectively. Pin 3 of comparator U22 is also connected to pin 1 via resistor R27. Pin 2 of comparator U22 is connected to... Resistor R28 is grounded and connected to P15V via resistor R26. Pin 1 of comparator U22 is connected to P15V via resistor R29. Pin 1 is also connected to one end of resistor R30, the other end of which outputs the VCE status monitoring signal VCE-Sat. The other end of resistor R30 is also connected to the cathode of diode D22, and the anode of diode D22 is grounded. P15V is the power supply voltage of the IGBT driver board, N12V is the power supply voltage of operational amplifier chip U21, VCE is the voltage across the CE terminals of the controlled IGBT, and R21 is a voltage divider formed by 58 196K small resistors connected in series. After voltage division, the voltage across the CE terminals of the IGBT is connected to pin 3 of operational amplifier chip U21 (model: TL081), and its voltage divider resistor value Um is:

[0030]

[0031] The output voltage Uo of pin 6 of operational amplifier chip U21 is:

[0032]

[0033] Afterwards, the voltage Uo passes through resistor R25 and is connected to pin 3 of comparator U22 (model: LM2903). The voltage at pin 2 of chip U22 is Up, which is the value of the P15V voltage after passing through voltage divider resistors R26 and R28, calculated as follows:

[0034]

[0035] When the voltage Uo is greater than the voltage Up, that is, when the voltage VCE is greater than 397V, the VCE-Sat output is high at 15V; when the voltage Uo is less than the voltage Up, that is, when the voltage VCE is less than 397V, the VCE-Sat output is low at 0V.

[0036] Based on the switching status of the driver board, under normal operating conditions during high-voltage operation, when the pulse input signal PWM is high, the IGBT is turned on, the voltage across VCE is the IGBT turn-on voltage drop, and the VCE-Sat signal is low. When the PWM signal is low, the IGBT is turned off, the voltage across VCE is the bus voltage, which is greater than the threshold voltage of 397V, and the VCE-Sat signal is high. Under normal operating conditions, the VCE-Sat signal is opposite to the PWM signal. Under fault conditions such as short circuits, when the pulse input signal PWM is high, the IGBT desaturates, and the voltage across VCE rapidly changes from low to high until it reaches the threshold voltage of 397V, at which point the VCE-Sat signal becomes high. By dynamically monitoring the VCE status in conjunction with the IGBT's switching status, the fault condition of the IGBT can be determined.

[0037] When the drive status feedback signal is the fault feedback signal FAILb, the main fault states of the feedback drive board are short circuit and power supply failure. The power supply failure monitoring circuit is as follows: Figure 3 As shown, the device includes a voltage monitoring chip U61, an N-MOS transistor Q61, and an N-MOS transistor Q62. Pin 3 of the voltage monitoring chip U61 is grounded through resistor R62, with capacitor C62 connected in parallel across resistor R62. Pin 3 is also connected to P15V through resistor R61, with capacitor C61 connected in parallel across resistor R61. Pin 1 of the voltage monitoring chip U61 is grounded. Pin 2 is connected to the gate of the N-MOS transistor Q61 through resistor R63. The source of the N-MOS transistor Q61 is grounded, and its drain is connected to P15V through resistor R64. The drain is also connected to the cathode of a Zener diode D61, whose anode is grounded. The cathode of the Zener diode D61 is connected to the gate of the N-MOS transistor Q62, whose source is grounded. The drain is connected to P15V through resistor R65, and the drain outputs a power fault signal UV-FAILb.

[0038] Depend on Figure 3 It can be seen that the value of P15V after passing through the two voltage divider resistors R61 and R62 is...

[0039]

[0040] Through pin 3 of the voltage monitoring chip U61 (model: TPS3809), the reference voltage of the voltage monitoring chip U61 is 5V and the threshold voltage is 4.55V. When 1 / 3P15V is greater than 4.55V, that is, when P15V is greater than 13.65V, the output pin 2 of U61 is high, N-MOS transistor Q61 is turned on, N-MOS transistor Q62 is turned off, and the power fault signal UV-FAILb is high; otherwise, the output pin 2 of chip U61 is low, N-MOS transistor Q61 is turned off, N-MOS transistor Q62 is turned on, and the power fault signal UV-FAILb is low.

[0041] Short circuit fault monitoring and feedback circuit diagram as follows Figure 4 As shown, it includes Schmitt NAND gate U41 and Schmitt NAND gate U42. Pins 1 and 2 of Schmitt NAND gate U41 are connected to the VCE status monitoring signal VCE-Sat and the pulse input signal PWM, respectively. Pin 3 of Schmitt NAND gate U41 outputs the short-circuit fault signal SC-FAILb. Pins 1 and 2 of Schmitt NAND gate U42 are connected to the power fault signal UV-FAILb and the short-circuit fault signal SC-FAILb, respectively. Pin 3 outputs the fault feedback signal FAILb. P15V is also connected to pin 2 of Schmitt NAND gate U42 through resistor R41. A diode D41 is also connected in reverse parallel across resistor R41. Figure 4 In the circuit, VCE-Sat and the pulse input signal PWM are passed through Schmitt NAND gate U41 (model HCF4093) to generate a short-circuit fault signal SC-FAILb. The short-circuit fault signal SC-FAILb and the power supply fault signal UV-FAILb are then passed through Schmitt NAND gate U42 (model HCF4093) to generate a fault feedback signal FAILb. Under normal operating conditions, VCE-Sat and the PWM pulse input signal are opposite, and UV-FAILb is at a high level. The waveform of the fault feedback signal FAILb is as follows: Figure 5 As shown.

[0042] Under normal operating conditions, the short-circuit fault signal SC-FAILb and the power supply fault signal UV-FAILb are both high, while the fault feedback signal FAILb is low. When a short circuit or power supply fault occurs, i.e., when SC-FAILb or UV-FAILb is low, the fault feedback signal FAILb is high. The high and low levels of the fault feedback signal FAILb can effectively transmit the operating status of the IGBT.

[0043] When the drive status feedback signal is a fault feedback signal FAILb-lat with latch protection, the specific implementation circuit is as follows: Figure 6As shown, the system includes a 555 timer U4, Schmitt NAND gates U1, U2, U3, and U5. Pins 1 and 2 of Schmitt NAND gate U1 are connected to the short-circuit fault signal SC-FAILb and the power fault signal UV-FAILb, respectively. Pin 3 is connected to pins 1 of Schmitt NAND gates U2 and U3. Pin 2 of Schmitt NAND gate U2 is connected to pin 1. Pin 3 of Schmitt NAND gate U2 is connected to pin 2 of Schmitt NAND gate U3 via resistor R1. Pin 2 of Schmitt NAND gate U3 is also grounded via capacitor C1. Pin 3 of Schmitt NAND gate U3 is connected to pin 2 of the 555 timer U4. Pin 4 is grounded, pin 5 is grounded through capacitor C3, pins 6 and 7 are connected, pin 6 is connected to P15V through resistor R2 and also grounded through capacitor C2, pin 8 is connected to P15V, pin 3 is connected to the anode of LED1 through resistor R3, the cathode of LED1 is grounded, pin 3 is also connected to pins 1 and 2 of Schmitt NAND gate U5, pin 3 of Schmitt NAND gate U5 outputs a fault feedback signal FAILb-lat with latching protection; SC_FAILb is a short circuit fault signal, normally high level 15V, low level 0V during a short circuit, UV_FAILb is a power supply fault signal, normally high level 15V, low level 0V during a fault. The SC_FAILb short-circuit fault signal and the UV_FAILb power fault signal pass through NAND gate U1 (model HCF4023), and then through Schmitt NAND gates U2 (model HCF4093) and U3 (model HCF4093) respectively, and then serve as the input of the TRIG pin of the 555 timer U4 (model TLC555). The OUT pin of the 555 timer U4 passes through Schmitt NAND gate U5 (model HCF4093) and then serves as the SO feedback signal.

[0044] The trigger level of timer U4 is approximately one-third of the power supply voltage P15V, and the threshold level is approximately two-thirds of the power supply voltage P15V. These levels can be changed using the control voltage terminal CONT. This scheme uses the default trigger and threshold levels: approximately 5V for the trigger level and approximately 10V for the threshold level. When the trigger input TRIG is lower than the trigger level of 5V, the trigger output OUT is high at 15V. When TRIG is higher than the trigger level of 5V, and the threshold input THR is higher than the threshold level of 10V, the trigger resets, and the trigger output OUT is low at 0V. The reset input RESET can override all other inputs and can be used to start a new timing cycle. If RESET is low, the trigger resets, and the output is low; this function is not used in this scheme.

[0045] The timing diagram of the feedback signal generated by this circuit is as follows: Figure 7As shown, by Figure 7 It can be seen that after either the SC_FAILb short-circuit fault signal or the UV_FAILb power supply fault signal is generated, the fault signal will change from a high level of 15V to a low level of 0V. After passing through the feedback signal processing circuit, the FAILb-lat signal changes from a high level of 15V to a low level of 0V and can be latched for a duration of TB. During this period, pin 3 of U4-3 is at a high level, and fault LED1 is lit. The fault latching time TB can be flexibly selected according to the actual situation. In this scheme, this time is determined by the values ​​of R2 and C2. In this scheme, R2 is selected as 392K, C2 is 1uF, and the latching time is:

[0046]

[0047] During fault latching, the pulse input signal needs to be blocked simultaneously. PWM emits a normal waveform, but the driver board's input pulse enable signal is shielded, causing the driver board to stop working. The PWM_EN input pulse enable signal circuit is as follows: Figure 8 As shown, the system includes Schmitt NAND gates U6, U7, U8, U9, and U10. Pins 1 and 2 of Schmitt NAND gate U6 are connected to the pulse input signal PWM and the fault feedback signal FAILb-lat with latch protection, respectively. Pin 3 of Schmitt NAND gate U6 is connected to pins 1 and 2 of Schmitt NAND gate U7. Pin 3 of Schmitt NAND gate U7 is connected to pin 2 of Schmitt NAND gate U8 and pin 1 of Schmitt NAND gate U9. Pin 1 of Schmitt NAND gate U8 is connected to the power fault signal UV_FAILb. Pin 2 of Schmitt NAND gate U9 is connected to the short-circuit fault signal SC_FAILb; pin 3 of Schmitt NAND gate U8 is connected to pin 1 of Schmitt NAND gate U10; pin 3 of Schmitt NAND gate U9 is connected to pin 2 of Schmitt NAND gate U10; pin 3 of Schmitt NAND gate U10 outputs the input pulse enable signal PWM_EN; the FAILb-lat signal and the pulse input signal PWM are processed by Schmitt NAND gate U6 (model HCF4093). After passing through Schmitt NAND gate U7 (model HCF4093), the output of U7 is combined with the UV_FAILb power fault signal through Schmitt NAND gate U8 (model HCF4093) and with the SC_FAILb short circuit fault signal through Schmitt NAND gate U9 (model HCF4093). The outputs of U8 and U9 are combined with Schmitt NAND gate U10 (model HCF4093) and then output as the input pulse enable signal PWM_EN.

[0048] Depend on Figure 9It can be seen that under normal operating conditions, the fault feedback signal FAILb-lat is high, and the input pulse enable signal is consistent with the original pulse input signal. When a short circuit or power failure occurs, the fault feedback signal FAILb-lat is low and remains low for time TB. During this period, the pulse input signal is blocked, and the input pulse enable signal remains low (0V) regardless of whether the pulse input signal is low. When the fault blocking time TB ends, if the fault is eliminated, the fault feedback signal FAILb-lat becomes high, and the input pulse enable signal resumes following the original pulse input signal. If the fault still exists, the fault feedback signal FAILb-lat remains low, continuing to block for time TB, and the input pulse enable signal remains low (0V).

Claims

1. A multifunctional drive state feedback signal processing circuit, characterized in that: This includes a VCE status monitoring circuit, a fault feedback circuit, and a fault feedback circuit with latching protection. The VCE status monitoring circuit generates a VCE status monitoring signal VCE-Sat, the fault feedback circuit generates a fault feedback signal FAILb, and the fault feedback circuit with latching protection generates a fault feedback signal FAILb-lat with latching protection. When the feedback signal SO uploaded to the host computer is selected as the VCE status monitoring signal VCE-Sat, the VCE status monitoring signal VCE-Sat is uploaded to the host computer through resistor R51. The fault feedback signal FAILb and the fault feedback signal FAILb-lat with latching protection are then connected. -lat is not uploaded; when the feedback signal SO uploaded to the host computer is selected as the fault feedback signal FAILb, the fault feedback signal FAILb is uploaded to the host computer through resistor R52, and the VCE status monitoring signal VCE-Sat and the fault feedback signal FAILb-lat with latch protection are not uploaded; when the feedback signal SO uploaded to the host computer is selected as the fault feedback signal FAILb-lat with latch protection, the fault feedback signal FAILb-lat with latch protection is uploaded to the host computer through resistor R53, and the VCE status monitoring signal VCE-Sat and the fault feedback signal FAILb are not uploaded.

2. The multifunctional drive state feedback signal processing circuit according to claim 1, characterized in that: The resistance values ​​of resistors R51, R52, and R53 are all 0.

3. The multifunctional drive state feedback signal processing circuit according to claim 2, characterized in that: The VCE status monitoring circuit includes an operational amplifier chip U21 (model TL081) and a comparator U22 (model LM2903). Pin 3 of the operational amplifier chip U21 is grounded through resistor R22 and connected to VCE via resistor R31 and R21. The midpoint between resistors R31 and R21 is also connected to the anode of diode D21. The cathode of diode D21 is connected to the power supply voltage of the IGBT driver board. Pin 2 of the operational amplifier chip U21 is grounded through resistor R23 and connected to pin 6 via resistor R24. Pin 6 of the operational amplifier chip U21 is connected to the comparator U22 via resistor R25. Pin 3 of comparator U22 is connected to pin 1 via resistor R27. Pin 2 of comparator U22 is grounded via resistor R28 and connected to the power supply voltage of the IGBT driver board via resistor R26. Pin 1 of comparator U22 is connected to the power supply voltage of the IGBT driver board via resistor R29. Pin 1 is also connected to one end of resistor R30. The other end of resistor R30 outputs the VCE status monitoring signal VCE-Sat. The other end of resistor R30 is also connected to the cathode of diode D22. The anode of diode D22 is grounded. VCE is the voltage across the CE terminals of the controlled IGBT.

4. The multifunctional drive state feedback signal processing circuit according to claim 3, characterized in that: The fault feedback circuit includes a power fault monitoring circuit and a short-circuit fault monitoring and feedback circuit; The power fault monitoring circuit includes a voltage monitoring chip U61 (model TPS3809), an N-MOS transistor Q61, and an N-MOS transistor Q62. Pin 3 of the voltage monitoring chip U61 is grounded through resistor R62, with capacitor C62 connected in parallel across resistor R62. Pin 3 is also connected to the power supply voltage of the IGBT driver board through resistor R61, with capacitor C61 connected in parallel across resistor R61. Pin 1 of the voltage monitoring chip U61 is grounded. Pin 2 is connected to the gate of the N-MOS transistor Q61 through resistor R63. The source of the N-MOS transistor Q61 is grounded. The drain is connected to the power supply voltage of the IGBT driver board through resistor R64. The drain is also connected to the cathode of the Zener diode D61. The anode of the Zener diode D61 is grounded. The cathode of the Zener diode D61 is connected to the gate of the N-MOS transistor Q62. The source of the N-MOS transistor Q62 is grounded. The drain is connected to the power supply voltage of the IGBT driver board through resistor R65. The drain outputs a power fault signal UV-FAILb. The short-circuit fault monitoring and feedback circuit includes Schmitt NAND gates U41 and U42, model HCF4093. Pins 1 and 2 of Schmitt NAND gate U41 are connected to the VCE status monitoring signal VCE-Sat and the pulse input signal PWM, respectively. Pin 3 of Schmitt NAND gate U41 outputs the short-circuit fault signal SC-FAILb. Pins 1 and 2 of Schmitt NAND gate U42 are connected to the power supply fault signal UV-FAILb and the short-circuit fault signal SC-FAILb, respectively. Pin 3 outputs the fault feedback signal FAILb.

5. The multifunctional drive state feedback signal processing circuit according to claim 4, characterized in that: The power supply voltage of the IGBT driver board is connected to pin 2 of the Schmitt NAND gate U42 through resistor R41. A diode D41 is also connected in reverse parallel across resistor R41.

6. The multifunctional drive state feedback signal processing circuit according to claim 4, characterized in that: The fault feedback circuit with latch protection includes a signal generation circuit, which comprises a TLC555 555 timer U4, an HCF4023 Schmitt NAND gate U1, an HCF4093 Schmitt NAND gate U2, an HCF4093 Schmitt NAND gate U3, and an HCF4093 Schmitt NAND gate U5. Pins 1 and 2 of Schmitt NAND gate U1 are connected to the short-circuit fault signal SC-FAILb and the power fault signal UV-FAILb, respectively. Pin 3 is connected to pins 1 of Schmitt NAND gates U2 and U3, respectively. Pin 2 of Schmitt NAND gate U2 is connected to its pin 1. Pin 3 of Schmitt NAND gate U2 is connected to... Pin 2 of Schmitt NAND gate U3 is connected, and pin 2 of Schmitt NAND gate U3 is also grounded through capacitor C1. Pin 3 of Schmitt NAND gate U3 is connected to pin 2 of 555 timer U4. Pin 1 of 555 timer U4 is grounded, pin 4 is connected to P15V, pin 5 is grounded through capacitor C3, pins 6 and 7 are connected, pin 6 is connected to P15V through resistor R2, and is also grounded through capacitor C2. Pin 8 is connected to P15V, pin 3 is connected to the anode of LED1 through resistor R3, the cathode of LED1 is grounded, pin 3 is also connected to pins 1 and 2 of Schmitt NAND gate U5, and pin 3 of Schmitt NAND gate U5 outputs a fault feedback signal FAILb-lat with latch protection.

7. The multifunctional drive state feedback signal processing circuit according to claim 6, characterized in that: The fault feedback circuit with latching protection also includes an enable signal circuit, which comprises HCF4093 Schmitt NAND gates U6, U7, U8, U9, and U10. Pins 1 and 2 of Schmitt NAND gate U6 are connected to the pulse input signal PWM and the fault feedback signal FAILb-lat with latching protection, respectively. Pin 3 of Schmitt NAND gate U6 is connected to pins 1 and 2 of Schmitt NAND gate U7. Pin 3 of Schmitt NAND gate U7 is connected to pin 2 of Schmitt NAND gate U8 and pin 1 of Schmitt NAND gate U9. Pin 1 of Schmitt NAND gate U8 is connected to the power fault signal UV_FAILb. Pin 2 of Schmitt NAND gate U9 is connected to the short-circuit fault signal SC_FAILb; pin 3 of Schmitt NAND gate U8 is connected to pin 1 of Schmitt NAND gate U10; pin 3 of Schmitt NAND gate U9 is connected to pin 2 of Schmitt NAND gate U10; and pin 3 of Schmitt NAND gate U10 outputs the input pulse enable signal PWM_EN.

8. A multifunctional drive state feedback signal processing circuit according to claim 6 or 7, characterized in that: The fault latching time TB can be flexibly selected according to the actual situation. This time TB is determined by the values ​​of resistor R2 and capacitor C2.

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