Method, system and storage medium for detecting robustness of chip power tolerance

Abstract

The application belongs to the technical field of communication, and particularly relates to a chip power tolerance robustness detection method, system and storage medium. The application calibrates the insertion loss of a first power measurement unit and the insertion loss of a second power measurement unit; calculates a first gain value of a to-be-detected chip according to a first measurement value and a second measurement value; stops transmitting an input signal to a power amplifier, and records a second static current of a current second power supply; compares the first static current with the second static current; calculates a second gain value of the to-be-detected chip according to a third measurement value and a fourth measurement value; compares the first gain value with the second gain value, and judges whether a first comparison value or a second comparison value exceeds a preset comparison value; if yes, the third measurement value is taken as a tolerance limit value of the to-be-detected chip. Compared with the prior art, the application can accurately detect and evaluate the tolerance of the to-be-detected chip, thereby preventing chip damage caused by receiving a high-power signal.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of communication technology, and particularly relates to a chip power tolerance robustness detection method, system and storage medium. BACKGROUND

[0002] With the continuous development of mobile communication technology, 5G communication has realized large-scale commercial popularization, and its deep application in the fields of Internet of Things, industrial Internet, ultra-high-definition video transmission, remote medical treatment and the like has put forward requirements far beyond the past for the communication quality of the communication system, not only the transmission demand of higher bandwidth and lower time delay needs to be met, but also the concurrent connection of a large number of devices needs to be supported.

[0003] In order to adapt to these complex application scenarios, the transmission power of the communication system is continuously improved to enhance the signal coverage range and penetration ability, and to ensure the stability of data transmission. As the core operation and signal processing unit of the communication device, the system working chip directly bears the reception and processing tasks of high-power signals, and its power tolerance robustness is severely tested. There is a lack of methods for testing the power tolerance robustness of the working chip in the prior art. If the power tolerance robustness of the chip is insufficient, when receiving high-power signals, problems such as overheating of the internal circuit of the chip, breakdown of components or permanent performance attenuation are likely to occur, which not only leads to communication interruption of a single device, but also may cause large-scale communication network failure, resulting in serious economic losses.

[0004] Therefore, there is an urgent need for a new chip power tolerance robustness detection method, system and storage medium to solve the above technical problems. SUMMARY

[0005] The present application provides a chip power tolerance robustness detection method, system and storage medium, which aims to accurately evaluate the power tolerance robustness of the working chip of the communication system.

[0006] In a first aspect, the present application provides a detection method based on a power tolerance detection device, the power tolerance detection device comprising a first power supply, a second power supply, a first power measurement unit, and a signal transmitting unit, a power amplifier, an isolator, a coupler, an attenuator and a second power measurement unit connected in sequence; the first power supply is used to power the power amplifier, the second power supply is used to provide voltage and current for the chip to be tested, and the first power measurement unit is used to detect the input power of the chip to be tested;

[0007] The detection method comprises the following steps:

[0008] S1, calibrate the insertion loss of the first power measurement unit and the insertion loss of the second power measurement unit;

[0009] S2, turn on the first power supply and the second power supply, and record a first static current of the second power supply at present;

[0010] S3, turn on the signal transmitting unit, transmit an input signal to the power amplifier through the signal transmitting unit, record a first measurement value of the first power measurement unit at present, keep the first measurement value of the first power measurement unit less than a first preset value, and record a second measurement value of the second power measurement unit at present; calculate a first gain value of the to-be-tested chip according to the first measurement value and the second measurement value;

[0011] S4, increase a power of a transmission signal of the signal transmitting unit by a second preset value, and record a third measurement value of the first power measurement unit at present;

[0012] S5, turn off the signal transmitting unit, stop transmitting the input signal to the power amplifier, and record a second static current of the second power supply at present; compare the first static current with the second static current to obtain a first comparison value;

[0013] S6, turn on the signal transmitting unit, transmit the input signal to the power amplifier through the signal transmitting unit, keep the first measurement value of the first power measurement unit less than the first preset value, and record a fourth measurement value of the second power measurement unit at present; calculate a second gain value of the to-be-tested chip according to the third measurement value and the fourth measurement value; compare the first gain value with the second gain value to obtain a second comparison value;

[0014] S7, judge whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, judge that the to-be-tested chip is damaged, and take the third measurement value as a tolerance limit value of the to-be-tested chip; if not, return to repeat steps S4-S7 until the tolerance limit value of the to-be-tested chip is obtained.

[0015] Preferably, the signal transmitting unit is used for transmitting the input signal to a first input end of the power amplifier;

[0016] A second input end of the power amplifier is connected with the first power supply, an output end of the power amplifier is connected with an input end of the isolator, and the isolator is used for blocking a reflected signal emitted after load mismatch;

[0017] An output end of the isolator is connected with an input end of the coupler, a first output end of the coupler is connected with an input end of the first power measurement unit, and a second output end of the coupler is connected with a first input end of the to-be-tested chip; the coupler is used for coupling the input signal of the to-be-tested chip.

[0018] The second input end of the to-be-tested chip is connected with the second power supply, and the output end of the to-be-tested chip is connected with the input end of the attenuator, so as to detect the static current of the to-be-tested chip.

[0019] The output end of the attenuator is connected with the input end of the second power measurement unit, and the attenuator is used to reduce the output power of the to-be-tested chip.

[0020] The second power measurement unit is used to detect the output power of the to-be-tested chip.

[0021] The signal transmitting unit is used to transmit an input signal to the first input end of the power amplifier.

[0022] The second input end of the power amplifier is connected with the first power supply, and the output end of the power amplifier is connected with the input end of the isolator, so as to block the reflected signal emitted after load mismatch.

[0023] The output end of the isolator is connected with the input end of the coupler, the first output end of the coupler is connected with the input end of the first power measurement unit, and the second output end of the coupler is connected with the first input end of the to-be-tested chip, so as to couple the input signal of the to-be-tested chip.

[0024] The second input end of the to-be-tested chip is connected with the second power supply, and the output end of the to-be-tested chip is connected with the input end of the attenuator, so as to detect the static current of the to-be-tested chip.

[0025] The output end of the attenuator is connected with the input end of the second power measurement unit, and the attenuator is used to reduce the output power of the to-be-tested chip.

[0026] The second power measurement unit is used to detect the output power of the to-be-tested chip.

[0027] Preferably, the first preset value is -20 dBm.

[0028] Preferably, the preset comparison value is 10%.

[0029] Preferably, the attenuator is a 20 dB attenuator.

[0030] In a second aspect, the present application provides a chip power tolerance robustness detection system, which comprises a power tolerance detection device, a calibration module, a power-on module, a gain calculation module, a power increase module, a first comparison module, a second comparison module and a judgment module, wherein the power tolerance detection device comprises a signal transmitting unit, a power amplifier, an isolator, a coupler, a first power measurement unit, an attenuator and a second power measurement unit.

[0031] The output end of the signal transmitting unit is connected to the first input end of the power amplifier, and the signal transmitting unit is configured to transmit an input signal to the first input end of the power amplifier.

[0032] The second input end of the power amplifier is connected to a first power supply, and the output end of the power amplifier is connected to the input end of the isolator, and the isolator is configured to block reflected signals emitted after load mismatch.

[0033] The output end of the isolator is connected to the input end of the coupler, the first output end of the coupler is connected to the input end of the first power measurement unit, and the second output end of the coupler is connected to the first input end of a chip to be tested; the coupler is configured to couple the input signal of the chip to be tested.

[0034] The first power measurement unit is configured to detect the input power of the chip to be tested.

[0035] The second input end of the chip to be tested is connected to a second power supply, and the output end of the chip to be tested is connected to the input end of the attenuator; the second power supply is configured to provide voltage and current for the chip to be tested and detect the quiescent current of the chip to be tested.

[0036] The output end of the attenuator is connected to the input end of the second power measurement unit; the attenuator is configured to reduce the output power of the chip to be tested.

[0037] The second power measurement unit is configured to detect the output power of the chip to be tested.

[0038] The calibration module is configured to calibrate the first power measurement unit and the second power measurement unit.

[0039] The power-on module is configured to turn on the first power supply and the second power supply and record the first quiescent current of the second power supply.

[0040] The gain calculating module is configured to turn on the signal transmitting unit, transmit an input signal to the power amplifier through the signal transmitting unit, record a current measurement value of the first power measuring unit as a first measurement value, keep the first measurement value of the first power measuring unit less than a first preset value, and record a current measurement value of the second power measuring unit as a second measurement value; and calculate a first gain value of the to-be-tested chip according to the first measurement value and the second measurement value.

[0041] The power increasing module is configured to increase the power of the signal transmitted by the signal transmitting unit by a second preset value, and record a current measurement value of the first power measuring unit as a third measurement value.

[0042] The first comparing module is configured to turn off the signal transmitting unit, stop transmitting the input signal to the power amplifier, and record a second static current of the second power supply; compare the first static current with the second static current to obtain a first comparison value.

[0043] The second comparing module is configured to turn on the signal transmitting unit, transmit an input signal to the power amplifier through the signal transmitting unit, keep the first measurement value of the first power measuring unit less than a first preset value, and record a current measurement value of the second power measuring unit as a fourth measurement value; calculate a second gain value of the to-be-tested chip according to the third measurement value and the fourth measurement value; and compare the first gain value with the second gain value to obtain a second comparison value.

[0044] The judging module is configured to judge whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, judge that the to-be-tested chip is damaged, and take the third measurement value as a tolerance limit value of the to-be-tested chip; and if no, return to the power increasing module.

[0045] Preferably, the first preset value is -20 dBm.

[0046] Preferably, the preset comparison value is 10%.

[0047] Preferably, the attenuator is a 20 dB attenuator.

[0048] In a third aspect, the present application further provides a computer device, comprising a memory, a processor, and a chip power tolerance robustness detection program stored in the memory and executable on the processor, wherein the processor implements the steps in the chip power tolerance robustness detection method according to any one of the above embodiments when executing the chip power tolerance robustness detection program.

[0049] In a fourth aspect, the present application further provides a computer readable storage medium, wherein a chip power tolerance robustness detection program is stored on the computer readable storage medium, and the chip power tolerance robustness detection program, when executed by a processor, implements the steps of the chip power tolerance robustness detection method according to any one of the above embodiments.

[0050] Compared with the prior art, the present application calibrates the insertion loss of the first power measurement unit and the insertion loss of the second power measurement unit; turns on the first power supply and the second power supply, and records the first static current of the current second power supply; turns on the signal transmitting unit, transmits the input signal to the power amplifier through the signal transmitting unit, records the measurement value of the current first power measurement unit as the first measurement value, keeps the first measurement value of the first power measurement unit less than the first preset value, and records the measurement value of the current second power measurement unit as the second measurement value; calculates the first gain value of the to-be-tested chip according to the first measurement value and the second measurement value; increases the power of the transmission signal of the signal transmitting unit by the second preset value, records the measurement value of the current first power measurement unit as the third measurement value; turns off the signal transmitting unit, stops transmitting the input signal to the power amplifier, and records the second static current of the current second power supply; compares the first static current with the second static current to obtain the first comparison value; turns on the signal transmitting unit, transmits the input signal to the power amplifier through the signal transmitting unit, keeps the first measurement value of the first power measurement unit less than the first preset value, and records the measurement value of the current second power measurement unit as the fourth measurement value; calculates the second gain value of the to-be-tested chip according to the third measurement value and the fourth measurement value; compares the first gain value with the second gain value to obtain the second comparison value; judges whether the first comparison value or the second comparison value exceeds the preset comparison value: if yes, judges that the to-be-tested chip is damaged, and takes the third measurement value as the tolerance limit value of the to-be-tested chip. In this way, the present application can accurately detect and evaluate the tolerance of the to-be-tested chip, and obtain the tolerance limit value of the to-be-tested chip, thereby preventing the chip from being damaged due to receiving a high-power signal. BRIEF DESCRIPTION OF DRAWINGS

[0051] The present application will be described in detail below with reference to the drawings. The above or other aspects of the present application will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0052] Figure 1 is a structural block diagram of the power tolerance detection device provided by the embodiment of the present application;

[0053] Figure 2 is a flow block diagram of the chip power tolerance robustness detection method provided by the embodiment of the present application;

[0054] Figure 3is a calibration environment structure block diagram of the first power measurement unit provided by the embodiment of the present application;

[0055] Figure 4 is a calibration environment structure block diagram of the second power measurement unit provided by the embodiment of the present application;

[0056] Figure 5 is a structure schematic diagram of the chip power tolerance robustness detection system provided by the embodiment of the present application;

[0057] Figure 6 is a structure schematic diagram of the computer device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0059] Embodiment one

[0060] Please refer to Figure 1 The present application provides a chip power tolerance robustness detection method, which is based on a power tolerance detection device 100, and the power tolerance detection device 100 comprises a signal transmitting unit 1, a power amplifier 2, an isolator 3, a coupler 4, a first power measurement unit 6, an attenuator 7 and a second power measurement unit 8.

[0061] The output end of the signal transmitting unit 1 is connected to the first input end of the power amplifier 2, and the signal transmitting unit 1 is used to transmit an input signal to the first input end of the power amplifier 2.

[0062] The second input end of the power amplifier 2 is connected to a first power supply 9, and the output end of the power amplifier 2 is connected to the input end of the isolator 3, and the isolator 3 is used to block the reflected signal emitted after load mismatch.

[0063] The output end of the isolator 3 is connected to the input end of the coupler 4, the first output end of the coupler 4 is connected to the input end of the first power measurement unit 6, and the second output end of the coupler 4 is connected to the first input end of the chip under test 5; the coupler 4 is used to couple the input signal of the chip under test 5; in the embodiment of the present application, the coupler 4 is an external cavity coupler.

[0064] The first power measurement unit 6 is used to detect the input power of the chip under test 5.

[0065] The second input end of the to-be-tested chip 5 is connected with a second power supply 10, the output end of the to-be-tested chip 5 is connected with the input end of the attenuator 7, and the second power supply 10 is used for providing voltage and current for the to-be-tested chip 5 and detecting the static current of the to-be-tested chip 5.

[0066] The output end of the attenuator 7 is connected with the input end of the second power measurement unit 8; and the attenuator 7 is used for reducing the output power of the to-be-tested chip 5.

[0067] The second power measurement unit 8 is used for detecting the output power of the to-be-tested chip 5.

[0068] The detection method comprises the following steps:

[0069] S1, calibrating the insertion loss of the first power measurement unit 6 and the insertion loss of the second power measurement unit 8.

[0070] In the embodiment of the present application, please refer to Figure 3 , Figure 3 is a calibration environment structure block diagram of the first power measurement unit provided by the embodiment of the present application; under the calibration environment as shown in Figure 3 , the transmission signal output of the signal transmission unit is 0dBm signal, the power P1 of the first power measurement unit and the power P2 of the second power measurement unit are recorded at this time, the insertion loss compensation value of the first power measurement unit at this time is P1. The through insertion loss of the coupler is P1+coupling coefficient-P2, the through insertion loss is recorded as IL1, P1-IL1 is compensated to the first power measurement unit, and the power value displayed by the first power measurement unit at this time is the input end power size of the to-be-tested chip.

[0071] Please refer to Figure 4 , Figure 4 is a calibration environment structure block diagram of the second power measurement unit provided by the embodiment of the present application; under the calibration environment as shown in Figure 4 , the transmission signal output of the signal transmission unit is 0dBm, the power value of the second power measurement unit is recorded as P, the back-end insertion loss of the to-be-tested chip at this time is P, compensation is carried out in the second power measurement unit, and the power value displayed by the second power measurement unit after compensation is the output power value of the to-be-tested chip.

[0072] S2, the first power supply 9 and the second power supply 10 are turned on, and the first static current of the second power supply 10 at present is recorded;

[0073] S3, turn on the signal transmitting unit 1, transmit an input signal to the power amplifier 2 through the signal transmitting unit 1, record a current measurement value of the first power measuring unit 6 as a first measurement value, keep the first measurement value of the first power measuring unit 6 less than a first preset value, and record a current measurement value of the second power measuring unit 8 as a second measurement value; calculate a first gain value of the chip 5 to be tested according to the first measurement value and the second measurement value.

[0074] In the embodiment of the present application, the first preset value is -20dBm, the first measurement value is defined as P1, the second measurement value is defined as P2, and the first gain value satisfies Gain1=P2-P1.

[0075] S4, increase the power of the signal transmitted by the signal transmitting unit 1 by a second preset value, and record a current measurement value of the first power measuring unit 6 as a third measurement value.

[0076] S5, turn off the signal transmitting unit 1, stop transmitting the input signal to the power amplifier 2, and record a second static current of the second power supply 10; compare the first static current with the second static current to obtain a first comparison value.

[0077] S6, turn on the signal transmitting unit 1, transmit an input signal to the power amplifier 2 through the signal transmitting unit 1, keep the first measurement value of the first power measuring unit 6 less than a first preset value, and record a current measurement value of the second power measuring unit 8 as a fourth measurement value; calculate a second gain value of the chip 5 to be tested according to the third measurement value and the fourth measurement value; compare the first gain value with the second gain value to obtain a second comparison value.

[0078] In the embodiment of the present application, the third measurement value is defined as P3, the fourth measurement value is defined as P4, and the second gain value satisfies Gain2=P4-P3.

[0079] S7, judge whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, judge that the chip 5 to be tested is damaged, and take the third measurement value as a tolerance limit value of the chip 5 to be tested; if not, return to repeat steps S4-S7 until the tolerance limit value of the chip to be tested is obtained.

[0080] In the embodiment of the present application, the first comparison value is the difference between the first static current and the second static current, the second comparison value is the difference between the first gain value and the second gain value, and the preset comparison value is 10%.

[0081] Compared with the prior art, the application calibrates the insertion loss of the first power measuring unit 6 and the insertion loss of the second power measuring unit 8, turns on the first power supply 9 and the second power supply 10, and records the first static current of the second power supply 10; turns on the signal transmitting unit 1, transmits the input signal to the power amplifier 2 through the signal transmitting unit 1, records the measurement value of the first power measuring unit 6 as the first measurement value, keeps the first measurement value of the first power measuring unit 6 less than the first preset value, and records the measurement value of the second power measuring unit 8 as the second measurement value; calculates the first gain value of the to-be-tested chip 5 according to the first measurement value and the second measurement value; increases the power of the transmission signal of the signal transmitting unit 1 by the second preset value, records the measurement value of the first power measuring unit 6 as the third measurement value; turns off the signal transmitting unit 1, stops transmitting the input signal to the power amplifier 2, and records the second static current of the second power supply 10; compares the first static current with the second static current to obtain the first comparison value; turns on the signal transmitting unit 1, transmits the input signal to the power amplifier 2 through the signal transmitting unit 1, keeps the first measurement value of the first power measuring unit 6 less than the first preset value, and records the measurement value of the second power measuring unit 8 as the fourth measurement value; calculates the second gain value of the to-be-tested chip 5 according to the third measurement value and the fourth measurement value; compares the first gain value with the second gain value to obtain the second comparison value; judges whether the first comparison value or the second comparison value exceeds the preset comparison value: if yes, judges that the to-be-tested chip 5 is damaged, and takes the third measurement value as the endurance limit value of the to-be-tested chip 5. In this way, the application can accurately detect and evaluate the endurance of the to-be-tested chip 5, and obtain the endurance limit value of the to-be-tested chip 5, thereby preventing the chip from being damaged due to receiving a high-power signal.

[0082] Embodiment two

[0083] The application also provides a chip power endurance robustness detection system, please refer to Figure 5 , Figure 5 is a structural schematic diagram of the chip power endurance robustness detection system 200 provided by the application, which comprises:

[0084] The detection system comprises a power endurance detection device 100, a calibration module 201, a power-on module 202, a gain calculation module 203, a power increase module 204, a first comparison module 205, a second comparison module 206 and a judgment module 207, and the power endurance detection device 100 comprises a signal transmitting unit 1, a power amplifier 2, an isolator 3, a coupler 4, a first power measuring unit 6, an attenuator 7 and a second power measuring unit 8.

[0085] The output end of the signal transmitting unit 1 is connected to the first input end of the power amplifier 2, and the signal transmitting unit 1 is used for transmitting an input signal to the first input end of the power amplifier 2.

[0086] The second input end of the power amplifier 2 is connected to the first power supply 9, and the output end of the power amplifier 2 is connected to the input end of the isolator 3, and the isolator 3 is used for blocking the reflected signal emitted after the load mismatch.

[0087] The output end of the isolator 3 is connected to the input end of the coupler 4, the first output end of the coupler 4 is connected to the input end of the first power measuring unit 6, and the second output end of the coupler 4 is connected to the first input end of the chip under test 5; the coupler 4 is used for coupling the input signal of the chip under test 5.

[0088] The first power measuring unit 6 is used for detecting the input power of the chip under test 5.

[0089] The second input end of the chip under test 5 is connected to the second power supply 10, and the output end of the chip under test 5 is connected to the input end of the attenuator 7; the second power supply 10 is used for providing voltage and current for the chip under test 5 and detecting the quiescent current of the chip under test 5.

[0090] The output end of the attenuator 7 is connected to the input end of the second power measuring unit 8; the attenuator 7 is used for reducing the output power of the chip under test 5.

[0091] The second power measuring unit 8 is used for detecting the output power of the chip under test 5.

[0092] The calibration module 201 is used for calibrating the first power measuring unit 6 and the second power measuring unit 8.

[0093] The power-on module 202 is used for turning on the first power supply 9 and the second power supply 10, and recording the first quiescent current of the second power supply 10 at present;

[0094] The gain calculation module 203 is used for turning on the signal transmitting unit 1, transmitting an input signal to the power amplifier 2 through the signal transmitting unit 1, recording the measurement value of the first power measuring unit 6 as a first measurement value, keeping the first measurement value of the first power measuring unit 6 less than a first preset value, recording the measurement value of the second power measuring unit 8 as a second measurement value, and calculating a first gain value of the chip under test 5 according to the first measurement value and the second measurement value.

[0095] The power increasing module 204 is used for increasing the power of the transmitting signal of the signal transmitting unit 1 by a second preset value, recording the current measuring value of the first power measuring unit 6 as a third measuring value;

[0096] The first comparison module 205 is used for closing the signal transmitting unit 1, stopping transmitting the input signal to the power amplifier 2, and recording the second static current of the second power supply 10; comparing the first static current with the second static current to obtain a first comparison value;

[0097] The second comparison module 206 is used for opening the signal transmitting unit 1, transmitting the input signal to the power amplifier 2 through the signal transmitting unit 1, keeping the first measuring value of the first power measuring unit 6 less than a first preset value, recording the measuring value of the second power measuring unit 8 as a fourth measuring value; calculating the second gain value of the chip 5 to be tested according to the third measuring value and the fourth measuring value; comparing the first gain value with the second gain value to obtain a second comparison value;

[0098] The judging module 207 is used for judging whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, judging that the chip 5 to be tested is damaged, and taking the third measuring value as the endurance limit value of the chip 5 to be tested; if no, returning to the power increasing module.

[0099] In the embodiment of the present application, the first preset value is -20dBm.

[0100] In the embodiment of the present application, the preset comparison value is 10%.

[0101] In the embodiment of the present application, the attenuator 7 is a 20dB attenuator.

[0102] The chip power endurance robustness detection system 200 can realize the steps in the chip power endurance robustness detection method in the above-mentioned embodiment, and can realize the same technical effects, and the description in the above-mentioned embodiment is referred to, and will not be repeated here.

[0103] Embodiment three

[0104] The embodiment of the present application also provides a computer device, which refers to Figure 6 , Figure 6 Fig. 1 is a structural schematic diagram of the computer device provided by the embodiment of the present application, and the computer device 300 comprises a memory 302, a processor 301, and a chip power endurance robustness detection program stored in the memory 302 and capable of running on the processor 301.

[0105] The processor 301 invokes the chip power tolerance robustness detection program stored in the memory 302 to perform the steps in the chip power tolerance robustness detection method provided by the embodiment of the application. Please refer to Figure 1 , and specifically includes the following steps:

[0106] The detection method includes the following steps:

[0107] S1, calibrate the insertion loss of the first power measurement unit 6 and the insertion loss of the second power measurement unit 8.

[0108] In the embodiment of the application, please refer to Figure 3 , Figure 3 is a calibration environment structural diagram of the first power measurement unit provided by the embodiment of the application; in the calibration environment as shown in Figure 3 , the transmission signal output of the signal transmission unit is 0dBm signal, the power P1 of the first power measurement unit and the power P2 of the second power measurement unit at this time are recorded, and the insertion loss compensation value of the first power measurement unit at this time is P1. The through insertion loss of the coupler is P1+coupling coefficient-P2, and the through insertion loss is recorded as IL1. P1-IL1 is compensated to the first power measurement unit, and the power value displayed by the first power measurement unit at this time is the input end power size of the chip to be measured.

[0109] Please refer to Figure 4 , Figure 4 is a calibration environment structural diagram of the second power measurement unit provided by the embodiment of the application; in the calibration environment as shown in Figure 4 , the transmission signal output of the signal transmission unit is 0dBm, and the power value of the second power measurement unit is recorded as P. At this time, the back-end insertion loss of the chip to be measured is P. After compensation in the second power measurement unit, the power value displayed by the second power measurement unit is the output power value of the chip to be measured.

[0110] S2, turn on the first power supply 9 and the second power supply 10, and record the first static current of the second power supply 10 at present;

[0111] S3, turn on the signal transmission unit 1, transmit an input signal to the power amplifier 2 through the signal transmission unit 1, record the measurement value of the first power measurement unit 6 at present as a first measurement value, and keep the first measurement value of the first power measurement unit 6 less than a first preset value, record the measurement value of the second power measurement unit 8 at present as a second measurement value; calculate the first gain value of the chip to be measured 5 according to the first measurement value and the second measurement value.

[0112] In the embodiment of the present application, the first preset value is -20dBm, the first measurement value is defined as P1, the second measurement value is defined as P2, and the first gain value satisfies Gain1=P2-P1.

[0113] S4, increasing the power of the transmission signal of the signal transmission unit 1 by a second preset value, and recording the measurement value of the first power measurement unit 6 as a third measurement value;

[0114] S5, closing the signal transmission unit 1, stopping transmitting the input signal to the power amplifier 2, and recording the second static current of the second power supply 10 as a second static current; comparing the first static current with the second static current to obtain a first comparison value.

[0115] S6, opening the signal transmission unit 1, transmitting the input signal to the power amplifier 2 through the signal transmission unit 1, keeping the first measurement value of the first power measurement unit 6 less than the first preset value, recording the measurement value of the second power measurement unit 8 as a fourth measurement value, calculating the second gain value of the chip 5 to be tested according to the third measurement value and the fourth measurement value, and comparing the first gain value with the second gain value to obtain a second comparison value.

[0116] In the embodiment of the present application, the third measurement value is defined as P3, the fourth measurement value is defined as P4, and the second gain value satisfies Gain2=P4-P3.

[0117] S7, judging whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, judging that the chip 5 to be tested is damaged, and taking the third measurement value as the endurance limit value of the chip 5 to be tested; if no, returning to repeat steps S4-S7 until the endurance limit value of the chip to be tested is obtained.

[0118] In the embodiment of the present application, the first comparison value is the difference between the first static current and the second static current, the second comparison value is the difference between the first gain value and the second gain value, and the preset comparison value is 10%.

[0119] The computer device 300 provided by the embodiment of the present application can realize the steps in the chip power endurance robustness detection method in the above-described embodiment, and can realize the same technical effects, and the description in the above-described embodiment is referred to herein.

[0120] Embodiment Four

[0121] The embodiment of the present application further provides a computer readable storage medium, which stores a chip power tolerance robustness detection program. The chip power tolerance robustness detection program is executed by a processor to implement each process and step in the chip power tolerance robustness detection method provided by the embodiment of the present application, and can achieve the same technical effects. To avoid repetition, details are not described herein.

[0122] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program or instruction-related hardware. The program can be stored in a computer readable storage medium. When the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM).

[0123] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0124] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and necessary general hardware platforms, of course, they can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc) and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner or network device, etc.) execute the methods described in the embodiments of the present application.

[0125] The embodiments of the present application are described above in combination with the drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative, not restrictive. Those skilled in the art can make many equivalent changes under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims, and all such changes are within the protection scope of the present application.

Claims

1. A method of detecting chip power tolerance robustness, characterized by, The detection method is based on a power tolerance detection device, the power tolerance detection device comprises a first power supply, a second power supply, a first power measurement unit, and a signal transmitting unit, a power amplifier, an isolator, a coupler, an attenuator and a second power measurement unit connected in sequence; the first power supply is used to power the power amplifier, the second power supply is used to provide voltage and current for the chip to be tested, and the first power measurement unit is used to detect the input power of the chip to be tested; The detection method comprises the following steps: S1, calibrating the insertion loss of the first power measurement unit and the insertion loss of the second power measurement unit; S2, turning on the first power supply and the second power supply, and recording the first static current of the second power supply at present; S3, turning on the signal transmitting unit, transmitting an input signal to the power amplifier through the signal transmitting unit, recording the measurement value of the first power measurement unit at present as a first measurement value, keeping the first measurement value of the first power measurement unit less than a first preset value, recording the measurement value of the second power measurement unit at present as a second measurement value, and calculating a first gain value of the chip to be tested according to the first measurement value and the second measurement value; S4, increasing the power of the transmission signal of the signal transmitting unit by a second preset value, and recording the measurement value of the first power measurement unit at present as a third measurement value; S5, turning off the signal transmitting unit, stopping transmitting the input signal to the power amplifier, and recording the second static current of the second power supply at present; comparing the first static current with the second static current to obtain a first comparison value; S6, turning on the signal transmitting unit, transmitting an input signal to the power amplifier through the signal transmitting unit, keeping the first measurement value of the first power measurement unit less than the first preset value, recording the measurement value of the second power measurement unit at present as a fourth measurement value, and calculating a second gain value of the chip to be tested according to the third measurement value and the fourth measurement value; comparing the first gain value with the second gain value to obtain a second comparison value; S7, judging whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, judging that the chip to be tested is damaged, and taking the third measurement value as the tolerance limit value of the chip to be tested; if not, returning to repeat steps S4-S7 until the tolerance limit value of the chip to be tested is obtained.

2. The method of claim 1, wherein the step of determining the power tolerance of the chip is performed by a power tolerance test program. The signal transmitting unit is used to transmit an input signal to the first input end of the power amplifier; The second input end of the power amplifier is connected with the first power supply, the output end of the power amplifier is connected with the input end of the isolator, and the isolator is used to block the reflected signal emitted after load mismatch; The output end of the isolator is connected with the input end of the coupler, the first output end of the coupler is connected with the input end of the first power measurement unit, and the second output end of the coupler is connected with the first input end of the chip to be tested; The coupler is used to couple the input signal of the chip to be tested; The second input end of the to-be-tested chip is connected with the second power supply, and the output end of the to-be-tested chip is connected with the input end of the attenuator, and the second power supply is used for detecting the static current of the to-be-tested chip; The output end of the attenuator is connected with the input end of the second power measurement unit; and the attenuator is used for reducing the output power of the to-be-tested chip; The second power measurement unit is used for detecting the output power of the to-be-tested chip. The signal transmitting unit is used for transmitting an input signal to the first input end of the power amplifier; The second input end of the power amplifier is connected with the first power supply, and the output end of the power amplifier is connected with the input end of the isolator, and the isolator is used for blocking the reflected signal emitted after load mismatch; The output end of the isolator is connected with the input end of the coupler, the first output end of the coupler is connected with the input end of the first power measurement unit, and the second output end of the coupler is connected with the first input end of the to-be-tested chip; The coupler is used for coupling the input signal of the to-be-tested chip; The second input end of the to-be-tested chip is connected with the second power supply, and the output end of the to-be-tested chip is connected with the input end of the attenuator, and the second power supply is used for detecting the static current of the to-be-tested chip; The output end of the attenuator is connected with the input end of the second power measurement unit; and the attenuator is used for reducing the output power of the to-be-tested chip; The second power measurement unit is used for detecting the output power of the to-be-tested chip.

3. The method of claim 1, wherein the step of determining the power tolerance of the chip is performed by a power tolerance test program. The first preset value is -20dBm.

4. The method of claim 1, wherein the method is performed by a test chip. The preset comparison value is 10%.

5. The method of claim 1, wherein the method is performed by a test chip. The attenuator is a 20dB attenuator.

6. A system for detecting chip power tolerance robustness, characterized by, The detection system comprises a power tolerance detection device, a calibration module, a power-on module, a gain calculation module, a power increase module, a first comparison module, a second comparison module and a judgment module, and the power tolerance detection device comprises a signal transmitting unit, a power amplifier, an isolator, a coupler, a first power measurement unit, an attenuator and a second power measurement unit; The output end of the signal transmitting unit is connected with the first input end of the power amplifier, and the signal transmitting unit is used for transmitting an input signal to the first input end of the power amplifier; The second input end of the power amplifier is connected with the first power supply, and the output end of the power amplifier is connected with the input end of the isolator, and the isolator is used for blocking the reflected signal emitted after load mismatch; The output end of the isolator is connected with the input end of the coupler, the first output end of the coupler is connected with the input end of the first power measurement unit, and the second output end of the coupler is connected with the first input end of the to-be-tested chip; and the coupler is used for coupling the input signal of the to-be-tested chip; The first power measurement unit is used for detecting the input power of the to-be-tested chip; The second input end of the to-be-tested chip is connected with the second power supply, and the output end of the to-be-tested chip is connected with the input end of the attenuator, and the second power supply is used for providing voltage and current for the to-be-tested chip and detecting the static current of the to-be-tested chip; The output end of the attenuator is connected with the input end of the second power measurement unit; and the attenuator is used for reducing the output power of the to-be-tested chip; The second power measurement unit is configured to detect the output power of the chip under test; The calibration module is configured to calibrate the first power measurement unit and the second power measurement unit; The power-on module is configured to turn on the first power supply and the second power supply, and record a first quiescent current of the second power supply; The gain calculation module is configured to turn on the signal transmitting unit, transmit an input signal to the power amplifier through the signal transmitting unit, record a first measurement value of the first power measurement unit, keep the first measurement value of the first power measurement unit less than a first preset value, record a second measurement value of the second power measurement unit, and calculate a first gain value of the chip under test according to the first measurement value and the second measurement value; The power increase module is configured to increase the power of the signal transmitted by the signal transmitting unit by a second preset value, and record a third measurement value of the first power measurement unit; The first comparison module is configured to turn off the signal transmitting unit, stop transmitting the input signal to the power amplifier, and record a second quiescent current of the second power supply; The first quiescent current and the second quiescent current are compared to obtain a first comparison value; The second comparison module is configured to turn on the signal transmitting unit, transmit the input signal to the power amplifier through the signal transmitting unit, keep the first measurement value of the first power measurement unit less than the first preset value, record a fourth measurement value of the second power measurement unit, calculate a second gain value of the chip under test according to the third measurement value and the fourth measurement value, and compare the first gain value and the second gain value to obtain a second comparison value; The judgment module is configured to judge whether the first comparison value or the second comparison value exceeds a preset comparison value: if yes, the chip under test is judged to be damaged, and the third measurement value is taken as a tolerance limit value of the chip under test; if not, the power increase module is returned to.

7. The system for detecting chip power tolerance robustness of claim 6, wherein, The first preset value is -20 dBm, and the preset comparison value is 10%.

8. The system for detecting chip power tolerance robustness of claim 6, wherein, The attenuator is a 20 dB attenuator.

9. A computer device, comprising: The chip power tolerance robustness detection device comprises: The memory, the processor, and a chip power tolerance robustness detection program stored in the memory and executable on the processor, wherein the processor implements the steps in the chip power tolerance robustness detection method according to any one of claims 1-5 when executing the chip power tolerance robustness detection program.

10. A computer readable storage medium characterized by The computer readable storage medium stores a chip power tolerance robustness detection program, and the chip power tolerance robustness detection program implements the steps in the chip power tolerance robustness detection method according to any one of claims 1-5 when executed by a processor.

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