Preparation method of SOI wafer structure and SOI wafer structure

Abstract

The invention provides a preparation method of an SOI wafer structure and the SOI wafer structure, and the method comprises the steps: sequentially forming a SiGe layer and a monocrystalline silicon layer on the surface of a first wafer, forming an oxide layer on the surface of a second wafer, bonding the oxide layer to the monocrystalline silicon layer, and then stripping and removing the SiGe layer and the first wafer. And transferring the monocrystalline silicon layer on the first wafer to the insulating layer on the surface of the second wafer to form an SOI wafer structure. According to the SOI wafer structure obtained by the method, the thickness of the monocrystalline silicon layer is controllable, and the uniformity is high; and the first wafer is stripped by using the SiGe layer as a stress buffer layer and an interface separation stop layer, so that excessive separation of the bonded wafers can be effectively avoided, interface defects are effectively reduced, and the quality of the SOI wafer is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a preparation method of an SOI wafer structure and an SOI wafer structure. BACKGROUND

[0002] With the continuous reduction of device feature size, silicon-on-insulator (SOI) technology emerges as the times require. The SOI wafer includes a top layer of silicon, a substrate, and a pre-embedded oxide layer between the top layer of silicon and the substrate. The SOI technology is an advanced semiconductor manufacturing technology, which can effectively reduce parasitic capacitance and leakage current, thereby improving device performance and having good development potential.

[0003] The first existing method for preparing an SOI wafer includes: using ion implantation technology to implant high-dose oxygen ions into a silicon wafer, so that the oxygen ions are distributed below the surface of the silicon wafer. Subsequently, high-temperature (about 1350℃) annealing treatment is performed to make the oxygen ions react with silicon to form a layer of silicon dioxide insulating layer, thereby obtaining an SOI structure with a top layer of silicon, a buried layer of silicon dioxide, and a bulk silicon.

[0004] The second existing method for preparing an SOI wafer includes: after a piece of silicon wafer is thermally oxidized to generate a silicon dioxide insulating layer, the silicon wafer is bonded to another silicon wafer, and then a back etching process is used to remove most of the silicon of one of the silicon wafers, leaving only a top layer of thin silicon. Finally, a CMP treatment is performed to obtain an SOI wafer.

[0005] However, the above-mentioned existing methods cannot effectively adjust the thickness of the top silicon layer, and the quality of the obtained SOI wafer is not high.

[0006] Therefore, how to prepare a high-quality SOI wafer has become a technical problem that needs to be solved in the industry. SUMMARY

[0007] In view of the above problems, the present application provides a preparation method of an SOI wafer structure and an SOI wafer structure to prepare a high-quality SOI wafer.

[0008] According to a first aspect of the present application, a preparation method of an SOI wafer structure is provided, comprising: providing a first wafer and forming a SiGe layer on the surface of the first wafer; forming a monocrystalline silicon layer on the surface of the SiGe layer; providing a second wafer and forming an oxide layer on the surface of the second wafer; bonding the oxide layer on the surface of the second wafer to the monocrystalline silicon layer of the first wafer to obtain a bonded third wafer; The SiGe layer in the third wafer and the first wafer are removed by exfoliation to form an SOI wafer structure, the SOI wafer structure comprising the second wafer, the oxide layer and the monocrystalline silicon layer.

[0009] Optionally, the removing the SiGe layer in the third wafer and the first wafer by exfoliation comprises: rapidly heating the third wafer to a first temperature at a heating rate greater than 15℃ / S; cooling to room temperature after maintaining the first temperature for a first time, so that the SiGe layer and the monocrystalline silicon layer are exfoliated to remove the SiGe layer and the first wafer.

[0010] Optionally, after the SiGe layer in the third wafer and the first wafer are removed by exfoliation, the method further comprises: removing the residual SiGe layer on the surface of the SOI wafer structure.

[0011] Optionally, the Ge content in the SiGe layer is 8% to 42%, and the Ge content increases first and then decreases along the film thickness direction of the SiGe layer.

[0012] Optionally, after the monocrystalline silicon layer is formed on the surface of the SiGe layer, before the SiGe layer in the third wafer and the first wafer are removed by exfoliation, the method further comprises the following steps: forming a fragile layer at the interface of the SiGe layer in contact with the monocrystalline silicon layer.

[0013] Optionally, the removing the SiGe layer in the third wafer and the first wafer by exfoliation is specifically removing the SiGe layer in the third wafer and the first wafer by exfoliation at the fragile layer.

[0014] Optionally, the forming a fragile layer at the interface of the SiGe layer in contact with the monocrystalline silicon layer specifically comprises the following steps: implanting fragile ions into a preset depth position at the top of the SiGe layer in contact with the monocrystalline silicon layer; performing a thermal annealing treatment on the first wafer to form a fragile layer at the interface of the SiGe layer in contact with the monocrystalline silicon layer.

[0015] Optionally, the fragile ions are H + ions, and the ion implantation dose is 5E10 / cm 2 ~ 5E16 / cm 2 .

[0016] Optionally, before the bonding the oxide layer on the surface of the second wafer to the monocrystalline silicon layer of the first wafer, the method further comprises the step of: The surface of the single crystal silicon layer and the oxide layer is subjected to plasma activation treatment using a first inert gas.

[0017] According to a second aspect of the present application, there is provided an SOI wafer structure prepared by the method for preparing an SOI wafer structure as described above.

[0018] The method for preparing an SOI wafer structure provided by the present application forms a SiGe layer and a single crystal silicon layer on the surface of a first wafer in sequence, forms an oxide layer on the surface of a second wafer, bonds the oxide layer to the single crystal silicon layer, and then removes the SiGe layer and the first wafer, so as to transfer the single crystal silicon layer on the first wafer to the insulating layer on the surface of the second wafer, thereby forming an SOI wafer structure. The SOI wafer structure obtained by the method has a controllable and high-uniformity thickness of the single crystal silicon layer, and the use of the SiGe layer as a stress buffer layer and an interface separation stop layer to remove the first wafer can effectively avoid excessive separation of the wafer after bonding, effectively reduce interface defects, and improve the quality of the SOI wafer. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0020] Figure 1 is a step flow diagram of the method for preparing an SOI wafer structure provided by an embodiment of the present application; Figure 2 is a step flow diagram of the removal of the SiGe layer provided by an embodiment of the present application; Figure 3 is a step flow diagram of the formation of a fragile layer provided by an embodiment of the present application; Figures 4-9 is a structure diagram corresponding to each step of the method for preparing an SOI wafer structure provided by an embodiment of the present application; Figures 10-11 is a structure diagram corresponding to each step of the formation of a fragile layer provided by an embodiment of the present application; Figure 12 is a third wafer structure diagram of the bonding of a first wafer containing a fragile layer and a second wafer provided by an embodiment of the present application.

[0021] Explanation of reference signs: 100 - first wafer; 101 - SiGe layer 102 - single crystal silicon layer; 103 - embrittlement layer; 200 - second wafer; 201 - oxidation layer; 300 - third wafer; 400 - SOI wafer structure. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0023] The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0024] As described in the background, the SOI wafer obtained by the existing method for preparing the SOI wafer cannot effectively adjust the thickness of the top silicon layer, and the quality of the obtained SOI wafer is not high.

[0025] Therefore, the present application provides a method for preparing an SOI wafer structure. The SiGe layer and the single crystal silicon layer are formed on the surface of the first wafer in sequence, the oxidation layer is formed on the surface of the second wafer, and then the oxidation layer is bonded to the single crystal silicon layer. Then, the SiGe layer and the first wafer are peeled off and removed, so that the single crystal silicon layer on the first wafer is transferred onto the insulating layer on the surface of the second wafer to form the SOI wafer structure. The thickness of the single crystal silicon layer of the SOI wafer structure obtained by the method is controllable and has high uniformity. By using the SiGe layer as a stress buffer layer and an interface separation stop layer to peel off the first wafer, the excessive separation of the wafer after bonding can be effectively avoided, the interface defects are effectively reduced, and the quality of the SOI wafer is improved.

[0026] Embodiment 1: Please refer to Figures 1-2and in combination Figures 4-9 The preparation method of the SOI wafer structure provided by the embodiment of the present application comprises the following steps: S101: providing a first wafer 100 and forming a SiGe layer 101 on the surface of the first wafer; the device structure schematic diagram after the completion of the step is shown in Figure 4 .

[0027] As an example, the first wafer 100 may be a silicon wafer. Of course, the present application is not limited thereto, and other types of wafers such as germanium wafers are also within the protection scope of the present application.

[0028] As a specific implementation, the forming method of the SiGe layer 101 on the first wafer 100 is specifically: using the RPCVD process to epitaxially grow the SiGe layer 101, and the process temperature of the RPCVD is for example 600-800°C. The thickness of the SiGe layer 101 may be for example 100-250 nm, and the Ge content in the SiGe layer 101 may be for example 8-42%, and the Ge content in the SiGe layer gradually increases and then decreases along the film thickness direction of the SiGe layer, that is, the Ge content gradually increases and then decreases from the side close to the first wafer to the side close to the monocrystalline silicon layer. Specifically, the Ge content in the SiGe layer close to the first wafer is 8%, and as the thickness of the SiGe layer increases, the Ge content also gradually increases, and the Ge content is the highest at the middle thickness of the SiGe layer, which is 42%, and then as the thickness of the SiGe layer increases, the Ge content also gradually decreases, and the Ge content close to the monocrystalline silicon layer of the SiGe layer is preferably 10%. Through the stepwise setting of the Ge content of different film thicknesses in the SiGe layer, the lattice matching between the formed SiGe layer 101 and the monocrystalline silicon layer 102 subsequently formed on the surface thereof is ensured, the normal growth of the monocrystalline silicon on the SiGe layer is ensured, the interface defects of the monocrystalline silicon layer are reduced, and thus the interface defects of the SOI wafer top silicon layer film (i.e. the monocrystalline silicon layer 102) subsequently formed are reduced. Further, by controlling the concentration distribution of Ge in the formed SiGe layer 101, the uniformity of the growth of the SiGe layer on the first wafer and the uniformity of the growth of the monocrystalline silicon layer on the SiGe layer are ensured, the stress matching between the SiGe layer and the first wafer and the monocrystalline silicon layer 102 is improved, the wafer warping of the first wafer possibly occurring during the growth of the SiGe layer and the monocrystalline silicon layer is reduced, and thus the excessive separation of the third wafer subsequently bonded with the second wafer is effectively avoided, the bonding effect of the monocrystalline silicon layer and the oxide layer of the second wafer is improved, and the quality of the finally formed SOI wafer is ensured. As a preferred implementation, before forming the SiGe layer 101, the surface of the first wafer 100 is cleaned with deionized water to remove the possible contaminants on the surface of the first wafer 100.

[0029] S102: Form a monocrystalline silicon layer 102 on the surface of the SiGe layer 101, as shown in Figure 5

[0030] As a specific embodiment, the monocrystalline silicon layer 102 on the surface of the SiGe layer 101 is formed by epitaxial growth of the monocrystalline silicon layer 102 by RPCVD process. The thickness of the monocrystalline silicon layer 102 may, for example, be 5nm-300nm, and the process temperature of the RPCVD may, for example, be 600℃-800℃. In the subsequent formation of the SOI wafer structure, the monocrystalline silicon layer 102 serves as the top silicon layer of the SOI wafer, and the thickness of the monocrystalline silicon grown here determines the thickness of the top silicon layer of the subsequently formed SOI wafer. By controlling the thickness of the monocrystalline silicon grown here, the thickness of the top silicon layer of the SOI wafer can be effectively adjusted. Those skilled in the art can grow a monocrystalline silicon layer 102 of a suitable thickness on the SiGe layer of the first wafer according to the actual thickness of the semiconductor device required; further, as the top silicon layer (i.e. the monocrystalline silicon layer 102) of the SOI wafer in the method of the embodiment, there is no need to perform a CMP process on the top silicon layer of the finally obtained SOI wafer to adjust the thickness of the top silicon layer, nor is there a need to obtain a buried oxide layer of the SOI by ion implantation process, thereby reducing the interface defects on the surface of the SOI top silicon layer film and ensuring the uniformity of the SOI top silicon layer film, thereby ensuring the quality of the top silicon layer of the SOI wafer.

[0031] As a preferred embodiment, the thickness of the SiGe layer 101 is 200nm, the process temperature for epitaxial growth of the SiGe layer 101 by RPCVD is 650℃, and the Ge content in the SiGe layer 101 is 8%-42%. The Ge content in the SiGe layer increases first and then decreases along the film thickness direction of the SiGe layer, so that the lattice matching and stress matching between the SiGe layer 101 and the monocrystalline silicon layer 102 reach the best level, thereby effectively avoiding excessive separation of the third wafer after bonding and reducing the interface defects of the monocrystalline silicon layer 102. The thickness of the monocrystalline silicon layer 102 is 220nm, and the process temperature for epitaxial growth of the monocrystalline silicon layer 102 by RPCVD is 750℃, so that the deposition rate and film uniformity of the monocrystalline silicon layer 102 reach the best level, thereby effectively improving the quality of the monocrystalline silicon layer 102.

[0032] The SiGe layer 101 and the polycrystalline silicon layer 102 are formed by epitaxial growth by RPCVD in the present application, and the thickness fluctuation range of the SiGe layer 101 and the polycrystalline silicon layer 102 can be accurately controlled within ±1nm. Of course, it should be realized that the present application is not limited thereto, and other epitaxial growth processes are also within the protection scope of the present application.

[0033] S103: Provide a second wafer 200 and form an oxide layer 201 on the surface of the second wafer 200; the device structure after this step is shown in​Figure 6

[0034] As a specific embodiment, before forming the oxide layer 201, the surface of the second wafer 200 is cleaned by deionized water to remove possible contaminants on the surface of the second wafer 200.

[0035] As an example, the second wafer 200 can be a silicon wafer, and the oxide layer 201 can be a SiO2layer.

[0036] As an example, the process of forming the oxide layer 201 is a vapor deposition process. Specifically, a SiO2layer is formed on the upper surface of the silicon wafer by the vapor deposition process, and in the subsequent formation of the SOI wafer structure, the oxide layer 201 serves as the buried oxide layer of the SOI wafer. The thickness of the SiO2layer grown here determines the thickness of the buried oxide layer of the subsequently formed SOI wafer. The thickness of the SiO2layer can be, for example, 1500 nm to 2500 nm to meet the specification requirements of the SOI wafer.

[0037] As another example, the process of forming the oxide layer 201 is a high-temperature furnace tube process. Specifically, a SiO2layer is deposited on the upper and lower surfaces of the silicon wafer by the high-temperature furnace tube process, as shown in Figure 7 The thickness of the SiO2layer can be, for example, 1500 nm to 2500 nm to meet the specification requirements of the SOI wafer. By depositing a SiO2layer on the lower surface of the silicon substrate, the stress mismatch generated by different material layers can be effectively balanced during subsequent bonding and heat treatment, thereby improving the flatness of the third wafer after bonding and improving the process yield.

[0038] Of course, it should be noted that step S103 in the embodiment of the present application can also be located before step S101, i.e., step S103 is performed first, and then steps S101-S102 are performed. Steps S103 and steps S101-S102 can also be performed simultaneously, and all three ways are within the protection scope of the present application.

[0039] S104: Bonding the oxide layer 201 on the surface of the second wafer to the single-crystal silicon layer 102 of the first wafer to obtain a bonded third wafer 300. The device structure after step S104 is shown in Figure 8

[0040] ​​As an embodiment, before step S104, the method further comprises: performing plasma activation treatment on the surface of the single crystal silicon layer 102 and the oxide layer 201 by using a first inert gas. By using the plasma of the first inert gas to bombard the surface of the single crystal silicon layer 102 and the oxide layer 201, the particles adsorbed on the surface of the single crystal silicon layer 102 and the oxide layer 201 can be peeled off and removed, so as to avoid the formation of gaps or weak bonding points of contaminants at the bonding interface. In addition, the plasma can also introduce high-activity groups to the bonding surface through chemical modification, so as to improve the bonding strength.

[0041] As an example, the first inert gas can be nitrogen. Of course, it should be realized that the present application is not limited thereto, and other types of inert gases, such as argon, etc., are also within the protection scope of the present application.

[0042] As an example, the bonding method can be fusion bonding. Of course, it should be realized that the present application is not limited thereto, and other types of bonding methods are also within the protection scope of the present application.

[0043] S105: stripping and removing the SiGe layer in the third wafer and the first wafer to form an SOI wafer structure 400, as shown in Figure 9 The SOI wafer structure 400 includes the second wafer 200, the oxide layer 201 and the single crystal silicon layer 102, that is, the second wafer 200 serves as the bottom silicon layer of the SOI wafer, the oxide layer 201 serves as the buried oxide layer of the SOI wafer, and the single crystal silicon layer 102 serves as the top silicon layer of the SOI wafer.

[0044] Since the single crystal silicon layer 102 obtained by epitaxy is used as the top silicon layer in the embodiment of the present application, the thickness of the top silicon layer is controllable and has high uniformity. Moreover, the SiGe layer is formed between the single crystal silicon layer 102 and the first wafer, and the first wafer is stripped by using the SiGe layer as a stress buffer layer and an interface separation stop layer, so that the excessive separation of the wafer after bonding can be effectively avoided, the interface defects are effectively reduced, and the quality of the SOI wafer is improved.

[0045] As shown in Figure 2 As a specific embodiment, step S105 includes: S1051: rapidly heating the third wafer to a first temperature at a heating rate greater than 15℃ / S, so that the shear stress is generated at the interface between the SiGe layer 101 and the single crystal silicon layer 102 due to the difference in the thermal expansion coefficients between the SiGe layer 101 and the single crystal silicon layer 102.

[0046] S1052: After the first time of keeping warm, cooling to room temperature to make the SiGe layer 101 break and peel off, so as to peel off the SiGe layer 101 from the third wafer. Specifically, in the process of cooling the third wafer from the first temperature to room temperature, the interface between the SiGe layer 101 and the monocrystalline silicon layer 102 breaks due to the sharp change of the shear stress.

[0047] Since the lattice constant of the SiGe layer 101 is greater than that of the monocrystalline silicon layer 102, the thermal expansion coefficient of the SiGe layer 101 is greater than that of the monocrystalline silicon layer 102. During the heating process, the SiGe layer 101 and the monocrystalline silicon layer 102 cannot expand freely due to the tight combination through the interface, the chemical bond and the mechanical constraint, and the monocrystalline silicon layer 102 will limit the "excess expansion" of the SiGe layer 101, so that the SiGe layer 101 is forced to bear compressive stress, and at the same time, the SiGe layer 101 will pull the monocrystalline silicon layer 102, so that it bears tensile stress. The stress generated by the difference in expansion of the two material films is "tensile type" shear stress at the interface of the two materials, that is, the stress component parallel to the interface, thereby aggravating the lattice mismatch between the SiGe layer 101 and the monocrystalline silicon layer 102. When the temperature rises slowly, the SiGe layer and the monocrystalline silicon layer have more sufficient time to release part of the stress through lattice relaxation, dislocation movement and other ways, so as to reduce the interface shear force. Only when the temperature rises rapidly, the stress cannot be released in time, and it will accumulate rapidly at the interface. In addition, rapid heating will cause transient non-uniform temperature distribution of the two layers of materials, which can further aggravate the local stress concentration, so as to significantly increase the shear stress between the SiGe layer 101 and the monocrystalline silicon layer 102, and significantly aggravate the lattice mismatch between the two layers.

[0048] When the temperature rises rapidly, the shear stress generated by the difference in thermal expansion coefficient between the SiGe layer 101 and the monocrystalline silicon layer 102 is mainly concentrated at the interface of the two. Due to the rapid heating, the stress distribution will appear transient non-uniformity and local concentration, such as at the edge or defect, so that the uniformity of subsequent peeling is poor. Through a period of keeping warm, the temperature gradient in the material can be effectively eliminated, so that the shear stress is more uniformly distributed at the interface of the SiGe layer and the monocrystalline silicon layer, thereby avoiding the premature release of local stress, such as stress dispersion caused by small range cracking. At the same time, the atoms at the interface are more likely to diffuse or rearrange under the joint action of thermal activation and interface shear stress during the keeping warm, so that the local chemical bond between the SiGe layer and the monocrystalline silicon layer caused by the aggravation of the lattice mismatch due to rapid heating is further weakened or broken, thereby providing a micro-defect basis for subsequent peeling.

[0049] In the cooling process after the heat preservation period, due to the shrinkage of the SiGe layer 101 being greater than that of the monocrystalline silicon layer 102, a shear stress opposite to that in the heating process will be generated at the interface between the SiGe layer 101 and the monocrystalline silicon layer 102. Since the interface micro defects have been accumulated in the heating and heat preservation stages, the opposite stress will further tear the weak areas of the interface, so that the SiGe layer 101 and the monocrystalline silicon layer 102 are broken apart from the interface.

[0050] As an example, the first temperature can be 600-900℃, the rapid heating process used can be a rapid thermal processing (RTP), and the first time can be 5-15 minutes.

[0051] In the preferred embodiment, the first temperature is 800℃, the heating rate is 20℃ / S, and the third wafer 300 is cooled to room temperature after being heat preserved for 10 minutes, so that the shear stress at the interface between the SiGe layer 101 and the monocrystalline silicon layer 102 is uniformly distributed and has a sufficient strength to make the SiGe layer 101 and the monocrystalline silicon layer 102 break apart more uniformly, so that the SiGe layer 101 is peeled off with less residue, and the monocrystalline silicon layer 102 is completely transferred to the surface of the oxide layer 201 of the second wafer 20 to form an SOI wafer structure 400, thereby precisely controlling the thickness and uniformity of the monocrystalline silicon layer on the surface of the SOI wafer structure.

[0052] It can be seen that, by precisely controlling the heating rate, heat preservation time and cooling time, and by utilizing the difference in the thermal expansion coefficients between the SiGe layer 101 and the monocrystalline silicon layer 102, a controllable and uniformly distributed shear stress is generated at the interface between the SiGe layer 101 and the monocrystalline silicon layer 102. When the shear stress exceeds the bonding strength of the SiGe layer 101 and the monocrystalline silicon layer 102, the SiGe layer 101 will be peeled off from the interface between the SiGe layer 101 and the monocrystalline silicon layer 102, so that the entire peeling process is controllable and the interface defects generated by the peeling are less. Meanwhile, the SiGe layer 101 acts as a stress buffer layer and an interface separation stop layer, which can effectively prevent the over separation of the bonded wafers, thereby precisely controlling the thickness and uniformity of the monocrystalline silicon layer 102 on the surface of the SOI wafer structure, and further effectively improving the quality of the SOI wafer structure and the yield of the preparation process.

[0053] As a specific embodiment, after the SiGe layer in the third wafer is peeled off and removed, the method further comprises: removing the residual SiGe layer on the surface of the SOI wafer structure. This is because the SiGe layer 101 will leave some residual SiGe layer on the surface of the SOI wafer structure 400 after being peeled off and removed.

[0054] As a specific example, removing the residual SiGe layer on the surface of the SOI wafer structure specifically includes: high-temperature thermal annealing treatment is performed on the SOI wafer structure 400; a wet etching process is used to remove the residual SiGe layer on the surface of the SOI wafer structure 400; and a chemical mechanical polishing (CMP) process is used to polish the surface of the SOI wafer structure 400.

[0055] As an example, the high-temperature thermal annealing treatment has a time of, for example, 25-35 minutes and an annealing temperature of, for example, 1000-1200°C. In a preferred embodiment, the annealing temperature is 1100°C and the annealing time is 30 minutes.

[0056] The high-temperature thermal annealing treatment can effectively repair the interface defects between the oxide layer 201 and the monocrystalline silicon layer 102, thereby improving the interface quality between the oxide layer 201 and the monocrystalline silicon layer 102. In a preferred embodiment, the interface defects between the oxide layer 201 and the monocrystalline silicon layer 102 are repaired most effectively, while avoiding excessive load on the machine equipment.

[0057] As an example, the wet etching solution includes at least one of HNO3, HF, and CH3COOH. The etching rate of the wet etching solution on the residual SiGe layer is greater than the etching rate on the monocrystalline silicon layer 102, so as to avoid damaging the monocrystalline silicon layer 102.

[0058] The CMP process polishes the surface of the SOI wafer structure 400, so that the film thickness uniformity of the monocrystalline silicon layer 102 is improved to ±0.5 nm, thereby ensuring the film uniformity and quality of the top silicon layer of the formed SOI wafer.

[0059] Embodiment 2: As a preferred embodiment, between step S102 and step S103, there is further included: a brittle layer 103 is formed at the interface of the SiGe layer 101 abutting the monocrystalline silicon layer 102, as shown in Figure 11 .

[0060] As shown in Figure 3 , as a specific embodiment, forming the brittle layer 103 specifically includes the following steps: S1021: implanting brittle ions into a preset depth position at the top of the SiGe layer 101 abutting the monocrystalline silicon layer 102, as shown in Figure 10 ; S1022: performing thermal annealing treatment on the first wafer to form a brittle layer 103 at the interface of the SiGe layer 101 abutting the monocrystalline silicon layer 102, as shown in Figure 11 .

[0061] As an example, the embrittlement ion could be H+. + Ions, ion implantation dose of 4E15 / cm 2 ~ 7E16 / cm 2 The ion implantation energy is 70 KeV, and the preset depth is about 10 nm below the interface between the SiGe layer 101 and the single-crystal silicon layer 102.

[0062] By precisely controlling the ion implantation dosage and energy, the peak distribution of embrittlement ions can be precisely positioned at a preset depth, while also avoiding the interface damage to the single-crystal silicon layer 102 caused by high-energy ion implantation in existing technologies; and compared to other heavy ions, H + Ions have extremely small radii and light weight, and after implantation, they are not likely to cause large displacement damage in the crystal lattice. However, they can diffuse and accumulate at interface defects, such as dislocations and vacancies, thus providing a basis for the formation of an embrittlement layer, and introducing few interface defects.

[0063] Of course, it should be understood that the present invention is not limited thereto, and other types of embrittlement ions are also within the scope of protection of the present invention.

[0064] In this process, by performing thermal annealing on the first wafer, the peak value of the embrittlement ions is ultimately distributed at a preset depth to form an embrittlement layer 103.

[0065] Except for the step of forming the embrittlement layer 103 added to Example 1, this embodiment is the same as Example 1 in other aspects, and will not be repeated here.

[0066] The schematic diagram of the device structure after bonding the oxide layer 201 on the surface of the second wafer 20 to the SiGe layer 101 is shown below. Figure 12 As shown. The SiGe layer 101 in the third wafer is peeled off from the embrittlement layer 103 to form the SOI wafer structure 400.

[0067] In a preferred embodiment of the present invention, by employing low-energy embrittlement ion implantation to form an embrittlement layer 103 at the interface between the SiGe layer 101 and the monocrystalline silicon layer 102, a stress-induced layer can be further formed between the SiGe layer 101 and the monocrystalline silicon layer 102, thereby effectively reducing the bonding strength between the SiGe layer 101 and the monocrystalline silicon layer 102, further improving the controllability of the subsequent SiGe layer 101 peeling process, so as to further achieve precise control of the thickness of the monocrystalline silicon layer after peeling, while effectively avoiding the interface damage to the monocrystalline silicon layer 102 caused by high-energy ion implantation in the prior art, and having fewer residual SiGe layers and peeling defects after peeling.

[0068] According to an embodiment of the present application, there is also provided an SOI wafer structure prepared by the above method.

[0069] Those skilled in the art will appreciate that embodiments of the present application can be provided as methods, apparatus, or electronic equipment, and thus the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating an SOI wafer structure, characterized by, The method comprises the following steps: providing a first wafer and forming a SiGe layer on the surface of the first wafer; forming a monocrystalline silicon layer on the surface of the SiGe layer; providing a second wafer and forming an oxide layer on the surface of the second wafer; bonding the oxide layer on the surface of the second wafer to the monocrystalline silicon layer of the first wafer to obtain a third wafer after bonding; removing the SiGe layer and the first wafer in the third wafer to form an SOI wafer structure, wherein the SOI wafer structure comprises the second wafer, the oxide layer and the monocrystalline silicon layer.

2. The method of claim 1, wherein the SOI wafer structure is prepared by a method comprising: The removing the SiGe layer and the first wafer in the third wafer comprises: rapidly heating the third wafer to a first temperature at a heating rate greater than 15℃ / S; after maintaining the first temperature for a first time, cooling to room temperature to cause the SiGe layer and the monocrystalline silicon layer to be broken and peeled off to remove the SiGe layer and the first wafer.

3. The method of claim 2, wherein the SOI wafer structure is prepared by the steps of: After the removing the SiGe layer and the first wafer in the third wafer, the method further comprises: ​ removing the residual SiGe layer on the surface of the SOI wafer structure.

4. The method of claim 1, wherein the SOI wafer structure is prepared by a method comprising: The content of Ge in the SiGe layer is 8% to 42%, and the content of Ge increases first and then decreases along the film thickness direction of the SiGe layer.

5. The method of producing an SOI wafer structure according to any one of claims 1 to 4, wherein After the forming the monocrystalline silicon layer on the surface of the SiGe layer, before the removing the SiGe layer and the first wafer in the third wafer, the method further comprises the following steps: forming a fragile layer at the interface of the SiGe layer in contact with the monocrystalline silicon layer.

6. The method of manufacturing an SOI wafer structure according to claim 5, wherein The removing the SiGe layer and the first wafer in the third wafer is specifically removing the SiGe layer and the first wafer in the third wafer at the fragile layer.

7. The method of claim 5, wherein the step of forming the SOI wafer structure is performed by a method comprising: The forming the fragile layer at the interface of the SiGe layer in contact with the monocrystalline silicon layer specifically comprises the following steps: ​ implanting fragile ions into a preset depth position at the top of the SiGe layer in contact with the monocrystalline silicon layer; performing a thermal annealing treatment on the first wafer to form a fragile layer at the interface of the SiGe layer in contact with the monocrystalline silicon layer.

8. The method of producing an SOI wafer structure according to claim 7, wherein The embrittling ions are H + ions, ion implantation dose of 5E10 / cm 2 ~ 5E16 / cm 2 .

9. The method of producing an SOI wafer structure according to claim 1, wherein Before the bonding the oxide layer on the surface of the second wafer to the monocrystalline silicon layer of the first wafer, the method further comprises the following step: performing a plasma activation treatment on the surface of the monocrystalline silicon layer and the oxide layer by using a first inert gas.

10. An SOI wafer structure, characterized by, The SOI wafer structure is prepared by using the preparation method of the SOI wafer structure according to any one of claims 1 to 9.

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