Memristor-based ternary logic gate circuit, control method and system

Abstract

The application discloses a kind of three-value logic gate circuit based on memristor, control method and system, belong to microelectronic logic operation technical field;The application includes two memristors, a fixed value resistance and a multi-value comparator, utilize the high resistance state, the medium resistance state and the low resistance state of memristor correspond to different three-value logic respectively, by adjusting the voltage of the input port of memristor, and by multi-value comparator, the voltage V c With the relationship between preset reference voltage V r1 And V r2 It can realize the judgment and output of three-value logic, both can realize three-value logic operation with two inputs, also can realize three-value logic operation with single input by suspended input, with higher versatility.At the same time, the application has simple structure, and does not need to rely on the resistance value state of memristor to express output result, not easy to be restricted by the flip characteristics of memristor, can realize accurate three-value logic gate operation with a simple and more general circuit structure.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic logic operation technology, and more specifically, relates to a memristor-based ternary logic gate circuit, control method and system. Background Technology

[0002] Traditional computers employ the von Neumann architecture, in which storage and processing units are physically separated. Typically, the processing unit reads data from storage, performs the corresponding arithmetic and logical operations, and then writes the data back to storage. The reading of stored information and the transport of data streams place enormous demands on peripheral read and control circuits, impose significant overhead and challenges on the data transmission bus, and result in substantial power consumption. Furthermore, engineers often need to adjust the speeds of processing units, storage units, and even the bus to achieve optimal matching and reduce idle time between units. However, achieving this matching is difficult, often leading to inefficient resource allocation and utilization among units. Therefore, better addressing the "bottleneck problem" and "memory wall" problem inherent in the existing von Neumann architecture has become a key research focus in the field of computer architecture.

[0003] To overcome these bottlenecks, in-memory computing technology has emerged. This technology integrates computing and storage functions on the same hardware platform, achieving advantages such as high computational parallelism, low latency, and low power consumption, and has gradually become a research hotspot in academia and industry. Memristors, as a novel type of non-volatile memory device, possess advantages such as low power consumption, small size, and compatibility with CMOS processes, making them an ideal candidate for in-memory computing architectures. Memristors can store information by changing their resistance state and retain that resistance state even after power is off, thus making them naturally suitable for digital logic operations.

[0004] Multivalued computation is a promising computational method in next-generation computing. Unlike traditional Boolean logic, which uses only binary states (1 and 0) for computation, multivalued computation utilizes two or more logical states. Due to the increased number of basic states, multivalued computation can improve computational efficiency by reducing data size. Ternary logic computation is the most basic type of multivalued logic computation. The basic states can usually be represented by numbers 0, 1, and 2. Based on the number of input logical values, it can be divided into ternary logic operations with two inputs and ternary logic operations with one input.

[0005] Existing ternary logic circuit implementations based on memristors mostly only support specific ternary logic operations. Different circuits are designed for different types of ternary logic operations, resulting in poor versatility and complex circuitry. In particular, ternary logic circuit implementations based on memristor state inversion express the results of ternary logic operations based on the memristor's resistance state, making them susceptible to the limitations of memristor switching characteristics and affecting the accuracy of the results. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a memristor-based ternary logic gate circuit, control method and system, the purpose of which is to provide a simple and relatively universal circuit structure to realize accurate ternary logic gate operation.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a three-valued logic gate circuit based on memristors, comprising: a multi-valued comparator, a resistor, and two identical memristors M1 and M2; the positive terminals of memristors M1 and M2 are respectively denoted as port T1 and port T2, and the negative terminals of both are connected to the first terminal of the resistor; the second terminal of the resistor is denoted as port T3.

[0008] A multi-value comparator is used to convert the voltage V at the first terminal of a resistor. c Each with a preset reference voltage V r1 and V r2 The comparison is performed, and the output voltage value corresponding to the result of the ternary logic operation is obtained, thus yielding the result of the ternary logic operation: when V c <V r1 When V is in the range Z1, the multi-value comparator outputs a voltage corresponding to the value Z1; when V is in the range Z1, the multi-value comparator outputs a voltage corresponding to the value Z1. r1 <V c <V r2 The multi-value comparator outputs a voltage corresponding to the value Z2; when V c >V r2 The multi-value comparator outputs a voltage corresponding to the value Z3;

[0009] When the above ternary logic gate circuit is used to perform a ternary logic operation with two inputs on input values ​​a and b: the resistance state of memristor M1 is the resistance state corresponding to value a; the resistance state of memristor M2 is the resistance state corresponding to logic value b; port T1 is used to connect voltage V. T1 Port T T2 Used to connect voltage V T2 Port T3 is used for grounding; V r1 =V r1,2 V r2 =V r2,2 Voltage V T1 V T2 V r1,2 Vr2,2 The value of is determined by the three-valued logic operation type with two inputs;

[0010] When the above ternary logic gate is used to perform a ternary logic operation with a single input on the input value a: the resistance state of memristor M1 is the resistance state corresponding to the value a; port T1 is used to connect voltage V. T1 Port T2 is left floating; port T3 is used for grounding; V r1 =V r1,1 V r2 =V r2,1 Voltage V T1 V r1,1 V r2,1 The value of is determined by the three-valued logic operation type with a single input;

[0011] Where a is Z1, Z2, or Z3; b is Z1, Z2, or Z3; the memristor resistance states corresponding to the values ​​Z1, Z2, and Z3 are respectively the high resistance state, intermediate resistance state, and low resistance state of the memristor; the resistance value in the intermediate resistance state is the preset resistance value R. IRS ;R LRS <R IRS <R HRS ;R LRS R is the resistance value of the memristor in its low-resistance state. HRS This represents the resistance value of the memristor when it is in a high-resistance state.

[0012] More preferably, for each three-valued logic operation with two inputs, the corresponding voltage V T1 V T2 V r1,2 V r2,2 The values ​​of satisfy the following simultaneously:

[0013]

[0014]

[0015]

[0016] Among them, conductivity value ; The resistance value of memristor M1 when the resistance state is the resistance state corresponding to the value P;

[0017] conductivity ; The resistance of memristor M2 when its resistance state corresponds to the value Q;

[0018] conductivity R is the resistance value;

[0019] and For any pair of input values ​​corresponding to the output value Z1 in the truth table of a three-valued logic operation with two inputs;

[0020] and For any pair of input values ​​corresponding to the output value Z2 in the truth table of a three-valued logic operation with two inputs;

[0021] and For any pair of input values ​​corresponding to the output value Z3 in the truth table of a three-valued logic operation with two inputs.

[0022] More preferably, for each three-valued logic operation with a single input, the corresponding voltage V T1 '、V r1,1 V r2,1 The values ​​of satisfy the following simultaneously:

[0023]

[0024] Among them, conductivity value ; The resistance value of memristor M1 when the resistance state is the resistance state corresponding to the value P;

[0025] conductivity R is the resistance value;

[0026] and For any pair of input values ​​corresponding to the output value Z1 in the truth table of a three-valued logic operation with a single input;

[0027] and For any pair of input values ​​corresponding to the output value Z2 in the truth table of a three-valued logic operation with a single input;

[0028] and For any pair of input values ​​corresponding to the output value Z3 in the truth table of a three-valued logic operation with a single input.

[0029] More preferably, when the above-mentioned ternary logic gate circuit is used to perform a ternary single-input logic operation on the input value a, the resistance value is: .

[0030] More preferably, R LRS : R IRS : R HRS = 1: 10: 100.

[0031] More preferably, the value Z1 is 0; the value Z2 is 1; and the value Z3 is 2.

[0032] In a second aspect, the present invention provides a control method for a ternary logic gate circuit based on a memristor; wherein the ternary logic gate circuit is the ternary logic gate circuit provided in the first aspect of the present invention;

[0033] When the above-mentioned ternary logic gate circuit is used to perform a ternary logic operation with two inputs on input values ​​a and b: the above control method includes: setting the resistance state of memristor M1 to the resistance state corresponding to value a; setting the resistance state of memristor M2 to the resistance state corresponding to logic value b; and connecting voltage V to port T1. T1 ; at port T T2 Input voltage V T2 Ground port T3; read the result of the ternary logic operation from the output of the multi-value comparator;

[0034] When the above ternary logic gate is used to perform a ternary logic operation with a single input on the input value a: the control method includes: setting the resistance state of memristor M1 to the resistance state corresponding to the value a; and connecting voltage V to port T1. T1 Set port T2 to a floating state; ground port T3; read the result of the three-valued logic operation from the output of the multi-valued comparator.

[0035] More preferably, the method for setting the resistance state of the memristor M to a resistance state corresponding to the value d includes:

[0036] Initialize memristor M to a high-resistance state; memristor M can be memristor M1 or M2.

[0037] When the value d is Z1 and the memristor M is M1, the port T1 is grounded, the port T2 is set to floating state, and the voltage V1 is connected to the port T3, so that the resistance state of the memristor M is set to the resistance state corresponding to the value d.

[0038] When the value d is Z2 and the memristor M is M1, the voltage V2 is applied to port T1, port T2 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0039] When the value d is Z3 and the memristor M is M1, the voltage V3 is applied to port T1, port T2 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0040] When the value d is Z1 and the memristor M is M2, the port T2 is grounded, the port T1 is set to floating state, and the voltage V1 is connected to the port T3, so that the resistance state of the memristor M is set to the resistance state corresponding to the value d.

[0041] When the value d is Z2 and the memristor M is M2, the voltage V2 is applied to port T2, port T1 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0042] When the value d is Z3 and the memristor M is M2, the voltage V3 is applied to port T2, port T1 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0043] Where V1 satisfies: V2 satisfies: V2 - V c-HRS >V iset V3 satisfies: V3-V c-HRS >V set ;Voltage Conductivity Conductivity Conductivity R is the resistance value; V set The voltage threshold for a memristor to transition from a high-resistance state to a low-resistance state; voltage V reset The voltage threshold for a memristor to transition from a low-resistance state to a high-resistance state; V iset The resistance value of the memristor is the preset resistance value R. IRS The voltage value corresponding to the time; V reset <V iset <V set .

[0044] More preferably, the method for initializing the memristor M to a high-resistivity state includes:

[0045] When the memristor M is memristor M1, ground port T1, set port T2 to floating state, and apply voltage V1 to port T3 to initialize memristor M to a high impedance state.

[0046] When memristor M is memristor M2, port T2 is grounded, port T1 is set to floating state, and voltage V1 is applied to port T3, thereby initializing memristor M to a high impedance state.

[0047] Thirdly, the present invention provides a memristor-based ternary logic gate computing system, comprising: a controller and the ternary logic gate circuit provided in the first aspect of the present invention;

[0048] The controller is used to execute the control method provided in the second aspect of the present invention.

[0049] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0050] 1. This invention provides a three-valued logic gate circuit based on memristors, including two memristors, a fixed resistor, and a multi-valued comparator. The high-resistance, medium-resistance, and low-resistance states of the memristors correspond to different three-valued logic states. The voltage at the input port of the memristors is adjusted, and the voltage V at the first terminal of the resistor is compared using the multi-valued comparator. c With preset reference voltage V r1 and V r2 By establishing the relationship between the input and output, the invention can realize the judgment and output of ternary logic. It can perform ternary logic operations with two inputs, as well as ternary logic operations with one input through floating inputs, thus exhibiting high versatility. At the same time, the invention has a simple structure and does not rely on the memristor resistance state to express the output result. It is not easily constrained by the memristor's switching characteristics and can realize accurate ternary logic gate operations with a simple and relatively universal circuit structure.

[0051] 2. Furthermore, the ternary logic gate circuit provided by this invention, for ternary logic operations with two inputs, derives the relationship between the inputs and outputs of the corresponding ternary logic gate operations, thereby determining a more optimal voltage V. T1 V T2 V r1,2 V r2,2 The value of further improves the accuracy of the calculation results.

[0052] 3. Furthermore, the ternary logic gate circuit provided by this invention, for each ternary logic operation with a single input, derives the relationship between the input and output of the corresponding ternary logic gate operation, thereby determining a more optimal voltage V. T1 V r1,1 V r2,1 The value of further improves the accuracy of the calculation results.

[0053] 4. Furthermore, the resistance value of the ternary logic gate circuit provided by this invention, when used to perform ternary single-input logic operations on the input value a, is: The above settings make the output voltage range symmetrical, which further improves the accuracy of the calculation results.

[0054] 5. Furthermore, in the ternary logic gate circuit provided by this invention, R LRS : R IRS : R HRSThe ratio of 1:10:100 gives the resistance values ​​of the three resistive states better differentiation, further improving the accuracy of the calculation results. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of a memristor provided in an embodiment of the present invention.

[0056] Figure 2 This is a schematic diagram of the structure of a memristor-based ternary logic gate circuit provided in an embodiment of the present invention.

[0057] Figure 3 The diagram illustrates the input-output relationship of a three-valued logic operation with two inputs, as provided in an embodiment of the present invention.

[0058] Figure 4 The diagram illustrates the input and output relationship of a three-valued logic operation with a single input, as provided in an embodiment of the present invention. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0060] To achieve the above objectives, in a first aspect, the present invention provides a three-valued logic gate circuit based on memristors, comprising: a multi-valued comparator, a resistor, and two identical memristors M1 and M2; the positive terminals of memristors M1 and M2 are respectively denoted as port T1 and port T2, and the negative terminals of both are connected to the first terminal of the resistor; the second terminal of the resistor is denoted as port T3.

[0061] A multi-value comparator is used to convert the voltage V at the first terminal of a resistor. c Each with a preset reference voltage V r1 and V r2 The comparison is performed, and the output voltage value corresponding to the result of the ternary logic operation is obtained, thus yielding the result of the ternary logic operation: when V c <V r1 When V is in the range Z1, the multi-value comparator outputs a voltage corresponding to the value Z1; when V is in the range Z1, the multi-value comparator outputs a voltage corresponding to the value Z1. r1 <V c <V r2 The multi-value comparator outputs a voltage corresponding to the value Z2; when V c >V r2 The multi-value comparator outputs a voltage corresponding to the value Z3;

[0062] When the above ternary logic gate circuit is used to perform a ternary logic operation with two inputs on input values ​​a and b: the resistance state of memristor M1 is the resistance state corresponding to value a; the resistance state of memristor M2 is the resistance state corresponding to logic value b; port T1 is used to connect voltage V. T1 Port T T2 Used to connect voltage V T2 Port T3 is used for grounding; V r1 =V r1,2 V r2 =V r2,2 Voltage V T1 V T2 V r1,2 V r2,2 The value of is determined by the three-valued logic operation type with two inputs;

[0063] When the above ternary logic gate is used to perform a ternary logic operation with a single input on the input value a: the resistance state of memristor M1 is the resistance state corresponding to the value a; port T1 is used to connect voltage V. T1 Port T2 is left floating; port T3 is used for grounding; V r1 =V r1,1 V r2 =V r2,1 Voltage V T1 V r1,1 V r2,1 The value of is determined by the three-valued logic operation type with a single input;

[0064] Where a is Z1, Z2, or Z3; b is Z1, Z2, or Z3; the memristor resistance states corresponding to the values ​​Z1, Z2, and Z3 are respectively the high resistance state, intermediate resistance state, and low resistance state of the memristor; the resistance value in the intermediate resistance state is the preset resistance value R. IRS ;R LRS <R IRS <R HRS ;R LRS R is the resistance value of the memristor in its low-resistance state. HRS This represents the resistance value of the memristor when it is in a high-resistance state.

[0065] like Figure 1As shown, the basic structure of a memristor includes an upper electrode, a lower electrode, and the device itself. Memristors can form multiple stable resistance states, thus allowing them to be used as multi-valued devices. This invention utilizes the three-valued characteristics of a memristor, employing its high resistance state (HRS), intermediate resistance state (IRS), and low resistance state (LRS) to implement ternary logic. Preferably, the resistance values ​​of the three states have a certain degree of differentiation. In one optional implementation, R... LRS : R IRS : R HRS The ratio = 1:10:100 ensures good differentiation between the resistance values ​​of the three resistive states. In one specific implementation, R... LRS =1KΩ, R IRS =10KΩ, R HRS =100KΩ.

[0066] In one alternative implementation, for each three-valued logic operation with two inputs, the corresponding voltage V T1 V T2 V r1,2 V r2,2 The values ​​of satisfy the following simultaneously:

[0067]

[0068]

[0069]

[0070] Among them, conductivity value ; The resistance value of memristor M1 when the resistance state is the resistance state corresponding to the value P;

[0071] conductivity ; The resistance of memristor M2 when its resistance state corresponds to the value Q;

[0072] conductivity R is the resistance value;

[0073] and For any pair of input values ​​corresponding to the output value Z1 in the truth table of a three-valued logic operation with two inputs;

[0074] and For any pair of input values ​​corresponding to the output value Z2 in the truth table of a three-valued logic operation with two inputs;

[0075] and For any pair of input values ​​corresponding to the output value Z3 in the truth table of a three-valued logic operation with two inputs.

[0076] In one alternative implementation, for each three-valued logic operation with a single input, the corresponding voltage V T1 '、V r1,1 V r2,1 The values ​​of satisfy the following simultaneously:

[0077]

[0078] Among them, conductivity value ; The resistance value of memristor M1 when the resistance state is the resistance state corresponding to the value P;

[0079] conductivity R is the resistance value;

[0080] and For any pair of input values ​​corresponding to the output value Z1 in the truth table of a three-valued logic operation with a single input;

[0081] and For any pair of input values ​​corresponding to the output value Z2 in the truth table of a three-valued logic operation with a single input;

[0082] and For any pair of input values ​​corresponding to the output value Z3 in the truth table of a three-valued logic operation with a single input.

[0083] Preferably, in an optional implementation, when the above-mentioned ternary logic gate circuit is used to perform a ternary single-input logic operation on the input value a, the resistance value is: .

[0084] It should be noted that Z1, Z2, and Z3 are three different values. Generally, Z1 is 0, Z2 is 1, and Z3 is 2. In addition, Z1 can also be -1, Z2 is 0, and Z3 is 1. It depends on the user's settings, as long as the memristor resistance states corresponding to Z1, Z2, and Z3 are respectively the high resistance state, intermediate resistance state, and low resistance state of the memristor.

[0085] In a second aspect, the present invention provides a control method for a ternary logic gate circuit based on a memristor; wherein the ternary logic gate circuit is the ternary logic gate circuit provided in the first aspect of the present invention;

[0086] When the above-mentioned ternary logic gate circuit is used to perform a ternary logic operation with two inputs on input values ​​a and b: the above control method includes: setting the resistance state of memristor M1 to the resistance state corresponding to value a; setting the resistance state of memristor M2 to the resistance state corresponding to logic value b; and connecting voltage V to port T1. T1 ; at port T T2 Input voltage V T2 Ground port T3; read the result of the ternary logic operation from the output of the multi-value comparator;

[0087] When the above ternary logic gate is used to perform a ternary logic operation with a single input on the input value a: the control method includes: setting the resistance state of memristor M1 to the resistance state corresponding to the value a; and connecting voltage V to port T1. T1 Set port T2 to a floating state; ground port T3; read the result of the three-valued logic operation from the output of the multi-valued comparator.

[0088] The related technical solutions are the same as the ternary logic gate circuits provided in the first aspect of this invention, and will not be described in detail here.

[0089] In one optional implementation, a method for setting the resistance state of memristor M to a resistance state corresponding to the value d includes:

[0090] Initialize memristor M to a high-resistance state; memristor M can be memristor M1 or M2.

[0091] When the value d is Z1 and the memristor M is M1, the port T1 is grounded, the port T2 is set to floating state, and the voltage V1 is connected to the port T3, so that the resistance state of the memristor M is set to the resistance state corresponding to the value d.

[0092] When the value d is Z2 and the memristor M is M1, the voltage V2 is applied to port T1, port T2 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0093] When the value d is Z3 and the memristor M is M1, the voltage V3 is applied to port T1, port T2 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0094] When the value d is Z1 and the memristor M is M2, the port T2 is grounded, the port T1 is set to floating state, and the voltage V1 is connected to the port T3, so that the resistance state of the memristor M is set to the resistance state corresponding to the value d.

[0095] When the value d is Z2 and the memristor M is M2, the voltage V2 is applied to port T2, port T1 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0096] When the value d is Z3 and the memristor M is M2, the voltage V3 is applied to port T2, port T1 is set to floating state, and port T3 is grounded, thereby setting the resistance state of the memristor M to the resistance state corresponding to the value d.

[0097] Where V1 satisfies: V2 satisfies: V2 - V c-HRS >V iset V3 satisfies: V3-V c-HRS >V set ;Voltage Conductivity Conductivity Conductivity R is the resistance value; V set The voltage threshold for a memristor to transition from a high-resistance state to a low-resistance state; voltage V reset The voltage threshold for a memristor to transition from a low-resistance state to a high-resistance state; V iset The resistance value of the memristor is the preset resistance value R. IRS The voltage value corresponding to the time; V reset <V iset <V set .

[0098] In one alternative implementation, the method for initializing the memristor M to a high-resistivity state includes:

[0099] When the memristor M is memristor M1, ground port T1, set port T2 to floating state, and apply voltage V1 to port T3 to initialize memristor M to a high impedance state.

[0100] When memristor M is memristor M2, port T2 is grounded, port T1 is set to floating state, and voltage V1 is applied to port T3, thereby initializing memristor M to a high impedance state.

[0101] Thirdly, the present invention provides a memristor-based ternary logic gate computing system, comprising: a controller and the ternary logic gate circuit provided in the first aspect of the present invention;

[0102] The controller is used to execute the control method provided in the second aspect of the present invention.

[0103] The related technical solutions are the same as the ternary logic gate circuits provided in the first aspect of this invention and the control method provided in the second aspect of this invention, and will not be described in detail here.

[0104] To further illustrate the ternary logic gate circuit and corresponding control method provided by the present invention, the following detailed description is provided in conjunction with specific embodiments:

[0105] For binary logic, to facilitate operation, event states can be expressed mathematically, generally writing "true" as "1" and "false" as "0". For ternary logic, in addition to the two states "true" and "false", there is also an intermediate state. Therefore, when expressing it mathematically, another formal expression is needed. In this embodiment, "2", "1", and "0" are used to represent the three states, namely "true", "intermediate state (neither true nor false)", and "false".

[0106] In this embodiment, the three-valued logic gate circuit based on memristors includes: a multi-valued comparator A, a fixed resistor (resistance value R), and two memristors M1 and M2, as follows: Figure 2 As shown. The upper electrode (positive electrode) of memristor M1 is connected to port T1; the upper electrode (positive electrode) of memristor M2 is connected to port T2. The lower electrodes (negative electrodes) of memristors M1 and M2 are connected to one end of a fixed resistor. The voltage at this node is denoted as V. c The other end of the fixed resistor is connected to port T3. One input of the multi-value comparator A is connected to V. c Connected, the other input is connected to V r (including V) r1 and V r2 Connected to the output terminal, the output voltage is V. o .

[0107] For a three-valued logic operation with two inputs, that is, two input quantities a and b, each input quantity has three possible states, which are "0", "1" and "2" in this embodiment.

[0108] Inputs a and b are mapped to the resistance states of memristors M1 and M2. At this time, the high resistance state of the memristor corresponds to the logic value "0", the intermediate resistance state corresponds to the logic value "1", and the low resistance state corresponds to the logic value "2". For example... Figure 2 As shown, by applying V to control ports T1, T2, and T3 respectively T1 V T2 The voltage value of 0 is used to perform logical operations, and the result is output as V through a multi-value comparator. o The principle of logic operations is that the resistance values ​​of memristors M1 and M2 affect V. c The value of Vr The output result can be obtained by comparison.

[0109] For V c Using Kirchhoff's current law, we can derive the equation:

[0110]

[0111] Simplifying, we get:

[0112]

[0113] The above formula converts resistance into conductance. , , In simplified form, R1, R2, and R correspond to the resistance values ​​of memristor M1, memristor M2, and resistor, respectively.

[0114] Therefore, V c With V r By comparing values ​​in the multi-value comparator A, V can be obtained. o Read the result of the logical calculation. The value to be read has three different states, so V is used to distinguish them. r In fact, two different values ​​V are needed. r1 V r2 (Default V) r1 <V r2 When V c <V r1 When V is zero, the output is recorded as "0"; when ... r1 <V c <V r2 When V is active, the output is recorded as "1"; when V is active... c >V r2 When the time is right, the output is recorded as "2".

[0115] The corresponding logic value is written by setting the resistance state of the memristor; where the high resistance state of the memristor corresponds to the logic value "0", the intermediate resistance state corresponds to the logic value "1", and the low resistance state corresponds to the logic value "2".

[0116] For a three-valued logic operation with a single input, i.e., with one input value 'a',

[0117] When ports T1 or T2 are floating, all other conditions remain unchanged, and the circuit forms a single-input ternary logic gate. Taking port T2 as an example, the circuit becomes a single-input ternary logic gate, and its common-point voltage... To optimize the threshold for comparison in a multi-value comparator, the following equation should be satisfied:

[0118]

[0119] in, This is the voltage value of the common-point voltage when memristor M1 is in a low-resistance state; This is the voltage value of the common-point voltage when memristor M1 is in the intermediate resistance state; This is the voltage value of the common-point voltage when memristor M1 is in a high-resistance state. Substituting this into the formula for calculating the common-point voltage, we can obtain:

[0120]

[0121] The above settings make the output voltage range symmetrical, which further improves the accuracy of the calculation results.

[0122] The optimal resistance value R of a fixed resistor can also be calculated using the same principle for a three-valued logic operation with two inputs.

[0123] The following details specific three-valued logical operations:

[0124] Example 1

[0125] The three-valued logic operation type involved in this embodiment is the three-valued substantial implication (IMPLY) logic operation, which is a three-valued logic operation type with two inputs.

[0126] A substantial implication proposition is false only when the antecedent is true and the consequent is false; otherwise, it is true. As shown in Table 1, there are four cases in a binary two-input substantial implication logic. The output is "0" only when a is "1" and b is "0", and "1" in all other cases. As shown in Table 2, there are nine possible cases for the three-valued two-input substantial implication logic. When a is "0" and b is "0", the output is "2"; when a is "0" and b is "1", the output is "2"; when a is "0" and b is "2", the output is "2"; when a is "1" and b is "0", the output is "1"; when a is "1" and b is "1", the output is "2"; when a is "1" and b is "2", the output is "2"; when a is "2" and b is "0", the output is "0"; when a is "2" and b is "1", the output is "1"; when a is "2" and b is "2", the output is "2".

[0127]

[0128]

[0129] The reconfigurable ternary logic gate circuit based on memristors provided in this invention can be used to implement ternary two-input essential implication logic. The specific operation is as follows:

[0130] Initialize memristors: Initialize memristors M1 and M2, ground terminals T1 and T2 (gnd), and connect terminal T3 to voltage V1, thus making the voltage difference |V| across memristors M1 and M2 equal. c -V1|greater than|V reset At this point, memristors M1 and M2 are set to a high-impedance state of "0".

[0131] Setting Input Quantities: Input quantities a and b are manipulated through memristors M1 and M2 to match their resistance states. The specific steps are as follows:

[0132] When the value of input quantity 'a' is "0", T1 port is grounded (gnd), T2 port is left floating, and T3 port is connected to V1, thereby making the voltage difference |V1 across memristor M1 equal to the voltage across the memristor M1. c -V1|greater than|V reset At this point, memristor M1 is set to a high-impedance state "0";

[0133] When the value of input quantity a is "1", connect port T1 to voltage V2, leave port T2 floating, and ground port T3, thereby making the voltage difference V2-V across memristor M1 equal to the voltage across the memristor M1. c Greater than V iset At this time, memristor M1 is set to the intermediate resistance state "1";

[0134] When the input value 'a' is "2", connect port T1 to voltage V3, leave port T2 floating, and ground port T3. This will cause the voltage difference across memristor M1 to be V3 - V. c Greater than V set At this time, memristor M1 is set to the low-resistance state "2".

[0135] When the value of input quantity b is "0", the T2 port is grounded, the T1 port is left floating, and the T3 port is connected to voltage V1, thus making the voltage difference |V1| across the memristor M2 equal to the voltage across the memristor M2. c -V1|greater than|V reset At this point, memristor M2 is set to a high-resistance state "0";

[0136] When the value of input quantity b is "1", the voltage V2 is connected to port T2, port T1 is left floating, and port T3 is grounded, thus making the voltage difference V2-V across memristor M2 equal to the voltage across the memristor M2. c Greater than V iset At this time, memristor M2 is set to the intermediate resistance state "1";

[0137] When the value of input quantity b is "2", connect port T2 to voltage V3, leave port T1 floating, and ground port T3. This will cause the voltage difference V3 - V across memristor M2 to be equal. c Greater than Vset At this point, memristor M2 is set to a low-resistance state "2".

[0138] Perform the following logical operation: Connect voltage V to port T1. T1 At port T T2 Input voltage V T2 Grounding the T3 port will cause the voltage V at the lower pole of the memristor to change depending on the resistance state of the memristor. c different.

[0139] Compare and obtain the result: The multi-value comparator compares the voltage value V. c and reference voltage V r The final result is obtained based on the different reference voltages. When V c <V r1 When V is in the range of 0, the multi-value comparator outputs a voltage corresponding to the logic value "0"; when V is in the range of 1 ...". r1 <V c <V r2 The multi-value comparator outputs a voltage corresponding to the logic value "1"; when V c >V r2 The multi-value comparator outputs a voltage corresponding to the logic value "2"; at this time, V r1 =V r1,2 V r2 =V r2,2 ;

[0140] Where V1 satisfies: V2 satisfies: V2 - V c-HRS >V iset V3 satisfies: V3-V c-HRS >V set ;Voltage Conductivity Conductivity Conductivity R is the resistance value; V set The voltage threshold for a memristor to transition from a high-resistance state to a low-resistance state; voltage V reset The voltage threshold for a memristor to transition from a low-resistance state to a high-resistance state; V iset The resistance value of the memristor is the preset resistance value R. IRS The voltage value corresponding to the time; V reset <V iset <V set .

[0141] It should be noted that for each type of three-valued logic operation with two inputs, the corresponding voltage V... T1 V T2 V r1,2 V r2,2 The values ​​of satisfy the first set of inequalities:

[0142]

[0143]

[0144]

[0145] Among them, conductivity value ; The resistance value of memristor M1 when the resistance state is the resistance state corresponding to the value P;

[0146] conductivity ; The resistance of memristor M2 when its resistance state corresponds to the value Q;

[0147] conductivity R is the resistance value;

[0148] and For any pair of input values ​​corresponding to the output value Z1 in the truth table of a three-valued logic operation with two inputs;

[0149] and For any pair of input values ​​corresponding to the output value Z2 in the truth table of a three-valued logic operation with two inputs;

[0150] and For any pair of input values ​​corresponding to the output value Z3 in the truth table of a three-valued logic operation with two inputs.

[0151] It can be observed that the judgment of a three-valued logic operation with two inputs can be viewed as two straight lines. For example... Figure 3 As shown, the curve that is ,curve that is .

[0152] For the three-valued substantial implication logic operation in this embodiment, the corresponding truth table for the three-valued logic operation is Table 2 above. Based on the first set of inequalities above, the voltage V corresponding to the three-valued substantial implication logic operation can be determined. T1 V T2 V r1,2 V r2,2 The value of .

[0153] It should be noted that the three-valued substantial implication logic implemented in this embodiment is complete and can constitute all three-valued logic gates, thus having high scalability.

[0154] Example 2

[0155] The three-valued logic operation type involved in this embodiment is the three-valued maximum gate logic operation, which is a three-valued logic operation type with two inputs.

[0156] The specific operation is basically the same as in Example 1, except that the truth table of the three-valued logic operation is different. The truth table of the three-valued logic operation in this example is the truth table of the three-valued maximum gate logic operation, as shown in Table 3.

[0157]

[0158] Based on the first set of inequalities above, the voltage V corresponding to the ternary maximum gate logic operation can be determined. T1 V T2 V r1,2 V r2,2 The value of .

[0159] Example 3

[0160] The three-valued logic operation type involved in this embodiment is the three-valued non-maximum gate logic operation, which is a three-valued logic operation type with two inputs.

[0161] The specific operation is basically the same as in Example 1, except that the truth table of the three-valued logic operation is different. The truth table of the three-valued logic operation in this example is the truth table of the three-valued non-maximum gate logic operation, as shown in Table 4.

[0162]

[0163] Based on the first set of inequalities above, the voltage V corresponding to the logic operation of the ternary non-maximum gate can be determined. T1 V T2 V r1,2 V r2,2 The value of .

[0164] Example 4

[0165] The three-valued logic operation type involved in this embodiment is the three-valued inversion (INV) logic operation, which is a three-valued logic operation type with a single input.

[0166] In classic binary logic, negation means that when the input is "true", the output is "false"; and when the input is "false", the output is "true". Mathematically, when the input is "1", the output is "0"; and when the input is "0", the output is "1". However, as shown in Figure 5, in ternary negation logic, when the input is "0", the output is "2"; when the input is "1", the output is "1"; and when the input is "2", the output is "0".

[0167]

[0168] In fact, the ternary negation logic is essentially contained within the substantive implication logic. When one input of the ternary two-input substantive implication logic is fixed at "0", the output is the negation of the other input. However, the ternary negation logic operation can also be implemented at the circuit level using the memristor-based ternary logic gate circuit provided by this invention. The specific operation is as follows:

[0169] Initialize memristors: Initialize memristor M1 by grounding port T1, setting port T2 to a floating state, and setting the voltage V1 at port T3, thereby making the voltage difference |V1| across memristors M1 and M2 equal. c -V1|greater than|V reset At this point, memristor M1 is set to a high-impedance state "0".

[0170] Set the input quantity: The input quantity a is adjusted by operating the memristor M1 so that the resistance state of the memristor matches the input quantity.

[0171] When the value of input quantity a is "0", T1 port is grounded, T2 port is set to floating state, and T3 port is connected to voltage V1, thereby making the voltage difference |V1 across memristor M1 equal to the voltage across the memristor M1. c -V1|greater than|V reset At this point, memristor M1 is set to a high-impedance state "0";

[0172] When the input value 'a' is "1", the T1 port is connected to voltage V2, the T2 port is left floating, and the T3 port is grounded. This results in a voltage difference V2 - V across the memristor M1. c Greater than V iset At this time, memristor M1 is set to the intermediate resistance state "1";

[0173] When the input value 'a' is "2", connect port T1 to voltage V3, set port T2 to a floating state, and ground port T3, thereby making the voltage difference V3-V across memristor M1 equal to the voltage across the memristor M1. c Greater than V set At this time, memristor M1 is set to the low-resistance state "2".

[0174] Perform the following logical operation: Connect voltage V to port T1. T1 Setting port T2 to a floating state and grounding port T3 will cause the voltage V at the lower pole of the memristor to change depending on the resistance state of the memristor. c different.

[0175] Compare and obtain the result: The multi-value comparator compares the voltage value V. c and reference voltage V rThe final result is obtained based on the different reference voltages. When V c <V r1 When V is in the range of 0, the multi-value comparator outputs a voltage corresponding to the logic value "0"; when V is in the range of 1 ...". r1 <V c <V r2 The multi-value comparator outputs a voltage corresponding to the logic value "1"; when V c >V r2 The multi-value comparator outputs a voltage corresponding to the logic value "2"; at this time, V r1 =V r1,1 V r2 =V r2,1 ;

[0176] Where V1 satisfies: V2 satisfies: V2 - V c-HRS >V iset V3 satisfies: V3-V c-HRS >V set ;Voltage Conductivity Conductivity Conductivity R is the resistance value; V set The voltage threshold for a memristor to transition from a high-resistance state to a low-resistance state; voltage V reset The voltage threshold for a memristor to transition from a low-resistance state to a high-resistance state; V iset The resistance value of the memristor is the preset resistance value R. IRS The voltage value corresponding to the time; V reset <V iset <V set .

[0177] It should be noted that for each type of three-valued logic operation with a single input, the corresponding voltage V... T1 '、V r1,1 V r2,1 The values ​​of satisfy the second set of inequalities:

[0178]

[0179] Among them, conductivity value ; The resistance value of memristor M1 when the resistance state is the resistance state corresponding to the value P;

[0180] conductivity R is the resistance value;

[0181] and For any pair of input values ​​corresponding to the output value Z1 in the truth table of a three-valued logic operation with a single input;

[0182] and For any pair of input values ​​corresponding to the output value Z2 in the truth table of a three-valued logic operation with a single input;

[0183] and For any pair of input values ​​corresponding to the output value Z3 in the truth table of a three-valued logic operation with a single input.

[0184] It can be observed that the judgment of a three-valued logic operation with a single input can be viewed as two straight lines. For example... Figure 4 As shown, the curve that is ,curve that is .

[0185] For the ternary negation gate logic operation in this embodiment, the corresponding truth table for the ternary logic operation is shown in Table 5 above. Based on the second set of inequalities above, the voltage V corresponding to the ternary negation gate logic operation can be determined. T1 '、V r1,1 V r2,1 The value of .

[0186] Example 5

[0187] The three-valued logic operation type involved in this embodiment is the three-valued copy gate logic operation (i.e., the three-valued COPY logic operation, where the output is the same as the input). This operation is a three-valued logic operation type with a single input.

[0188] The specific operation is basically the same as in Example 1, except that the truth table of the three-valued logic operation is different. The truth table of the three-valued logic operation in this example is the truth table of the three-valued copy gate logic operation, as shown in Table 6.

[0189]

[0190] Based on the second set of inequalities above, the voltage V corresponding to the logic operation of the ternary copy gate can be determined. T1 '、V r1,1 V r2,1 The value of .

[0191] Example 6

[0192] The three-valued logic operation type involved in this embodiment is a three-valued true logic operation (the output is always 2 regardless of the number of inputs), which is a three-valued logic operation type with a single input.

[0193] The specific operation is basically the same as in Example 1, except that the truth table of the three-valued logic operation is different. The truth table of the three-valued logic operation in this example is the truth table of the three-valued true logic operation, as shown in Table 7.

[0194]

[0195] Based on the second set of inequalities mentioned above, the voltage V corresponding to the ternary true logic operation can be determined. T1 '、V r1,1 V r2,1 The value of .

[0196] Example 7

[0197] The three-valued logic operation type involved in this embodiment is a three-valued pseudo logic operation (the output is 0 regardless of the number of inputs), which is a three-valued logic operation type with a single input.

[0198] The specific operation is basically the same as in Example 1, except that the truth table of the three-valued logic operation is different. The truth table of the three-valued logic operation in this example is a three-valued pseudo logic operation truth table, as shown in Table 8.

[0199]

[0200] It should be noted that the implementation methods of other three-valued logic operation types with two inputs are similar to those in Examples 1-3, except for the truth table, and will not be described in detail here. The implementation methods of other three-valued logic operation types with one input are similar to those in Examples 4-7, except for the truth table, and will not be described in detail here.

[0201] Therefore, it can be deduced that different truth tables can be derived based on the different positions and slopes of the two curves, thus enabling the implementation of the three-valued logic operation in one step. A total of 157 three-valued logic gates can be implemented in one step, which will not be elaborated upon here.

[0202] Furthermore, the three-valued substantial implication logic implemented in the embodiments of the present invention is itself complete, that is, it can constitute all three-valued logic gates.

[0203] In summary, the memristor-based ternary logic gate circuit provided by this invention includes two memristors, a fixed resistor, and a multi-value comparator. The high-resistance, medium-resistance, and low-resistance states of the memristors correspond to different ternary logic states. The circuit is controlled by adjusting the input port voltage of the memristors and measuring the common-point voltage V. c With preset reference voltage V r1 and V r2This invention establishes a relationship between three-valued logic gates to achieve judgment and output. The proposed structure can implement three-valued logic operations with two inputs, as well as single-input three-valued logic operations via floating inputs. Using this circuit structure, up to 157 three-valued logic gate operations can be implemented in one step, exhibiting high versatility and scalability, and is particularly suitable for constructing complete three-valued intrinsic implication logic systems. This invention combines the polymorphic characteristics of memristors with the advantages of in-memory computing, providing an efficient, low-power, and structurally simple implementation scheme for multi-valued logic operations, with broad application prospects.

[0204] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memristor-based ternary logic gate circuit, characterized by, Comprising: a multi-value comparator, a resistor and two identical memristors M1, M2; the positive poles of the memristors M1, M2 are marked as ports T1 and T2 respectively, and the negative poles are both connected to the first end of the resistor; the second end of the resistor is marked as port T3; The multi-value comparator is used for comparing the voltage V c at the first end of the resistor with preset reference voltages V r1 and V r2 respectively, outputting voltage values corresponding to three-value logic operation results, and obtaining the three-value logic operation results: when V c <V r1 , the multi-value comparator outputs a voltage corresponding to a value Z1; when V r1 <V c <V r2 , the multi-value comparator outputs a voltage corresponding to a value Z2; when V c >V r2 , the multi-value comparator outputs a voltage corresponding to a value Z3. When the ternary logic gate circuit is used to perform a ternary logic operation with two inputs on input values a, b: the resistance state of the memristor M1 is a resistance state corresponding to the value a; the resistance state of the memristor M2 is a resistance state corresponding to the logic value b; the port T1 is used to access a voltage V T1 , the port T2 is used to access a voltage V T2 , and the port T3 is used to ground; V r1 = V r1,2 , V r2 = V r2,2 ; the values of the voltages V T1 , V T2 , V r1,2 , V r2,2 are determined by the type of ternary logic operation with two inputs; When the ternary logic gate circuit is used to perform a ternary logic operation with single input on an input value a: the resistance state of the memristor M1 is a resistance state corresponding to the value a; the port T1 is used to access a voltage V T1 , the port T2 is in a suspended state; the port T3 is used to ground; V r1 = V r1,1 , V r2 = V r2,1 ; the values of the voltages V T1 , V r1,1 , V r2,1 are determined by the type of ternary logic operation with single input. Wherein, a is Z1 or Z2 or Z3; b is Z1 or Z2 or Z3; the resistance state corresponding to the value Z1, Z2, Z3 of the memristor in turn is high resistance state, intermediate resistance state and low resistance state; the resistance value in the intermediate resistance state is a preset resistance value R IRS ; R LRS ; R IRS ; R HRS ; R LRS is the resistance value of the memristor in the low resistance state; R HRS is the resistance value of the memristor in the high resistance state.

2. The ternary logic gate circuit according to claim 1, wherein For each kind of three-valued logic operation with two inputs, the corresponding voltage V T1 , V T2 , V r1,2 , V r2,2 takes values that satisfy simultaneously: wherein the conductance value ; is the resistance value of the memristor M1 when the resistance state of the memristor M1 is the resistance state corresponding to the value P. conductance value ; the resistance of the memristor M2 when the resistance state of the memristor M2 is the resistance state corresponding to the value Q; conductance value ; R is the resistance value of the resistance; and any pair of input values corresponding to the output value Z1 in the truth table of the three-valued logic operation with two inputs; and is any pair of input values corresponding to the output value Z2 in the truth table of the ternary logic operation with two inputs; and corresponding to any pair of input values in the truth table of the ternary logic operation with two inputs whose output value is Z3.

3. The ternary logic gate circuit of claim 1, wherein, For each kind of three-valued logic operation with single input, the corresponding voltage V T1 ', V r1,1 ', V r2,1 takes the value that satisfies the following conditions simultaneously: wherein the conductance value ; is the resistance value of the memristor M1 when the resistance state of the memristor M1 is the resistance state corresponding to the value P. conductance value ; R is the resistance value of the resistance; and any pair of input values corresponding to the output value Z1 in the truth table of the ternary logic operation with a single input and any pair of input values corresponding to the output value Z2 in the truth table of the ternary logic operation with a single input; and is any pair of input values corresponding to the output value Z3 in the truth table of the ternary logic operation with a single input.

4. The ternary logic gate circuit of claim 1, wherein, When the ternary logic gate circuit is used to perform ternary single-input logic operation on an input value a, the resistance of the resistor is: .

5. The ternary logic gate circuit according to any one of claims 1 to 4, wherein R LRS : R IRS : R HRS =1: 10:

100.

6. The ternary logic gate circuit according to any one of claims 1 to 4, wherein value Z1 is 0; value Z2 is 1; value Z3 is 2.

7. A control method of a ternary logic gate circuit based on a memristor, characterized by, The ternary logic gate circuit is the ternary logic gate circuit of any one of claims 1-6; When the ternary logic gate circuit is used to perform a ternary logic operation with two inputs a, b: the control method comprises: setting the resistance state of the memristor M1 to the resistance state corresponding to the value a; setting the resistance state of the memristor M2 to the resistance state corresponding to the logic value b; accessing the voltage V T1 at the port T1; accessing the voltage V T2 at the port T2; grounding the port T3; reading the ternary logic operation result at the output of the multi-value comparator; When the ternary logic gate circuit is used to perform a ternary logic operation with a single input on an input value a: the control method comprises: setting the resistance state of the memristor M1 to a resistance state corresponding to the value a; connecting the port T1 to the voltage V T1 ; setting the port T2 to a floating state; grounding the port T3; reading the ternary logic operation result at the output of the multi-value comparator.

8. The control method of the ternary logic gate circuit according to claim 7, characterized by, A method for setting the resistance state of a memristor M to a resistance state corresponding to a value d, comprising: initializing the memristor M to a high resistance state; the memristor M is a memristor M1 or M2; when the value d is value Z1 and the memristor M is the memristor M1, grounding the port T1, setting the port T2 to a suspended state, and connecting the port T3 to a voltage V1, thereby setting the resistance state of the memristor M to a resistance state corresponding to the value d; when the value d is value Z2 and the memristor M is the memristor M1, connecting the port T1 to a voltage V2, setting the port T2 to a suspended state, and grounding the port T3, thereby setting the resistance state of the memristor M to a resistance state corresponding to the value d; when the value d is value Z3 and the memristor M is the memristor M1, connecting the port T1 to a voltage V3, setting the port T2 to a suspended state, and grounding the port T3, thereby setting the resistance state of the memristor M to a resistance state corresponding to the value d; when the value d is value Z1 and the memristor M is the memristor M2, grounding the port T2, setting the port T1 to a suspended state, and connecting the port T3 to a voltage V1, thereby setting the resistance state of the memristor M to a resistance state corresponding to the value d; when the value d is value Z2 and the memristor M is the memristor M2, connecting the port T2 to a voltage V2, setting the port T1 to a suspended state, and grounding the port T3, thereby setting the resistance state of the memristor M to a resistance state corresponding to the value d; when the value d is value Z3 and the memristor M is the memristor M2, connecting the port T2 to a voltage V3, setting the port T1 to a suspended state, and grounding the port T3, thereby setting the resistance state of the memristor M to a resistance state corresponding to the value d; V1 satisfies: V2 satisfies: V2- V c-HRS > V iset V3 satisfies: V3- V c-HRS > V set ; voltage ; conductance value ; conductance value ; conductance value ; R is the resistance value of the resistance; V set is the voltage threshold value at which the memristor changes from a high resistance state to a low resistance state; voltage V reset is the voltage threshold value at which the memristor changes from a low resistance state to a high resistance state; V iset is the voltage value corresponding to the resistance value of the memristor being a preset resistance value R IRS ; V reset < V iset < V set .

9. The control method of the ternary logic gate circuit according to claim 8, characterized by, The method for initializing the memristor M to a high resistance state comprises: when the memristor M is the memristor M1, grounding the port T1, setting the port T2 to a suspended state, and connecting the port T3 to a voltage V1, thereby initializing the memristor M to a high resistance state; when the memristor M is the memristor M2, grounding the port T2, setting the port T1 to a suspended state, and connecting the port T3 to a voltage V1, thereby initializing the memristor M to a high resistance state.

10. A memristor-based ternary logic gate computing system, comprising: Comprising: a controller and the ternary logic gate circuit of any one of claims 1-6; wherein the controller is configured to perform the control method of any one of claims 7-9.

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