A method for measuring the thickness of a gate oxide layer

Abstract

This application relates to the field of semiconductor technology and provides a method for measuring the thickness of a gate oxide layer. The method includes: preparing an ultrathin TEM sample, the ultrathin TEM sample comprising, from bottom to top, a substrate layer, a gate oxide layer, and other material layers; placing the ultrathin TEM sample in a TEM microscopy area and setting the aperture to its maximum; adjusting the tilt angle of the ultrathin TEM sample at low magnification until the contrast of the substrate layer becomes dark to align the zone axis; then, while maintaining the maximum aperture, adjusting the magnification and fine-tuning the focus until the gate oxide layer can be clearly observed; taking a photograph of the ultrathin TEM sample to obtain a TEM image; and measuring the thickness of the gate oxide layer based on the TEM image. This application not only reduces the risk of radiation damage or secondary deformation of the ultrathin TEM sample, thereby improving the measurement accuracy and precision of the gate oxide layer, but also saves imaging time, which is beneficial for improving measurement efficiency and reducing measurement costs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a method for measuring gate oxide layer thickness. BACKGROUND

[0002] The gate oxide layer is a core insulating layer in a semiconductor device (such as a MOSFET (metal oxide semiconductor field effect transistor), a memory, etc.), and its thickness directly affects the threshold voltage, leakage current and other electrical properties of the device. Therefore, accurately characterizing the gate oxide layer thickness is a key link in the research and development and quality control of semiconductor processes.

[0003] The transmission electron microscope (TEM) is one of the most mainstream means for characterizing the gate oxide layer thickness of a semiconductor device. In the related art, the method for characterizing the gate oxide layer thickness by using the TEM usually needs to enter the diffraction mode to adjust the crystal axis on the silicon substrate near the gate oxide layer, and to judge whether the crystal axis is adjusted by using the Kish line. However, in the diffraction mode, the electron beam spot is very small, and in the process of adjusting the crystal axis, the target position is easily deviated, resulting in that the crystal axis is not adjusted, the sample appears to be superimposed, and the measurement accuracy and accuracy of the gate oxide layer thickness are affected. Secondly, since the electron beam converges very small and has high energy, the TEM sample (especially the ultra-thin TEM sample (thickness is about 20 nm) itself has a certain deformation) is easily damaged by irradiation or deformed again. In addition, since the ultra-thin sample has a certain degree of deformation, the crystal axes at different positions are not the same, and need to be adjusted multiple times, which increases the photographing time and the risk of irradiation damage.

[0004] It can be seen that the conventional method for characterizing the gate oxide layer thickness by using the TEM easily causes the sample to be damaged by irradiation or deformed again, thereby affecting the measurement accuracy and accuracy of the gate oxide layer thickness, and the measurement efficiency is low and the measurement cost is high. SUMMARY

[0005] Therefore, the present application provides a method for measuring gate oxide layer thickness, which aims to solve the problem that the conventional method for characterizing the gate oxide layer thickness by using the TEM easily causes the TEM sample to be damaged by irradiation or deformed again, thereby affecting the measurement accuracy and accuracy of the gate oxide layer thickness, and the measurement efficiency is low and the measurement cost is high.

[0006] To achieve the above-mentioned application purposes, the embodiments of the present application provide a method for measuring gate oxide layer thickness, comprising:

[0007] An ultra-thin TEM sample is prepared, and the ultra-thin TEM sample comprises a substrate layer, a gate oxide layer and other material layers from bottom to top in sequence;

[0008] Place the ultrathin TEM sample in the TEM inspection area and set the aperture to its maximum. Adjust the tilt angle of the ultrathin TEM sample at low magnification until the contrast of the substrate layer turns black to correct the zone axis. Then, while keeping the aperture at its maximum, adjust the magnification and fine-tune the focal length until the gate oxide layer can be clearly observed. Take a picture of the ultrathin TEM sample to obtain a TEM image.

[0009] The thickness of the gate oxide layer was measured based on TEM images.

[0010] Compared with the prior art, the beneficial effects of this application include at least the following:

[0011] The technical solution provided in this embodiment allows for TEM microscopy inspection of ultrathin TEM samples without entering diffraction mode. Instead, the aperture is set to maximum, and the tilt angle of the ultrathin TEM sample is adjusted directly at low magnification until the contrast of the substrate layer turns black. By observing the contrast of the substrate layer, it is determined whether the zone axis is aligned. This not only reduces the risk of irradiation damage or secondary deformation of ultrathin TEM samples, thereby improving the measurement accuracy and precision of the gate oxide layer of ultrathin TEM samples, but also saves imaging time, which is beneficial for improving measurement efficiency and reducing measurement costs. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of an ultrathin TEM sample provided in an embodiment of this application;

[0014] Figure 2 This is a schematic diagram showing the blackening of the substrate layer in an ultrathin TEM sample provided in an embodiment of this application at a magnification of 4600 x.

[0015] Figure 3 This is a schematic diagram showing the blackening of the substrate layer in an ultrathin TEM sample provided in an embodiment of this application at a magnification of 8600 x.

[0016] Figure 4 This is a schematic diagram showing the blackening of the substrate layer in an ultrathin TEM sample provided in an embodiment of this application at a magnification of 94000 x.

[0017] Figure 5 This is a schematic diagram showing the blackening of the substrate layer in an ultrathin TEM sample provided in an embodiment of this application at a magnification of 150 kx;

[0018] Figure 6 This is a schematic diagram of an ultrathin TEM sample provided in an embodiment of this application when the substrate layer turns white at a magnification of 630 kx;

[0019] Figure 7 This is a schematic diagram of the position of the zone axis of an ultrathin TEM sample provided in an embodiment of this application when the substrate turns white at a magnification of 630 kx;

[0020] Figure 8 This is a schematic diagram of the substrate layer of an ultrathin TEM sample provided in an embodiment of this application when it turns black at a magnification of 630 kx;

[0021] Figure 9 This is a schematic diagram of the position of the zone axis of an ultrathin TEM sample provided in an embodiment of this application when the substrate turns black at a magnification of 630 kx;

[0022] Figure 10 This is a schematic diagram of the target region of a semiconductor device provided in an embodiment of this application;

[0023] Figure 11 This is a schematic diagram of the process before trenching is performed on both sides of the target area of ​​a semiconductor device, according to an embodiment of this application.

[0024] Figure 12 This is a schematic diagram of trenching on both sides of a target area of ​​a semiconductor device according to an embodiment of this application;

[0025] Figure 13 This is a schematic diagram of the structure of the thin sheet before the copper mesh is transferred, according to an embodiment of this application;

[0026] Figure 14 This is a schematic diagram of the free end of a thin sheet welded using a nanorobot, provided in one embodiment of this application;

[0027] Figure 15 This is a schematic diagram of welding a thin sheet to the edge of a copper mesh according to an embodiment of this application;

[0028] Figure 16 This is a schematic diagram of the final ultrathin TEM sample extracted according to an embodiment of this application;

[0029] Figure 17 These are TEM images of ultrathin TEM samples obtained using the measurement methods provided in the embodiments of this application;

[0030] Figure 18 These are TEM images of ultrathin TEM samples obtained using traditional measurement methods. Detailed Implementation

[0031] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are only for explaining this application, but the implementation of this application is not limited thereto.

[0032] TEM uses a high-energy electron beam to penetrate the sample and form an image through the interaction of electrons and atoms, allowing direct observation of the cross-sectional morphology of the gate oxide layer and thus measurement of its thickness. For nanoscale oxide layers, high-resolution TEM (HR TEM) or scanning transmission electron microscopy (STEM) is required, with a resolution of up to 0.1 nm and extremely high precision, suitable for precise measurements at critical process nodes.

[0033] For ultrathin TEM samples (thickness ≤ 20 nm), the traditional method for characterizing the gate oxide layer thickness using TEM involves narrowing the aperture on the substrate and then adjusting the zone axis using the Kikuchi line in diffraction mode. However, this method has two significant drawbacks: First, due to the thinness of the sample and the small aperture, prolonged zone axis adjustment in diffraction mode can easily damage the sample structure. Second, because the sample is so thin, it will naturally exhibit some deformation. After adjusting the zone axis at one location, the zone axis in other locations may still be misaligned. Direct imaging in this case will affect image quality and measurement accuracy. To obtain a clear image of the structure, the zone axis must be readjusted at the target location (adjusting the zone axis at high magnification still requires entering diffraction mode, where the probability of diffraction spots damaging the sample is even greater). This is not only time-consuming but also increases the risk of irradiation damage to the structure, thus affecting the accuracy and precision of measuring the gate oxide layer thickness of ultrathin TEM samples.

[0034] It is evident that the traditional method of characterizing the gate oxide layer thickness using TEM is prone to irradiation damage or secondary deformation of the TEM sample, which affects the measurement accuracy and precision of the gate oxide layer thickness. Furthermore, the measurement efficiency is low and the measurement cost is high.

[0035] Based on this, this application provides a method for measuring the thickness of the gate oxide layer. Utilizing the principle of electron diffraction contrast, when performing TEM microscopy on ultrathin TEM samples, it is not necessary to enter diffraction mode. Instead, the aperture is set to its maximum (i.e., without reducing the aperture or entering diffraction mode), and the tilt angle of the ultrathin TEM sample is directly adjusted at low magnification until the contrast of the substrate layer turns black. By observing the contrast of the substrate layer, it is determined whether the zone axis is aligned. This not only reduces the risk of irradiation damage or secondary deformation of ultrathin TEM samples, thereby improving the measurement accuracy and precision of the gate oxide layer of ultrathin TEM samples, but also saves imaging time, which is beneficial to improving measurement efficiency and reducing measurement costs.

[0036] Electron diffraction contrast principle: When an electron beam is incident on a crystal in the opposite direction to the zone axis, if the zone axis is strictly parallel to the electron beam direction (i.e., the more positive the zone axis), according to the Bragg diffraction condition, the crystal planes that meet the condition will produce strong diffraction. At this time, a large number of electrons will be diffracted to other directions, and the number of electrons that pass through the sample and reach the detector will decrease. The brightness of the silicon substrate (substrate layer) in a TEM image depends on the dose of incident electrons that pass through the sample and reach the detector. The more electrons that pass through, the brighter the image; the fewer electrons that pass through, the darker the image. Because the more positive the zone axis, the stronger the electron diffraction, and the fewer electrons that pass through the substrate and reach the detector, the darker the silicon substrate appears in the TEM image.

[0037] This application provides a method for measuring the thickness of a gate oxide layer, including the following steps:

[0038] S1. Prepare ultrathin TEM samples.

[0039] like Figure 1 As shown, the ultrathin TEM sample prepared in this embodiment of the application includes, from bottom to top, a substrate layer 101, a gate oxide layer 102, and other material layers 103. The substrate layer 101 is typically a silicon substrate. The other material layers 103 typically refer to at least a portion of the metal material layer and / or encapsulation material layer formed on the gate oxide layer 102.

[0040] S2. Place the ultrathin TEM sample in the TEM inspection area and set the aperture to its maximum. Adjust the tilt angle of the ultrathin TEM sample at low magnification until the contrast of the substrate layer turns black to correct the zone axis. Then, while keeping the aperture at its maximum, adjust the magnification and fine-tune the focus until the gate oxide layer can be clearly observed. Take a picture of the ultrathin TEM sample to obtain a TEM image.

[0041] As an example, the tilt angle of the ultrathin TEM sample is adjusted by tilting the double tilt bar loaded with the ultrathin TEM sample in the left-right and up-down directions until the contrast of the substrate layer of the ultrathin TEM sample turns black.

[0042] S3. Measure the thickness of the gate oxide layer based on the TEM image.

[0043] The technical solution provided in this embodiment allows for TEM microscopy inspection of ultrathin TEM samples without entering diffraction mode. Instead, the aperture is set to maximum, and the tilt angle of the ultrathin TEM sample is adjusted directly at low magnification until the contrast of the substrate layer turns black. By observing the contrast of the substrate layer, it is determined whether the zone axis is aligned. This not only reduces the risk of irradiation damage or secondary deformation of ultrathin TEM samples, thereby improving the measurement accuracy and precision of the gate oxide layer of ultrathin TEM samples, but also saves imaging time, which is beneficial for improving measurement efficiency and reducing measurement costs.

[0044] In some implementations, the tilt angle refers to the α tilt and β tilt angles of the dual tilt sample bar of the scanning transmission electron microscope (model Talos F200E), that is, the tilt angle of the sample around the axes (X-axis and Y-axis). The adjustment range of the α angle is generally ±25° of a first reference angle; the adjustment range of the β angle is ±25° of a second reference angle.

[0045] The first and second reference angles can be flexibly set according to the actual situation.

[0046] As an example, the specific procedure for photographing ultrathin TEM samples using TEM is as follows:

[0047] The first step is to place the prepared ultrathin TEM sample in the TEM inspection area and set the aperture to its maximum. Then, at low magnification (approximately 3300 x-4600 x), adjust the Z-axis to bring the object distance within a reasonable range. Next, rotate the "focus button" to further adjust the image distance to achieve a clear image. Afterward, at this low magnification, adjust the tilt angle of the ultrathin TEM sample (α angle adjustment range is ±35° of the first reference angle, β angle adjustment range is ±30° of the second reference angle), while simultaneously observing the contrast change of the substrate layer 101 (e.g., a silicon substrate). When the contrast of the substrate layer near the gate of the ultrathin TEM sample becomes darker (e.g., when the contrast changes to a silicon substrate), the contrast change is observed. Figure 2 (As shown in the red box in the image), then fine-tune the "focus button" to adjust the zone axis, and you can take a picture (exposure time is 50ms, current is 0.3nA) to obtain the first TEM image (TEM image at a magnification of 4600 x).

[0048] The second step is to adjust the TEM magnification to 8600 x ~ 150 kx, keeping the aperture at its maximum to avoid irradiation damage to the structure of the ultrathin TEM sample. If the contrast of the substrate layer of the ultrathin TEM sample does not change significantly, you can directly take a picture after adjusting the focus button to obtain the second TEM image. If the contrast of the substrate layer of the ultrathin TEM sample changes significantly, you can repeat the first step above. When you observe that the contrast of the substrate layer near the gate of the ultrathin TEM sample becomes darker, fine-tune the "focus button" to align the zone axis and take a picture of the ultrathin TEM sample to obtain the third TEM image; where, Figure 3 , Figure 4 and Figure 5 The images are third TEM images of the ultrathin TEM sample at magnifications of 8600 x, 94000 x, and 150 kx, respectively.

[0049] The third step is to further adjust the TEM magnification until the gate oxide layer thickness of the ultrathin TEM sample can be clearly observed and measured (magnification approximately 630 kx). Keep the aperture at its maximum. At this point, the substrate layer beneath the gate oxide layer of the ultrathin TEM sample appears white (e.g., ...). Figure 6 As shown), the zone axis is misaligned (e.g. Figure 7 (As shown). At this point, it is necessary to repeat the first step above, adjusting the tilt angle of the ultrathin TEM sample, until the contrast of the substrate layer of the ultrathin TEM sample turns black (as shown). Figure 8 When (as shown), the zone axis has also been adjusted (as shown). Figure 9 As shown in the image, fine-tune the "focus" button to take a picture of the ultrathin TEM sample and obtain a TEM image.

[0050] In some implementations, step S1 specifically includes:

[0051] S101. Apply adhesive to the surface of the semiconductor device and perform ion beam deposition to obtain the sample to be thinned.

[0052] S102. The sample to be thinned is subjected to thinning treatment to obtain an ultrathin TEM sample.

[0053] The above step S101 specifically includes: applying adhesive to the surface of the semiconductor device to form a first protective layer on the surface of the semiconductor device, thereby obtaining an adhesive-coated sample;

[0054] The surface of the coated sample is subjected to ion beam deposition to form a second protective layer on the first protective layer of the coated sample, thus obtaining the sample to be thinned.

[0055] As an example, adhesive (such as a range of Master Bond adhesives, e.g., M-Bond 610) can be applied to the surface of a semiconductor device, spread evenly with a brush, and then baked at 60°C for 30 minutes to form a first protective layer (i.e., adhesive layer) on the surface of the semiconductor device, resulting in a brushed sample. Next, the sample stage is tilted to 52°~55°, and the brushed sample undergoes ion beam Pt deposition to form a second protective layer on top of the first protective layer, resulting in the sample to be thinned. The ion beam deposition process parameters include: accelerating voltage of 30kV, beam current of 0.3 nA, and beam current density of 10~20 pA / µm².

[0056] Please see Figure 10 The target region (typically including the gate and gate oxide layers) can be located based on the layout diagram of the semiconductor device. Then, ion beam Pt deposition is performed on the surface of this target region. The Pt deposition area is approximately 10 µm × 2 µm × 2 µm (e.g., ...). Figure 10(The area within the red rectangle in the image) can be deposited for 2-3 minutes.

[0057] By applying adhesive and performing ion beam deposition on semiconductor devices, the structural integrity of the semiconductor devices can be protected during subsequent thinning operations.

[0058] In some embodiments, the sample to be thinned is subjected to a thinning process to obtain an ultrathin TEM sample, including:

[0059] Identify the target region in the sample to be thinned;

[0060] Thin slices containing the target region are cut and separated from the sample to be thinned;

[0061] The thin film is transferred to a copper mesh and fixed at the edge of the mesh. The copper mesh is rotated to make the thin film parallel to the ion beam, and the thin film is thinned in a stepwise manner to obtain an ultrathin TEM sample.

[0062] As an example, the target region (typically containing the gate and gate oxide layers) can be located according to the layout diagram of the semiconductor device, and then the semiconductor device can be cross-sectioned (in a direction parallel to the substrate) or longitudinally sectioned (in a direction perpendicular to the substrate) to separate and extract a thin film containing the target region.

[0063] Please see Figures 11-14 First, the target region (typically including the gate and gate oxide layers) can be located based on the layout diagram of the semiconductor device. Then, a high beam current (accelerating voltage of 30 kV, beam current of 20~30 nA) is used in the target region (e.g., Figure 11 , Figure 12 As shown in the red rectangle, grooves are cut on both sides, with a groove depth of 3~5 µm, leaving a sheet thickness of 1.5~2 µm. Next, switch to a small beam (beam current of 1~2.5 nA) to polish the sides of the sheet, and then use a beam current of 2.5 nA to cut the bottom and sidewall connections of the sheet, leaving the cantilever uncut (as shown in the red rectangle). Figure 13 (As shown). Then, as... Figure 14 As shown, a nanorobotic arm was used to weld Pt onto the free end of the thin film (beam current 30-50 pA). After welding, the cantilever of the thin film was cut off to separate and extract the thin film containing the target region from the semiconductor device. Finally, as... Figure 15 As shown, the copper mesh is pre-tilted at 45°, and the aforementioned sheet is welded to the edge of the copper mesh using a nanorobot (beam current 50 pA, Pt fixed) to avoid stress damage. Before performing stepped thinning, the copper mesh is rotated to make the sheet parallel to the ion beam (tilt angle 10°) to ensure uniform thinning.

[0064] In some embodiments, the sheet is thinned in a stepwise manner to obtain an ultrathin TEM sample, including:

[0065] The first stage of thinning treatment is performed on the thin sheet to obtain the first thinned sheet;

[0066] The first thinned sheet is subjected to a second-stage thinning process to obtain a second thinned sheet;

[0067] The second thinned sheet was subjected to a third stage of thinning treatment to obtain an ultrathin TEM sample.

[0068] As an example, firstly, the above-mentioned thin sheet undergoes a first-stage thinning process (initial thinning) with an accelerating voltage of 30 kV and a beam current of 250 pA, resulting in a first thinned sheet with a thickness of 150–500 nm. Then, the first thinned sheet undergoes a second-stage thinning process (fine thinning) with an accelerating voltage of 30 kV and a beam current of 100–150 pA, resulting in a second thinned sheet with a thickness of 100–150 nm. Next, the second thinned sheet undergoes a third-stage thinning process (ultra-thin polishing) with an accelerating voltage of 5 kV and a beam current of 20 pA, resulting in an ultra-thin TEM sample with a thickness of less than 20 nm. Finally, the surface of the ultra-thin TEM sample is cleaned using a low voltage to remove its amorphous layer, with an accelerating voltage of 1–2 kV and a beam current of 20 pA, resulting in the final ultra-thin TEM sample (e.g., [image of sample]). Figure 16 (As shown).

[0069] By employing a stepped thinning method to reduce the thickness of the sheet, nanometer-level precision thinning can be achieved (thickness error ≤5nm, target area ≤1μm). Through "high-energy coarse reduction" and "medium-low energy fine reduction", the TEM sample preparation time can be reduced to 1-2 hours (60% faster than existing TEM sample preparation methods, greatly improving sample preparation efficiency). At the same time, the damage layer is controlled to ≤5nm and the local sample temperature is ≤50℃ (stress reduction of 70%). It can be adapted to bulk, thin film, or heterogeneous structures and special samples, accurately locates semiconductor micron-level fault points, improves TEM imaging clarity by 40%, and supports automated operation (error rate reduction of 1%), comprehensively meeting the needs of microscopic characterization and failure analysis.

[0070] To further illustrate the technical effects of the technical solutions provided in the embodiments of this application, the gate oxide layer thickness of the same semiconductor device was measured using both the measurement method provided in the embodiments of this application and a traditional measurement method. The test results are as follows: Figures 17-18 As shown.

[0071] from Figure 17 As can be seen, the measurement method provided in this application, at a magnification of 500 kx, shows that the gate oxide layer structure of the sample is clear and the substrate layer (silicon substrate) is normal.

[0072] from Figure 18It can be seen that, using the traditional measurement method, at a magnification of 500 kx, after adjusting the zone axis in diffraction mode (2 min), carbon deposits are formed on the substrate (silicon substrate), resulting in polycrystalline silicon irradiation damage and deformation of the gate oxide layer.

[0073] In summary, the technical solutions provided in this application have at least the following beneficial effects:

[0074] First, for ultrathin TEM samples, traditional techniques require multiple adjustments to the zone axis in diffraction mode, which can easily lead to radiation damage to the sample structure. Furthermore, the imaging time is long, resulting in low measurement efficiency and high measurement costs. In contrast, the technique proposed in this application eliminates the need to enter diffraction mode. Instead, it directly tilts the sample under the gate oxide layer, causing the contrast of the Si substrate at that location to darken, thus achieving zone axis alignment. This avoids radiation damage to ultrathin TEM samples, saves imaging time, improves measurement efficiency, and reduces measurement costs.

[0075] Second, the technical solution of this application provides new technical support for the design, manufacturing, reliability and process stability of semiconductor devices.

[0076] Third, the technical solution of this application is applicable to ultrathin TEM samples with high requirements for photography and measurement, and has wide applicability.

[0077] Fourth, the TEM images obtained by the technical solution of this application are of high quality, with clear structure, and the measurement results have high accuracy and precision, and good reliability.

[0078] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of measuring gate oxide thickness, characterized by, The method comprises the following steps: Preparation of an ultrathin TEM sample comprising, from bottom to top, a substrate layer, a gate oxide layer and other material layers; Placing the ultrathin TEM sample in a TEM lens field and setting the aperture to maximum, adjusting the tilt angle of the ultrathin TEM sample at a low magnification until the contrast of the substrate layer becomes black, adjusting the magnification and fine focus while keeping the aperture at maximum until the gate oxide layer can be clearly observed, taking a photo of the ultrathin TEM sample to obtain a TEM image; the tilt angle comprises an alpha angle and a beta angle; the adjustment range of the alpha angle is a first reference angle ± 25°, and the adjustment range of the beta angle is a second reference angle ± 25°; Measuring the thickness of the gate oxide layer according to the TEM image.

2. The method of measuring gate oxide thickness according to claim 1, wherein, The exposure time for taking a photo of the ultrathin TEM sample is 50 ms, and the current is 0.3 nA.

3. The method of claim 1, wherein, Preparation of an ultrathin TEM sample, comprising: Brushing glue on the surface of a semiconductor device and performing ion beam deposition treatment to obtain a sample to be thinned; Thinning the sample to be thinned to obtain an ultrathin TEM sample.

4. The method of claim 3, wherein, Brushing glue on the surface of a semiconductor device and performing ion beam deposition treatment to obtain a sample to be thinned, comprising: Brushing glue on the surface of a semiconductor device to form a first protective layer on the surface of the semiconductor device to obtain a brushed sample; Performing ion beam deposition treatment on the surface of the brushed sample to form a second protective layer on the first protective layer of the brushed sample to obtain a sample to be thinned.

5. The method of measuring gate oxide thickness of claim 4, wherein, The process parameters of the ion beam deposition treatment comprise: an acceleration voltage of 30 kV, a beam current of 0.3 nA, and a beam current density of 10-20 pA / µm².

6. The method of claim 3, wherein, Thinning the sample to be thinned to obtain an ultrathin TEM sample, comprising: Determining a target region in the sample to be thinned; Cutting and separating a thin piece containing the target region from the sample to be thinned; Transferring the thin piece to a copper mesh and fixing it at the edge of the copper mesh, rotating the copper mesh to make the thin piece parallel to the ion beam, and performing stepwise thinning on the thin piece to obtain an ultrathin TEM sample.

7. The method of claim 6, wherein, Thinning the thin piece to obtain an ultrathin TEM sample, comprising: Performing first-stage thinning treatment on the thin piece to obtain a first thinned piece; Performing second-stage thinning treatment on the first thinned piece to obtain a second thinned piece; Performing third-stage thinning treatment on the second thinned piece to obtain an ultrathin TEM sample.

8. The method of measuring gate oxide thickness of claim 7, wherein, The process parameters of the first-stage thinning treatment comprise: an acceleration voltage of 30 kV and a beam current of 250 pA; The process parameters of the second-stage thinning treatment comprise: an acceleration voltage of 30 kV and a beam current of 100-150 pA; The process parameters of the third-stage thinning treatment comprise: an acceleration voltage of 5 kV and a beam current of 20 pA.

9. The method of measuring gate oxide thickness of claim 7, wherein, The thickness of the first thinned piece is 150-500 nm, the thickness of the second thinned piece is 100-150 nm, and the thickness of the ultrathin TEM sample is 20 nm or less.

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