Vector instruction processing method, electronic device, readable medium and program product

Abstract

The present disclosure provides a vector instruction processing method, an electronic device, a readable medium and a program product. The vector instruction processing method comprises: obtaining a vector length of a vector instruction; in a case where the vector length of the vector instruction is a first value and a second source operand valid indication is a first value, canceling emission of the vector instruction, and setting the second source operand valid indication to a second value; the first value of the second source operand valid indication represents that an old value of a destination register is not required as an effective indication of a second source operand, and the second value of the second source operand valid indication represents that the old value of the destination register is required as the effective indication of the second source operand; in a case where the destination register is ready, re-emitting the vector instruction; obtaining a first source operand and a second source operand based on the vector instruction, and executing the vector instruction based on the first source operand and the second source operand, the second source operand being the old value of the destination register.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and in particular, to a vector instruction processing method, an electronic device, a readable medium and a program product. BACKGROUND

[0002] The fifth generation reduced instruction set computer (RISC-V) has the advantages of complete open source, simple architecture, and modularity. In the RISC-V vector extension (V extension) RVV 1.0 version, the element bit width and other information of the RVV instruction are no longer statically coded in the instruction code, but are dynamically controlled by the control and status register (CSR), so the flexibility is higher. In order to improve the performance of the superscalar out-of-order processor, the RVV uses an agnostic mechanism for tail elements and non-active elements, which can reduce the scenario of reading the old value of the destination register. However, in some special scenarios, the old value of the destination register needs to be preserved, otherwise the function of the superscalar out-of-order processor will be affected. Therefore, it is necessary to provide a vector instruction processing method that can guarantee the performance of the superscalar out-of-order processor and preserve the old value of the destination register in special scenarios. SUMMARY

[0003] The present disclosure provides a vector instruction processing method, an electronic device, a readable medium and a program product.

[0004] In a first aspect, an embodiment of the present disclosure provides a vector instruction processing method, comprising:

[0005] obtaining a vector length of a vector instruction;

[0006] in a case where the vector length of the vector instruction is a first value and a second source operand valid indication is a first value, canceling emission of the vector instruction, and setting the second source operand valid indication to a second value; the first value of the second source operation valid indication represents that the old value of the destination register is not needed as the valid indication of the second source operand, and the second value of the second source operation valid indication represents that the old value of the destination register is needed as the valid indication of the second source operand;

[0007] in a case where the destination register is ready, re-emitting the vector instruction;

[0008] obtaining a first source operand and the second source operand based on the vector instruction, and executing the vector instruction based on the first source operand and the second source operand, the second source operand being the old value of the destination register.

[0009] In a second aspect, an electronic device is provided, which includes a memory and a processor. The memory stores a computer program executable by the processor. The computer program, when executed by the processor, implements any of the vector instruction processing methods provided in the embodiments of the present disclosure.

[0010] In a third aspect, a computer readable medium is provided, which stores a computer program. The computer program, when executed by a processor, implements any of the vector instruction processing methods provided in the embodiments of the present disclosure.

[0011] In a fourth aspect, a computer program product is provided, which includes a computer program. The computer program, when executed by a processor, implements any of the vector instruction processing methods provided in the embodiments of the present disclosure.

[0012] The vector instruction processing method provided in the embodiments of the present disclosure cancels the emission of the vector instruction when the vector length of the vector instruction is a first value and the second source operand validity indication is a first value, and sets the second source operand validity indication to a second value. The first value of the second source operand validity indication represents that the old value of the destination register is not required as the source operand validity indication, and the second value of the second source operand validity indication represents that the old value of the destination register is required as the source operand validity indication. The vector instruction is re-emitted when the destination register is ready. The first source operand and the second source operand are obtained based on the vector instruction, and the vector instruction is executed based on the first source operand and the second source operand. This method can not only make full use of the agnostic mechanism allowed by the RVV instruction set, improve the parallel processing capability of the vector instruction, and thus guarantee the performance of the processor, but also meet the special scenario of retaining the old value of the destination register, and improve the out-of-order processing capability of the processor. BRIEF DESCRIPTION OF DRAWINGS

[0013] In the drawings of the embodiments of the present disclosure:

[0014] Figure 1 An execution schematic diagram of an RVV vector integer addition instruction in the related art is shown.

[0015] Figure 2 A structural block diagram of a superscalar out-of-order processor core is shown.

[0016] Figure 3 A flowchart of a vector instruction processing method provided in the embodiments of the present disclosure is shown.

[0017] Figure 4 A flowchart of a vector instruction processing method in the scenario of vl=0 is shown.

[0018] Figure 5A flowchart of a vector instruction processing method for a scenario where vl≠ 0 is shown;

[0019] Figure 6 A flowchart of a processing method for a vmacc.vv instruction is shown;

[0020] Figure 7 A block diagram of an electronic device is shown. DETAILED DESCRIPTION

[0021] For those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0022] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. The present disclosure may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0023] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, illustrate the embodiments of the present disclosure and together with the detailed description serve to explain the present disclosure. The above and other features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0024] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0025] The terms used in the present disclosure are only used to describe particular embodiments, and are not intended to limit the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in the present disclosure, the terms "comprises", "comprised of", "comprising", "consisting of" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] Unless otherwise defined, all terms used in the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0027] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0028] Figure 1 This diagram illustrates the execution of the RVV vector integer addition instruction in related technologies. For example... Figure 1 As shown, for the instructions `vadd.vvvd`, `vs2`, `vs1`, and `vm`, execution primarily relies on the vector type (vtype) CSR and the vector length (vl) CSR. Specifically, the vtype CSR's field `vector register set multiplier` (vlmul) = 3'b001 indicates that a single operand of the instruction consists of two vector registers (Vreg). The selected element bit width (vsew) = 3'b010 indicates that the element bit width for the instruction operation is 32 bits. `vma` (vma) = 0 indicates that for inactive elements indicated by the mask register (v0 mask), the final result should retain the old value in the destination register (vd). The vector tail element uncertainty (vta) = 1 indicates that for the tail element indicated by vl, the final result can either be all 1s or retain the old value in the destination register. The vl CSR specifies the number of elements to be computed in the current instruction.

[0029] For example, when vl=6, only the first 6 elements need to be calculated, and the last 2 elements are called the tail elements, following the update strategy indicated by the vtype.vta field.

[0030] In some related technologies, the processing rules for inactive elements and tail elements in RVV are listed in Table 1. Among them, "undisturbed" means that it is processed by preserving the old value of the destination register, and "agnostic" means that it can be processed by either writing all 1s or preserving the old value of the destination register.

[0031] Table 1

[0032]

[0033] In superscalar out-of-order processor cores, renaming mechanisms are generally used to remove pseudo-dependencies such as Write After Write (WAW) and Write After Read (WAR) to improve instruction-level parallel processing capabilities.

[0034] For example, Table 2 shows the source registers required by each instruction without reading the old value of the destination register. Assuming that the vector architecture registers v0-v5 are mapped to the vector physical registers p0-p5 respectively before the instruction sequence is executed, after renaming, the 2nd instruction and the 4th instruction write the results to the vector physical registers p6 and p8 respectively, so that the out-of-order scheduling can be performed without affecting the correctness of the results. However, the RVV instruction needs to retain the old value of the destination register in some scenarios. For example, it is stipulated that when vl=0, the destination register needs to retain the old value regardless of the settings of the vma field and the vta field, which brings a problem to the processor core supporting the renaming of the vl CSR. Because it is not known whether vl is equal to 0 in the decoding stage, in order to deal with the special scenario of vl=0, the old value of the destination register needs to be retained, which makes the destination register also a source operand, which in turn makes the WAW false dependency become a RAW true dependency, affecting the parallel scheduling capability of the instruction.

[0035] Table 2

[0036]

[0037] Table 3 shows the source registers required by each instruction when the old value of the destination register needs to be read. If the old value of the destination register needs to be read for each instruction, the 4th instruction will depend on the execution result of the 2nd instruction, and if the 2nd instruction is an instruction with a long latency such as division, the 4th instruction will be blocked for a long time, which seriously affects the performance of the processor.

[0038] Table 3

[0039]

[0040] In summary, if all vector instructions read the old value of the destination register, the performance of the superscalar out-of-order processor will be seriously affected. If the agnostic mechanism of RVV for tail elements and inactive elements is used to process vector instructions, although the scenario of reading the old value of the destination register can be reduced, flushing and re-decoding the pipeline when vl=0 will cause the vector instruction to affect the progress of pre-commit, thereby affecting the processing progress of the subsequent instructions that cannot be speculatively executed. Therefore, a processing method for inactive elements and tail elements of vector instructions is needed, which can not only guarantee the performance of the superscalar out-of-order processor, but also meet the functional requirements of retaining the old value of the destination register in special scenarios.

[0041] Figure 2 A structural block diagram of a superscalar out-of-order processor core is shown, which is used to implement the vector instruction processing method of the embodiments of the present disclosure. As shown in FIG. 1, the superscalar out-of-order processor core includes a front-end unit 101, a back-end unit 102, and a core interconnect 103. Figure 2As shown, the superscalar out-of-order processor core includes an instruction fetch unit (Fetch) 11, a decode unit (Decode) 12, a rename unit (Rename) 13, a dispatch unit (Dispatch) 14, a vector issue unit (Vec Issue) 15, a vector physical register file (VRF) / vl physical register file (VLRF) 16, a vector bypass network (Vec Bypass) 17, a vector execution unit (Vec Exe) 18, a scalar issue unit (Scalar Issue) 19, a scalar physical register file (GRF) 20, and a scalar execution unit (Scalar Exe) 21.

[0042] Fetch 11 is configured to fetch instructions from an instruction cache.

[0043] Decode 12 is configured to decode, according to a vta field and a vma field in a vtype CSR and a vm field in an instruction encoding, to generate an indication signal src2_v of whether a destination register old value is required as a source operand, to generate an effective indication src_vl_v of whether a vl source operand is required (src_vl_v=1 for a vector instruction), and to obtain an architectural number of the destination register (src2_tag) from the instruction encoding, and to pass the above information to the rename unit. Decode 12 is also configured to split a vector instruction, to split the vector instruction into uops (uops) and to forward the uops to a next-level module.

[0044] In an embodiment of the present disclosure, the vm field is located at Bit

[25] of the vector instruction encoding, vm=0 indicates that the vector instruction is controlled by v0 mask and can have non-active elements, otherwise, the vector instruction is not controlled by v0 mask and has no non-active elements.

[0045] In an embodiment of the present disclosure, src2_v=~(vta&(vma|vm)), and the destination register old value can be stored in a second register (src2).

[0046] Rename 13 is configured to convert the architectural number of the destination register into a physical number of the destination register according to a rename mapping table, and to allocate a new physical register for the destination register. If src2_v=1, or scr2_v=0 and src_vl_v=1, the physical number (src2_ptag) of the destination register old value can be obtained by querying a vector register rename mapping table through src2_tag; if src_vl_v=1, the physical number (vl_ptag) of the vl register can be obtained by querying a vl register rename mapping table.

[0047] Dispatch 14 is configured to receive the uops issued by the rename unit 13, and to dispatch the uops to corresponding issue units according to the types of the uops.

[0048] Vec Issue 15 issues the vector uops out of order, prioritizing the oldest ready uop for dispatch. For example, the first round of dispatch determines whether the destination register old value needs to be read based on the original src2_v (src2_v_true = src2_v) signal. If src2_v = 0, then the src2 operand is not needed, and the other operands are ready for arbitration for dispatch. If a vl_zero_cancel indication is received from the vector bypass network 18 (corresponding to a scenario where vl = 0 but the destination register old value is not read), then the vector uop is canceled, and the IQ copy of src2_v_true is forced to 1, and the second round of dispatch is performed when src2 is ready, which obtains the destination register old value.

[0049] VRF / VLRF 16, where VRF is used to store vector physical register data, and the corresponding data can be read based on the physical number of each source register. VLRF is used to store vl physical register data, and the corresponding data can be read based on the physical number of the vl register.

[0050] Vec Bypass 17 is used to obtain source register data from the physical register or the feedforward path of the execution unit, and send it to Vec Exe 18, while judging based on the obtained vl value. If ~src2_v_true & src_vl_v & vl = 0 (corresponding to a scenario where the vector instruction vl = 0 but the destination register old value is not read), then a vl_zero_cancel indication is sent to Vec Issue 15. The destination register tail element and the non-active element update strategy indication vm_vt_a, vm_vt_a = ~src2_v_true, are sent to Scalar Exe 21. A unified predicate register is generated based on the vl value and the v0 mask value, indicating irrelevant elements (corresponding to tail elements or non-active elements) and elements that need to be calculated in byte granularity.

[0051] Vec Exe 18 is used to perform corresponding operations on the input operands based on the function of the vector uop, and update the tail elements and non-active elements of the destination register based on the vm_vt_a indication. When vm_vt_a = 1, the tail elements and non-active elements are written as all 1s, otherwise, the second source register data src2_data, i.e., the destination register old value, is filled.

[0052] Scalar Issue 19 is used to dispatch scalar uops and uops decomposed from vector configuration instructions (vset{i}vl{i}).

[0053] The GRF 20 is used to store scalar physical register data, and the corresponding data is read according to the physical number of the source register.

[0054] The Scalar Exe 21 is used to execute scalar uops or uops decomposed from vector configuration instructions, to generate vl data or vector register data, and to send the data to the Vec Bypass 17.

[0055] In a first aspect, the embodiments of the present disclosure provide a vector instruction processing method.

[0056] Figure 3 A flowchart of a vector instruction processing method provided by the embodiments of the present disclosure is shown. As shown in FIG. 1, the vector instruction processing method provided by the embodiments of the present disclosure includes the following steps. Figure 3 The vector instruction processing method provided by the embodiments of the present disclosure includes the following steps.

[0057] In step S301, the vector length of a vector instruction is obtained.

[0058] In the embodiments of the present disclosure, the vector length vl of the vector instruction refers to the vector length of the RVV vector instruction operation.

[0059] In step S302, in a case where the vector length of the vector instruction is a first value, and the second source operand validity indication is a first value, the emission of the vector instruction is cancelled, and the second source operand validity indication is set to a second value.

[0060] The first value of the second source operation validity indication indicates that the old value of the destination register is not required as the validity indication of the second source operand, and the second value of the second source operation validity indication indicates that the old value of the destination register is required as the validity indication of the second source operand.

[0061] For example, the first value is “0”, and the second value is “1”. When the second source operation validity indication scr2_v=0, it indicates that the old value of the destination register is not required as the second source operand. When the second source operation validity indication scr2_v=1, it indicates that the old value of the destination register is required as the second source operand.

[0062] In the embodiments of the present disclosure, the first source operand and the second source operand are both values obtained from registers, and the difference lies in that the first source operand refers to a value directly obtained from a source register, and it is not required to determine whether to read the old value of the register. The second source operand refers to an old value obtained from a destination register, and it is required to determine whether to read the old value of the register. The old value of the destination register refers to a value stored before the destination register is updated.

[0063] The vector instruction in the launch queue is launched according to the out-of-order scheduling mode, when the vector instruction is launched, it is determined that the vector length vl of the vector instruction is 0, and the second source operation effective indication scr2_v is 0, the launch of the vector instruction is cancelled, and the scr2_v of the vector instruction copy in the launch queue is forcibly set to "1", and the launch queue is waited until the destination register is ready.

[0064] In some embodiments, the vector instruction is launched when the vector length of the vector instruction is not the first value.

[0065] For example, when the vector length vl of the vector instruction is not "0", the vector instruction is normally launched.

[0066] Step S303, when the destination register is ready, the vector instruction is re-launched.

[0067] When the destination register is ready, the vector instruction is re-launched, and at this time the vector instruction can normally obtain the old value of the destination register, that is, it meets the requirement of retaining the old value of the destination register in the vl=0 scenario.

[0068] In the launch queue, the vector instruction is launched according to the out-of-order scheduling mode, if the vector length of the vector instruction is not the first value, the vector instruction is normally launched, if the vector length of the vector instruction is the first value and the second source operation number effective indication is the first value, the launch of the vector instruction is cancelled, and the scr2_v of the vector instruction copy is forcibly set to "1", after the destination register is ready, the vector instruction is re-launched, at this time, the vector instruction can obtain the old value of the destination register from the destination register, so that the agnostic mechanism of RVV for tail elements and non-active elements can be fully utilized to reduce the scenario of reading the old value of the destination register, and at the same time, the requirement of retaining the old value of the destination register in the small probability scenario of vl=0 can be met.

[0069] Step S304, based on the vector instruction, the first source operand and the second source operand are obtained, and the vector instruction is executed based on the first source operand and the second source operand.

[0070] The vector instruction processing method provided by the embodiment of the present disclosure, in the case that the vector length of the vector instruction is a first value and the second source operand validity indication is a first value, cancels the emission of the vector instruction and sets the second source operand validity indication to a second value; the first value of the second source operation validity indication represents that the old value of the destination register is not required as the source operand validity indication, and the second value of the second source operation validity indication represents that the old value of the destination register is required as the source operand validity indication; in the case that the destination register is ready, the vector instruction is re-emitted; the first source operand and the second source operand are obtained based on the vector instruction, and the vector instruction is executed based on the first source operand and the second source operand, which can not only make full use of the agnostic mechanism allowed by the RVV instruction set to improve the parallel processing capability of the vector instruction, thereby guaranteeing the performance of the processor, but also meet the special scene of retaining the old value of the destination register and improve the out-of-order processing capability of the processor.

[0071] In some embodiments, the vector instruction includes at least one micro-operation (uop). The micro-operations can be obtained by splitting the vector instruction by a decode unit as shown in Figure 2 The decode unit can split the vector instruction into one or more micro-operations.

[0072] In some embodiments, emitting the vector instruction includes emitting the micro-operation that has the corresponding register in the ready state in the emission queue and enters the emission queue earliest, wherein the emission queue is a queue of vector instructions waiting to be emitted.

[0073] The embodiment is to emit the vector instruction in the emission queue by the out-of-order scheduling manner, check the state of the source register corresponding to each micro-operation in the emission queue, and emit the micro-operation when the source register corresponding to the micro-operation is in the ready state. When there are multiple micro-operations whose corresponding source registers are in the ready state, the micro-operation that enters the emission queue earliest is emitted preferentially.

[0074] The embodiment of the present disclosure does not limit the judgment manner of whether the source register is ready, and any manner capable of judging the state of the source register can be used for judgment.

[0075] In some embodiments, before re-emitting the vector instruction, the method further includes: dispatching the micro-operations into corresponding emission queues according to the types of the micro-operations.

[0076] The embodiment of the present disclosure can utilize the dispatch unit to dispatch the micro-operations into corresponding emission queues according to the types of the micro-operations, and emit the micro-operations by the corresponding vector emission unit.

[0077] In some embodiments, before obtaining the vector length of the vector instruction, further comprising: obtaining a vm field of the vector instruction, and a vma field and a vta field of the vector data type register; determining a second source operand valid indication src2_v, and an indication signal src_vl_v of whether the vl source operand is needed based on the vm field, the vma field and the vta field.

[0078] For example, src2_v=~(vta&(vma|vm)), and the old value of the destination register is stored in src2. src_vl_v=1 indicates that the vector instruction is a vector instruction.

[0079] In some embodiments, in the case that the vector instruction is an integer vector multiply-add instruction, i.e. the destination register old value is needed as an operation operand in the vector instruction itself, the second source operand valid indication is determined as the second value.

[0080] For example, assuming that the integer vector multiply-add instruction is vmacc.vv vd, vs1, vs2, vm, which defines the function vd[i] = +(vs1[i]×vs2[i]) + vd[i]), the old value of the destination register vd must be read and the old value of the destination register is used as the addend to participate in the operation, therefore, the decoding stage will set src2_v=1 and src2_tag=vd, so that even if vl=0, such a vector instruction will not have vl_zero_cancel in the subsequent steps, and the tail elements and non-active elements are always processed by preserving the old value of the destination register.

[0081] In the case that the execution result of the vector instruction is a mask register, the second source operand valid indication is determined based on the vm field and the vma field.

[0082] For example, if the vector instruction is an instruction whose execution result is a mask register, such as the vmseq.vv instruction, the vmfeq.vv instruction or the vms[b / i / o]f.m instruction. The second source operand valid indication src2_v=~(vma|vm), and no matter what value vtype.vta is, the tail elements always follow the tail-agnostic update strategy.

[0083] In the case that the vm field is the first value, all actual data operation elements need to be updated, and the source register is not used as a mask register, the second source operand valid indication is determined based on the vta field.

[0084] For example, for instruction encoding vm=0, but v0 as a borrow / carry or select indication signal, not as a mask register, such as vadc.vvm instruction, vmerge.vvm instruction or vfmerge.vfm instruction. The second source operand valid indication src2_v=~vta, such instructions update all actual data operation (body) elements, therefore, there is no inactive element, and the irrelevant element only needs to consider the tail element.

[0085] For instructions with vm field as the first value, the execution result of the vector instruction as a mask register and updating all body elements, the second source operand valid indication is determined as the first value.

[0086] For example, for instruction encoding vm=0, the execution result of the vector instruction as a mask register and updating all body elements, such as vmadc.vvm instruction, src2_v=0.

[0087] Table 4 lists a variety of special instructions without reading the old value of the destination register, the decoding of the valid indication src2_v of the old value reading of the destination register can be relaxed according to the characteristics of the vector instruction, so as to improve the program performance.

[0088] Table 4

[0089]

[0090] In some embodiments, before obtaining the vector length of the vector instruction, further comprising: obtaining the valid indication and the architecture number of the source register; querying the renaming table according to the architecture number of the source register to obtain the corresponding physical number, and allocating a new physical register for the destination register.

[0091] In the decoding stage, the decoding unit obtains the valid indication and the architecture number of the source register according to the vector instruction.

[0092] For example, for the vector instruction vadd.vv vd, vs2, vs1, vm (vm=0); vtype CSR: vma=1, vta=1, vlmul=0, the corresponding valid indication and the architecture number of the source register are as shown in Table 5.

[0093] Table 5 shows the valid indication and the architecture number of the source register

[0094]

[0095] In the renaming stage, the renaming unit queries the renaming table according to the architecture number of the source register to obtain the corresponding physical number of the source register, and allocates a new physical register for the destination register.

[0096] It should be noted that although src2_v=0, src_vl_v=1, so the renaming table is still queried to obtain the physical number of src2.

[0097] For example, the valid indication and the physical number of the source register of the vector instruction vadd.vv are shown in Table 6.

[0098] Table 6

[0099]

[0100] In some embodiments, based on the vector instruction obtaining the first source operand and the second source operand, and before executing the vector instruction based on the first source operand and the second source operand, further comprising: determining the indication of the irrelevant elements according to the value of the v0 field of the mask register and the vector length of the vector instruction; generating an update strategy indication of updating the irrelevant elements according to the valid indication of the second source operand.

[0101] The source register and the destination register can be vector / VL physical registers, and the operands of the execution unit are selected from a vector / VL physical register stack and a bypass network, and the execution unit irrelevant element indication (predicate) is generated according to the v0 mask and the vl value.

[0102] In some embodiments, the irrelevant elements include tail elements and non-active elements.

[0103] In the case where the update strategy indication of the irrelevant elements is the first value, the tail elements and the non-active elements retain the old value of the destination register.

[0104] In the case where the update strategy indication of the irrelevant elements is the second value, the tail elements and the non-active elements are written to the second value.

[0105] For example, the first value is 0 and the second value is 1, and the vector execution unit performs a corresponding operation on the first operand and the second operand according to the type of the micro-operation, and if vm_vt_a=1, the tail elements and the non-active elements are written to 1; if vm_vt_a=0, the old value of the destination register is retained.

[0106] In some embodiments, based on the vector instruction obtaining the first source operand and the first source operand, and based on the first source operand and the first source operand executing the vector instruction, comprising: obtaining the first source operand from the source register according to the physical number of the source register, and obtaining the old value of the destination register from the destination register as the second source operand according to the physical number of the destination register, and then executing the vector instruction based on the first source operand and the second source operand.

[0107] In some embodiments, obtaining the first source operand and the second source operand based on the vector instruction, and after performing the vector instruction based on the first source operand and the second source operand, the method comprises: writing back the execution result of the vector instruction to the physical register file.

[0108] After the execution of the vector instruction ends, the execution result can be written back to the vector physical register file.

[0109] In order to better understand the vector instruction processing method provided by the embodiment, the following is combined with Figure 4 and Figure 5 The following is further illustrated by taking the vector instruction and vtype CSR information as an example.

[0110] vadd.vv vd, vs2, vs1, vm (vm=0);

[0111] vtype CSR: vma=1, vta=1, vlmul=0.

[0112] Figure 4 A flowchart of a vector instruction processing method in the scenario of vl=0 is shown as follows. Figure 4 As shown in the figure, in the scenario of vl=0, the vector instruction processing method comprises:

[0113] In step S401, the valid indication and the architecture code of the source register are obtained according to the vector instruction.

[0114] If the vector instruction corresponds to multiple source registers, the valid indication and the architecture code of all the source registers are obtained, as shown in Table 5.

[0115] In the decoding stage, src2_v is obtained according to the configuration information of the current vtype CSR and the vm field of the vector instruction. If the configuration information of the vtype CSR includes the vma field and the vta field of the vector data type register, then src2_v=~(vta&(vma|vm))=0, indicating that the old value of the destination register is not read.

[0116] Since vm=0, src_v0=~vm=1, indicating that the v0 register needs to be read as a mask register. The vadd.vv vector instruction needs vs2 and vs1 as the source operands of the addition operation, which correspond to the source register src0 and the source register src1 respectively. According to the vtype CSR information, the current vtype.vlmul=0, so each source operand corresponds to only one vector register, and the vadd.vv vector instruction can only be split into one micro-operation.

[0117] In step S402, the corresponding physical number is obtained by querying the renaming table according to the architecture number of the source register, and a new physical register is allocated for the destination register.

[0118] In the renaming stage, for the vadd.vv vector instruction, although src2_v=0, src_vl_v=1, thus, the physical number of the source register src2 needs to be queried from the renaming table, and the valid signals and physical numbers of the source registers in the renaming stage are shown in Table 6.

[0119] In step S403, the micro-operations are allocated to the issue queues according to the types of the micro-operations.

[0120] In the dispatch stage, the micro-operations are allocated to the issue queues according to the types of the micro-operations, and each issue queue can correspond to a different vector issue unit, and the micro-operations in the issue queue are issued by the vector issue unit in an out-of-order scheduling manner.

[0121] In step S404, the ready states of the source registers corresponding to the micro-operations in the issue queue are checked, and among the micro-operations in which the source registers corresponding to the micro-operations are all ready, the micro-operation that enters the issue queue earliest is selected for issue.

[0122] For example, the source register src_v0, the source register src0, the source register src1, and the source register src_vl of the micro-operation are all ready, and the micro-operation is the earliest micro-operation among all the ready micro-operations in the issue queue, and then the micro-operation is issued for the first time.

[0123] In step S405, the vector / VL physical register file is read according to the micro-operations.

[0124] In the register reading stage, the vector / VL physical register file is read according to the actual needs of the micro-operations, the first source operand is obtained from the source register according to the physical number of the source register, and the old value of the destination register is obtained from the destination register according to the physical number of the destination register.

[0125] In step S406, the indication of the irrelevant element is determined according to the value of the vma field of the vector data type register and the vector length of the vector instruction, and the update strategy indication of the updated irrelevant element is generated according to the valid indication of the second source operand.

[0126] The operands of the execution unit are selected from the vector / VL physical register file and the bypass network, the indication of the irrelevant element and the update strategy indication are generated. The irrelevant element indication of the execution unit is generated according to the v0 mask and the vl value, and the update strategy indication vm_vt_a is generated according to src2_v_true, vm_vt_a=~src2_v_true=1.

[0127] In step S407, it is judged whether ~src2_v&src_vl_v&vl=0 is true, and if so, step S408 is performed.

[0128] According to Table 5, ~src2_v and src_vl_v are both 1, and if vl = 0, ~src2_v & src_vl_v & vl = 0.

[0129] In step S408, src2_v is set to "1", and the micro-operation is re-issued after the destination register src2 is ready.

[0130] In the data bypass stage, if it is found that ~src2_v_true & src_vl_v & vl = 0 by checking the vl value, a vl_zero_cancel indication is sent to the vector issue unit to cancel the issue of the micro-operation, i.e., the micro-operation will not be sent to the execution unit but will enter the issue stage again. src2_v is set to "1", and the valid signals and physical numbers of the source registers at this time are shown in Table 7.

[0131] Table 7

[0132]

[0133] In addition to the previously ready source registers src_v0, src0, src1 and src_vl, the destination register src2 also needs to be ready before the re-issued micro-operation can be performed.

[0134] In step S409, the vector / VL physical register file is read according to the micro-operation.

[0135] Step S409 is performed in the same way as step S405, and thus will not be described again.

[0136] In step S410, the indication of the irrelevant element is determined according to the value of the vma field of the vector data type register and the vector length of the vector instruction, and the update strategy indication of the updated irrelevant element is generated according to the valid indication of the second source operand.

[0137] The operand of the execution unit is selected from the vector / VL physical register file and the bypass network, and the indication of the irrelevant element and the update strategy indication are generated. The indication of the irrelevant element of the execution unit is generated according to the v0 mask and the vl value, and the update strategy indication vm_vt_a is generated according to src2_v_true, vm_vt_a = ~src2_v_true = 0.

[0138] In step S411, it is determined whether ~src2_v & src_vl_v & vl = 0 is true, and if not, step S412 is performed.

[0139] As shown in Table 7, although vl is equal to 0, scr2_v_true = 1, and thus no vl_zero_cancel is generated, and the micro-operation is successfully sent to the execution unit.

[0140] Step S412, performing corresponding operation on the operands according to the micro-operation type, obtaining the execution result, and reserving the old value of the destination register according to the indication of vm_vt_a=0 for the tail element and the non-active element.

[0141] The vector execution unit performs corresponding operation on the operands according to the micro-operation type, and processes the old value of the destination register carried in src2_data according to the indication of vm_vt_a=0 for the tail element and the non-active element.

[0142] Step S413, writing back the execution result of the vector instruction to the physical register file.

[0143] After the execution of the vector instruction ends, the data can be written back to the vector physical register file, and the execution of the vector instruction ends.

[0144] Figure 5 A flow chart of a vector instruction processing method in the scenario of vl≠0 is shown as follows. Figure 5 As shown in the figure, the vector instruction processing method in the scenario of vl≠0 includes:

[0145] Step S501, obtaining the effective indication of the source register and the architecture code according to the vector instruction.

[0146] Step S502, querying the renaming table according to the architecture number of the source register to obtain the corresponding physical number, and allocating a new physical register for the destination register.

[0147] Step S503, allocating the micro-operation to the launch queue according to the type of the micro-operation.

[0148] Step S504, checking the ready state of the source register corresponding to each micro-operation in the launch queue, and selecting the micro-operation that enters the launch queue earliest among the micro-operations whose corresponding source registers are all ready.

[0149] Step S505, reading the vector / VL physical register file according to the micro-operation.

[0150] Step S506, determining the indication of the irrelevant element according to the value of the vma field of the vector data type register and the vector length of the vector instruction; and generating the update strategy indication of updating the irrelevant element according to the effective indication of the second source operand.

[0151] Selecting the operands of the execution unit from the vector / VL physical register file and the bypass network, generating the indication of the irrelevant element and the update strategy indication. Generating the irrelevant element indication of the execution unit according to the v0 mask and the vl value, and generating the update strategy indication vm_vt_a according to src2_v_true, vm_vt_a=~src2_v_true=1.

[0152] Step S507, determine whether ~src2_v & src_vl_v & vl = 0 is true, if not, execute step S508.

[0153] According to table 5, ~src2_v and src_vl_v are both 1, if vl≠0, then ~src2_v & src_vl_v & vl≠0.

[0154] Step S508, according to the micro-operation type, perform corresponding operation on the operands, obtain the execution result, and write all 1s to the tail elements and non-active elements according to the indication of vm_vt_a = 1.

[0155] Step S509, write the execution result of the vector instruction back to the physical register file.

[0156] After the execution of the vector instruction ends, the data can be written back to the vector physical register file.

[0157] For special instructions, such as instructions whose destination register old value is required as an operation operand, the old value of the destination register needs to be processed according to the reservation. For example, the integer vector multiply-add instruction vmacc.vv vd, vs1, vs2, vm, whose definition function is vd[i] = +(vs1[i] x vs2[i]) + vd[i]), the old value of the destination register vd must be read to participate in the operation as an addend.

[0158] Figure 6 A flow chart of a processing method of a vmacc.vv instruction is shown. As shown in Figure 6 , the vector instruction processing method includes:

[0159] Step S601, obtain the effective indication of the source register and the architecture code according to the vmacc.vv instruction.

[0160] In the decoding stage, src2_v = 1, src2_tag = vd, even if vl = 0, such vector instructions will not produce vl_zero_cancel afterwards, and the tail elements and non-active elements are always processed according to the reservation of the old value of the destination register.

[0161] Step S602, query the renaming table according to the architecture number of the source register to obtain the corresponding physical number, and allocate a new physical register for the destination register.

[0162] Step S603, according to the type of the micro-operation, allocate the micro-operation to the emission queue.

[0163] Step S604, check the readiness of the source registers corresponding to the micro-operations in the issue queue, and among the micro-operations whose source registers are all ready, select the micro-operation that enters the issue queue earliest to issue.

[0164] Step S605, read the vector / VL physical register file according to the micro-operation.

[0165] Step S606, determine the indication of irrelevant elements according to the value of the vma field of the vector data type register and the vector length of the vector instruction; and generate an update strategy indication of updating the irrelevant elements according to the effective indication of the second source operand.

[0166] Select the operands of the execution unit from the vector / VL physical register file and the bypass network, generate the indication of irrelevant elements and the update strategy indication. Generate the indication of irrelevant elements of the execution unit according to the v0 mask and the vl value, and generate the update strategy indication vm_vt_a according to src2_v_true, vm_vt_a=~src2_v_true=0.

[0167] Step S607, determine whether ~src2_v&src_vl_v&vl=0 is true, and if not, execute step S608.

[0168] Since the vmacc.vv instruction itself needs the old value of the destination register as an operand, even if vl=0, such instructions will not have vl_zero_cancel in the future. The tail elements and non-active elements are always processed according to the reserved old value of the destination register.

[0169] Step S608, perform corresponding operations on the operands according to the micro-operation type, obtain the execution result, and reserve the old value of the destination register for the tail elements and non-active elements according to the indication of vm_vt_a=0.

[0170] Step S609, write the execution result of the vmacc.vv instruction back to the physical register file.

[0171] The execution flow of other special instructions shown in Table 3 is similar to that of the vadd.vv instruction, but the decoding of the destination register old value reading effective indication src2_v can be performed according to ~(vta&(vma|vm)), or can be relaxed according to the characteristics of the instruction, so that more scenarios do not need to read the old value of the destination register, and the program performance is improved.

[0172] The vector instruction processing method provided by the embodiments of the present disclosure can make full use of the agnostic mechanism allowed by the RVV instruction set, reduce the scenario of reading the old value of the destination register of the instruction, and greatly reduce the possibility of write-after-write false dependence becoming write-after-read true dependence, thereby improving the parallelism of the superscalar out-of-order processor in executing the vector instruction, and further improving the performance of the processor, while meeting the requirement of "preserving the old value of the destination register when vl=0", realizing the dual requirements of function and performance.

[0173] The vector instruction processing method provided by the embodiments of the present disclosure can be applied to all general-purpose processor (CPU) cores supporting vector instructions, and can also be applied to digital signal processors (DSPs), vector processors, or graphics processors (GPUs), etc.

[0174] In a second aspect, the embodiments of the present disclosure provide an electronic device.

[0175] Figure 7 A block diagram of an electronic device provided by the embodiments of the present disclosure is shown. As shown in the figure, Figure 7 The electronic device provided by the embodiments of the present disclosure includes a processor 701 and a memory 702. The memory 702 stores a computer program executable by the processor 701, and the computer program is executed by the processor 701 to implement any vector instruction processing method of the embodiments of the present disclosure.

[0176] In some embodiments, the electronic device further includes an I / O interface (read-write interface) 703 connected between the processor 701 and the memory 702, which can realize the information interaction between the memory 702 and the processor 701, including but not limited to a data bus (Bus) and the like.

[0177] Among them, the processor is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize the information interaction between the memory and the processor, including but not limited to a data bus (Bus) and the like.

[0178] Those of ordinary skill in the art can understand that the functional modules / units in all or some of the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0179] The embodiment of the present disclosure further provides a computer readable medium, which has a computer program stored thereon, wherein the computer program implements any of the vector instruction processing methods described in the above embodiments when executed by a processor.

[0180] The embodiment of the present disclosure further provides a computer program product, which comprises a computer program, and the computer program implements any of the vector instruction processing methods described in the above embodiments when executed by a processor.

[0181] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation.

[0182] Those of ordinary skill in the art can understand that the functional modules / units in all or some of the steps, systems and devices disclosed above can be implemented as software, firmware, hardware and appropriate combinations thereof.

[0183] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation.

[0184] Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on computer readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), FLASH memory or other solid state memory; compact disc read only memory (CD-ROM), digital versatile discs (DVDs), or other optical disk storage; magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices; any other medium that can be used to store the desired information and that can be accessed by a computer; and any other medium that can be used to store the desired information and that can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

[0185] The present disclosure has disclosed example embodiments, and while specific terminology has been employed, it is merely in the service of a general descriptive purpose and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics or / and elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, those skilled in the art will appreciate that various changes can be made in form and detail without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A vector instruction processing method, characterized in that, include: Get the length of the vector command; When the vector length of the vector instruction is a first value and the second source operand valid indication is a first value, the issuance of the vector instruction is cancelled and the second source operand valid indication is set to a second value; the first value of the second source operand valid indication indicates that the old value of the destination register is not needed as the valid indication of the second source operand, and the second value of the second source operand valid indication indicates that the old value of the destination register is needed as the valid indication of the second source operand. If the destination register is ready, the vector instruction will be retransmitted; The vector instruction obtains a first source operand and a second source operand, and executes the vector instruction based on the first source operand and the second source operand, wherein the second source operand is the old value of the destination register.

2. The method according to claim 1, characterized in that, The vector instruction includes at least one micro-operation; The transmission of the vector command includes: The micro-operation whose register corresponding to the micro-operation in the launch queue is in a ready state and which is the first micro-operation to enter the launch queue is launched, wherein the launch queue is a queue of vector instructions waiting to be launched.

3. The method according to claim 2, characterized in that, Before retransmitting the vector command, the method further includes: The micro-operations are assigned to the corresponding launch queues according to their type.

4. The method according to claim 1, characterized in that, Also includes: If the vector length of the vector command is not a first value, the vector command is transmitted.

5. The method according to claim 1, characterized in that, Before obtaining the vector length of the vector instruction, the method further includes: Obtain the vm field of the vector instruction, and the vma and vta fields of the vector data type register; The second source operand validity indication is determined based on the vm field, the vma field, and the vta field.

6. The method according to claim 5, characterized in that, When the vector instruction is an integer vector multiply-add instruction, the second source operand valid indicator is determined to be the second value; If the execution result of the vector instruction is a mask register, the validity indication of the second source operand is determined based on the vm field and the vma field; When the vm field is the first value, all actual data operation elements need to be updated, and the source register is not used as a mask register, the second source operand valid indication is determined based on the vta field; For instructions where the vm field is the first value, the execution result of the vector instruction is the mask register, and all actual data operation elements are updated, the second source operand valid indication is determined to be the first value.

7. The method according to claim 1, characterized in that, Before obtaining the vector length of the vector instruction, the method further includes: Obtain the valid indication and architecture number of the source register; The corresponding physical number is obtained by querying the renaming table based on the architecture number of the source register, and a new physical register is allocated for the destination register.

8. The method according to claim 7, characterized in that, Before obtaining the first source operand and the second source operand based on the vector instruction, and executing the vector instruction based on the first source operand and the second source operand, the method further includes: The indication of irrelevant elements is determined based on the value of the v0 field of the mask register and the vector length of the vector instruction; An update strategy instruction for updating the irrelevant elements is generated based on the valid instruction of the second source operand.

9. The method according to claim 8, characterized in that, The irrelevant elements include tail elements and inactive elements; When the update policy indication for the irrelevant element is the first value, the tail element and the inactive element retain the old value of the destination register; If the update strategy for irrelevant elements is indicated by the second value, then the tail element and the inactive element are written entirely to the second value.

10. The method according to claim 1, characterized in that, After obtaining the first source operand and the second source operand based on the vector instruction, and executing the vector instruction based on the first source operand and the second source operand, the process includes: Write the execution result of the vector instruction back to the physical register file.

11. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the vector instruction processing method according to any one of claims 1 to 10.

12. A computer-readable medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the vector instruction processing method according to any one of claims 1 to 10.

13. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the vector instruction processing method according to any one of claims 1 to 10.

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