Dual-pfc input power supply circuit and high-frequency interleaving control method thereof

Abstract

The application discloses a double-PFC input power supply circuit and a high-frequency stagger control method thereof. The double-PFC input power supply circuit comprises two parallelly connected PFC circuits, two micro control units (MCUs) are used for controlling the two PFC circuits to work respectively, and a synchronization circuit is arranged between the two micro control units and is used for transmitting a synchronization signal between the two micro control units, so as to realize the same-frequency stagger control of the driving signals of the two PFC circuits. The independent working mode of the two PFC circuits is retained, fault isolation is realized, the reliability of system operation is improved, the high-frequency stagger control mode of the two PFC circuits is realized through the two micro control units, parallel stagger driving of the two PFC circuits is realized, the input current ripple is reduced, the power density is improved, the load efficiency is improved, and the system reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of double-input AC-DC converter, in particular to a double-PFC input power supply circuit and a high-frequency stagger control method thereof. BACKGROUND

[0002] With the rapid development of science and technology, electronic products gradually play an important role in various aspects of people's life and work. As the heart of electronic products, power supply plays an irreplaceable role. The development of double-input power supply is the result of the interweaving of reliability demand, energy transformation and technological progress. With the increase of renewable energy penetration and the maturity of digital control technology, its application scenarios will further expand to smart home, edge computing and other emerging fields, becoming one of the key technologies for building flexible energy systems.

[0003] At present, the double-PFC control is mostly in the form of 180° stagger controlled by the same MCU or the output of two PFCs is connected in parallel to share the same bus capacitor. The former two PFC circuits are not in independent working mode and are not suitable for redundancy or shunt power supply scenarios. The latter has large ripple and low efficiency, and needs more number of capacitors to cope with the ripple current. SUMMARY

[0004] Therefore, it is necessary to provide a double-PFC input power supply circuit and a high-frequency stagger control method thereof, which can meet the independent working mode, have small current ripple and high efficiency.

[0005] A double-PFC input power supply circuit, comprising two parallel connected PFC circuits, each of which has a micro control unit MCU, two micro control units MCU are used to control two PFC circuits respectively, and a synchronization circuit is arranged between the two micro control units.

[0006] The two micro control units MCU include a master control unit MCU1 and a slave control unit MCU2, and the synchronization circuit is used for the master control unit MCU1 to send a high-frequency synchronization signal SYN to the slave control unit MCU2 to realize the same frequency stagger control of the driving signals of the two PFC circuits.

[0007] Preferably, the two PFC circuits include a first PFC circuit and a second PFC circuit, the input ends of the first PFC circuit and the second PFC circuit are connected to the same AC power supply end or different AC power supply ends, the output ends of the first PFC circuit and the second PFC circuit are connected in parallel to the load end, the first PFC circuit includes a first switch tube S1, and the second PFC circuit includes a second switch tube S2.

[0008] Preferably, an input end of the main control unit MCU1 is connected to an input end of the first PFC circuit, an output end of the main control unit MCU1 is connected to a gate of the first switch tube S1, and the main control unit MCU1 is configured to send a driving signal to the first switch tube S1.

[0009] An input end of the slave control unit MCU2 is connected to an input end of the second PFC circuit, and an output end of the slave control unit MCU2 is connected to a gate of the second switch tube S2, and the slave control unit MCU2 is configured to send a driving signal to the second switch tube S2.

[0010] Preferably, the main control unit MCU1 comprises a first timer configured to perform period timing of the main control unit MCU1.

[0011] The slave control unit MCU2 comprises a second timer configured to perform period timing of the slave control unit MCU2.

[0012] The first timer and the second timer have the same timing duration.

[0013] Furthermore, a high-frequency interleaving control method of a dual-PFC input power supply circuit is provided, which is configured to perform high-frequency interleaving control of switch tubes of two PFC circuits in the dual-PFC input power supply circuit.

[0014] Step one: circuit configuration; the two PFC circuits are arranged in parallel, and output ends of two micro control units MCU are respectively connected to a first switch tube S1 of a first PFC circuit and a second switch tube S2 of a second PFC circuit; a synchronization circuit is arranged between a main control unit MCU1 and a slave control unit MCU2;

[0015] Step two: the main control unit MCU1 generates a first period signal; when the device is powered on, a first timer in the main control unit MCU1 and a second timer in the slave control unit MCU2 are started;

[0016] Step three: a high-frequency synchronization signal SYN is generated and transmitted from the main control unit MCU1 to the slave control unit MCU2;

[0017] Step four: the slave control unit MCU2 generates a second period signal in synchronization; after the second timer is controlled to clear by the high-frequency synchronization signal SYN, the second timer starts timing again;

[0018] Step five: the main control unit MCU1 and the slave control unit MCU2 generate interleaving waveforms;

[0019] Step six, the master control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit to work respectively according to the staggered wave.

[0020] Preferably, the step two, the specific steps of the master control unit MCU1 generating the first periodic signal include:

[0021] Step 2.1, the device is powered on;

[0022] Step 2.2, the master control unit MCU1 and the slave control unit MCU2 are synchronized by the phase-locked loop PLL clock;

[0023] Step 2.3, the first timer in the master control unit MCU1 and the second timer in the slave control unit MCU2 are started;

[0024] Step 2.4, the master control unit MCU1 generates the first periodic signal according to the timing length of the first timer;

[0025] Step 2.5, the slave control unit MCU2 generates the second periodic signal according to the timing length of the second timer.

[0026] Preferably, the step three, the specific steps of generating the high-frequency synchronization signal SYN include:

[0027] Step 3.1, the first timer starts timing from 0, and when the time count value increases to a predetermined value of a predetermined length, the first timer is cleared and starts timing again;

[0028] Step 3.2, in the master control unit MCU1, when the time count value of the first timer is 0, the high-frequency synchronization signal SYN is flipped from low to high, and when the time count value of the first timer is half of the predetermined length, the high-frequency synchronization signal SYN is flipped from high to low;

[0029] Step 3.3, the high-frequency synchronization signal SYN is transmitted from the master control unit MCU1 to the slave control unit MCU2 through the synchronization circuit.

[0030] Preferably, the step four, the specific steps of the slave control unit MCU2 generating the synchronized second periodic signal include:

[0031] Step 4.1, the slave control unit MCU2 receives the high-frequency synchronization signal SYN;

[0032] Step 4.2, the rising edge of the high-frequency synchronization signal SYN triggers the second timer to clear;

[0033] Step 4.3, the second timer starts timing again from 0, and the time count value increases from 0 to a predetermined value of a predetermined length;

[0034] Step 4.4, the second periodic signal is generated by the slave control unit MCU2 according to the timing duration of the second timer.

[0035] Preferably, the step five, the specific steps of the master control unit MCU1 and the slave control unit MCU2 generating the staggered waveforms include:

[0036] Step 5.1, the master control unit MCU1 generates the first high-frequency drive signal, which is spread from the half of the first periodic signal to both sides;

[0037] Step 5.2, the slave control unit MCU2 generates the second high-frequency drive signal, which is spread from the starting point of the second periodic signal to both sides.

[0038] Preferably, the step six, the specific steps of the master control unit MCU1 and the slave control unit MCU2 controlling the first PFC circuit and the second PFC circuit to work according to the staggered waveforms include:

[0039] Step 6.1, the master control unit MCU1 samples the input voltage Vin1, the input current Iin1 and the output voltage Vout of the first PFC circuit, runs the PFC control algorithm, the voltage loop generates the current command according to the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the first high-frequency drive signal according to the current command and the sampled input current Iin1;

[0040] Step 6.2, the slave control unit MCU2 samples the input voltage Vin2, the input current Iin2 and the output voltage Vout of the second PFC circuit, runs the PFC control algorithm, the voltage loop generates the current command according to the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the second high-frequency drive signal according to the current command and the sampled input current Iin2;

[0041] Step 6.3, the first high-frequency drive signal and the second high-frequency drive signal are sent to the gate of the first switch S1 of the first PFC circuit and the gate of the second switch S2 of the second PFC circuit respectively.

[0042] The double PFC input power supply circuit and the high-frequency stagger control method thereof have the advantages that the main control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit arranged in parallel, so that the first PFC circuit and the second PFC circuit remain the independent working mode, fault isolation is realized, and the reliability of system operation is improved. Meanwhile, the main control unit MCU1 and the slave control unit MCU2 implement the high-frequency stagger control mode on the first PFC circuit and the second PFC circuit, parallel stagger driving of the two PFC circuits is realized, the input current ripple is reduced, the power density is improved, the load efficiency is improved, and the system reliability is improved. The double PFC input power supply circuit has the advantages of simple structure, easy implementation, low cost, and convenience for popularization. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 FIG. 1 is a structural schematic diagram of a double PFC input power supply circuit according to an embodiment of the present application.

[0044] Figure 2 FIG. 2 is a flowchart of a high-frequency stagger control method of a double PFC input power supply circuit according to an embodiment of the present application.

[0045] Figure 3 FIG. 3 is a double PFC stagger control schematic diagram of a high-frequency stagger control method of a double PFC input power supply circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The double PFC input power supply circuit and the high-frequency stagger control method thereof will be described in detail below with reference to specific embodiments and the accompanying drawings.

[0047] Please refer to Figure 1 FIG. 1 is a structural schematic diagram of a double PFC input power supply circuit according to an embodiment of the present application. The double PFC input power supply circuit comprises two parallel connected PFC circuits. Each of the PFC circuits has a micro control unit MCU. Two micro control units MCU are used to control the working of the two PFC circuits respectively. A synchronization circuit is arranged between the two micro control units.

[0048] The two micro control units MCU include a main control unit MCU1 and a slave control unit MCU2. The synchronization circuit is used to send a high-frequency synchronization signal SYN from the main control unit MCU1 to the slave control unit MCU2, so as to realize the same-frequency stagger control of the driving signals of the two PFC circuits.

[0049] Specifically, the power factor correction (PFC) circuit is mainly used to improve the power factor of an AC-DC conversion system and reduce harmonic pollution. The PFC circuit adjusts the input current waveform so that it is in phase with the input voltage waveform, thereby improving the efficiency of electric energy utilization.

[0050] By parallel connection of the two PFC circuits, high-power loads can be shared, and the parallel connection is suitable for high-power application scenarios; the two PFC circuits controlled in an interleaved manner can offset part of the ripples, so that the input current is smoother; the system efficiency is improved, the shell reliability is enhanced, and the two parallel PFC circuits are more suitable for high-power scenarios.

[0051] Preferably, the two PFC circuits include a first PFC circuit and a second PFC circuit, input ends of the first PFC circuit and the second PFC circuit are connected to the same AC power end or different AC power ends, output ends of the first PFC circuit and the second PFC circuit are connected in parallel to a load end, the first PFC circuit includes a first switch tube S1, and the second PFC circuit includes a second switch tube S2.

[0052] Preferably, an input end of the main control unit MCU1 is connected to an input end of the first PFC circuit, an output end of the main control unit MCU1 is connected to a gate of the first switch tube S1, and the main control unit MCU1 is configured to send a driving signal to the first switch tube S1.

[0053] An input end of the slave control unit MCU2 is connected to an input end of the second PFC circuit, an output end of the slave control unit MCU2 is connected to a gate of the second switch tube S2, and the slave control unit MCU2 is configured to send a driving signal to the second switch tube S2.

[0054] Specifically, the main control unit MCU1 and the slave control unit MCU2 adopt a communication protocol such as SPI, I2C, UART, or USART, and implement high-frequency synchronization signal SYN transmission.

[0055] The synchronization circuit is provided with a shielding line and a terminal resistor to realize impedance matching of the circuit, avoid electromagnetic interference, and ensure signal integrity.

[0056] Preferably, the main control unit MCU1 includes a first timer, and the first timer is configured to perform period length timing of the main control unit MCU1.

[0057] The slave control unit MCU2 includes a second timer, and the second timer is configured to perform period length timing of the slave control unit MCU2.

[0058] The first timer and the second timer have the same timing length.

[0059] Specifically, the first timer and the second timer have a predetermined timing length, and after the predetermined timing length is reached, the first timer and the second timer are reset and start timing again.

[0060] Specifically, the predetermined timing duration of the first timer and the second timer depends on the frequency and period of the driving signal of the switch tube in the PFC circuit. The higher the frequency and the shorter the period of the switch tube, the shorter the timing duration of the first timer and the second timer; on the contrary, the lower the frequency and the longer the period of the switch tube, the longer the timing duration of the first timer and the second timer.

[0061] And, refer to Figure 2 , show a high-frequency interleaving control method of a dual-PFC input power supply circuit, for realizing high-frequency interleaving control of the switch tubes of the two PFC circuits in the dual-PFC input power supply circuit as described above, the specific steps of the method include:

[0062] Step S10, circuit configuration; the two PFC circuits are arranged in parallel, and the output ends of the two micro control units MCU are respectively connected to the first switch tube S1 of the first PFC circuit and the second switch tube S2 of the second PFC circuit; a synchronization circuit is arranged between the master control unit MCU1 and the slave control unit MCU2.

[0063] Specifically, the working frequency of the PFC is set in the master control unit MCU1, and the corresponding switching period is calculated.

[0064] Step S20, the master control unit MCU1 generates a first period signal; the device is powered on to start, and the first timer in the master control unit MCU1 and the second timer in the slave control unit MCU2 start.

[0065] The specific steps include:

[0066] Step S21, the device is powered on to start;

[0067] Step S22, the master control unit MCU1 and the slave control unit MCU2 are synchronized by the phase-locked loop PLL clock;

[0068] Step S23, the first timer in the master control unit MCU1 and the second timer in the slave control unit MCU2 start;

[0069] Step S24, the master control unit MCU1 generates a first period signal according to the timing duration of the first timer;

[0070] Step S25, the slave control unit MCU2 generates a second period signal according to the timing duration of the second timer.

[0071] Step S30, generate a high-frequency synchronization signal SYN, and transmit the high-frequency synchronization signal SYN from the master control unit MCU1 to the slave control unit MCU2.

[0072] The specific steps include:

[0073] Step S31, the first timer starts counting from 0, and when the time count value increases to a predetermined value of a predetermined time length, the first timer is cleared and starts counting again;

[0074] Step S32, in the main control unit MCU1, when the time count value of the first timer is 0, the high-frequency synchronization signal SYN is flipped from low to high, and when the time count value of the first timer is half of the predetermined time length, the high-frequency synchronization signal SYN is flipped from high to low;

[0075] Step S33, the high-frequency synchronization signal SYN is transmitted from the main control unit MCU1 to the slave control unit MCU2 through the synchronization circuit.

[0076] Step S40, the slave control unit MCU2 generates a synchronized second periodic signal; after the second timer is cleared by the high-frequency synchronization signal SYN, the second timer starts counting again.

[0077] The specific steps include:

[0078] Step S41, the slave control unit MCU2 receives the high-frequency synchronization signal SYN;

[0079] Step S42, the rising edge of the high-frequency synchronization signal SYN triggers the second timer to clear;

[0080] Step S43, the second timer starts counting again from 0, and the time count value increases from 0 to a predetermined value of a predetermined time length;

[0081] Step S44, the slave control unit MCU2 generates a second periodic signal according to the timing length of the second timer.

[0082] Specifically, under the action of the high-frequency synchronization signal SYN, the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2 are synchronized, so that the first periodic signal generated by the main control unit MCU1 and the second periodic signal generated by the slave control unit MCU2 are synchronized.

[0083] Step S50, the main control unit MCU1 and the slave control unit MCU2 generate staggered wave emission.

[0084] The specific steps include:

[0085] Step S51, the main control unit MCU1 generates a first high-frequency drive signal, and the first high-frequency drive signal spreads to both sides from the middle of the first periodic signal;

[0086] Step S52, the slave control unit MCU2 generates a second high-frequency drive signal, and the second high-frequency drive signal spreads to both sides from the starting point of the second periodic signal.

[0087] Specifically, the first high-frequency drive signal and the second high-frequency drive signal are out of phase by 180°, in order to provide power density of the circuit, the duty cycle of the first high-frequency drive signal and the second high-frequency drive signal is less than 50%, by reducing the ripple current and optimizing the operating point, the system efficiency is improved.

[0088] Step S60, the master control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit to work respectively according to staggered wave.

[0089] Specific steps include:

[0090] Step S61, the master control unit MCU1 samples the input voltage Vin1, the input current Iin1 and the output voltage Vout of the first PFC circuit, runs the PFC control algorithm, the voltage loop generates the current command according to the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the first high-frequency drive signal according to the current command and the sampled input current Iin1;

[0091] Step S62, the slave control unit MCU2 samples the input voltage Vin2, the input current Iin2 and the output voltage Vout of the second PFC circuit, runs the PFC control algorithm, the voltage loop generates the current command according to the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the second high-frequency drive signal according to the current command and the sampled input current Iin2;

[0092] Step S63, the first high-frequency drive signal and the second high-frequency drive signal are sent to the gate of the first switch tube S1 of the first PFC circuit and the gate of the second switch tube S2 of the second PFC circuit respectively.

[0093] Specifically, the work of the double PFC is controlled by two MCUs respectively, although in the software control two ways will control to the same working frequency, but due to the inevitable difference between the two MCUs, it is impossible to guarantee that the frequency of the two PFCs is completely consistent, which will lead to the input current beat frequency effect, which may affect the normal work of the load, so it is necessary to ensure that the working frequency of the two PFCs is completely consistent.

[0094] In this embodiment, the double PFC circuit is independently controlled by one micro control unit MCU, under this condition, as shown in the figure, Figure 3 the MCU determines the working frequency according to the period value (P) of the timer timer, Figure 3 as shown in the figure, the timer counts from 0 to P and resets to 0, and counts periodically. From Figure 3It can be seen that when the cycle count of MCU1 reaches P, the count value of MCU2 has not reached P, assuming that the working frequency error time of MCU1 and MCU2 is t0, it can be seen that when the cycle count of MCU1 reaches P, the count value of MCU2 is at (P-t0), however, at this time, MCU2 has not reached the count cycle value P and does not occur count reset, and MCU1 has reached the cycle value P and has carried out count reset. Only when the count of MCU1 and MCU2 is completely synchronized, the complete same frequency and interleaving can be ensured. Therefore, before the two-way PFC circuit normally works to send out PWM, the high-frequency synchronization signal SYN is needed to carry out immediate synchronization before starting, which is transmitted from MCU1 to MCU2. When the timer count of MCU1 is at 0(P), the high-frequency synchronization signal is flipped from low level to high level, and at P / 2, it is flipped from high level to low level. When the timer count of MCU2 reaches (P-t0), the high-frequency synchronization signal SYN from MCU1 is received. MCU2 uses the rising edge of the high-frequency synchronization signal SYN as a trigger condition to reset the timer counter, and the synchronization of the timers of MCU1 and MCU2 is completed. After the PFC circuit starts to send PWM, the timer count period of MCU2 is finely adjusted to ensure real-time dynamic synchronization. The fine adjustment is strictly limited to ensure that it does not affect the current harmonic, power factor and other working states, so that P-t0 approaches 0(P). On this basis, the interleaved wave sending shown in Figure 3 can be completed. SYN_MCU1_PWM wave sending is spread from P / 2 to both sides, and SYN_MCU2_PWM is spread from P to both sides, ensuring 180° interleaving.

[0095] Figure 3 The annotations of each signal in the above table are as follows:

[0096] MCU1-MaterTimer—timer counter of MCU1;

[0097] MCU2-MaterTimer—timer counter of MCU2;

[0098] SYN—high-frequency synchronization signal from MCU1 to MCU2;

[0099] SYN_MCU2-MaterTimer—timer counter of MCU2 after synchronization;

[0100] SYN_MCU1_PWM—PWM wave sending of MCU1 after counter synchronization;

[0101] SYN_MCU2_PWM—PWM wave sending of MCU2 after counter synchronization.

[0102] In the double PFC input power supply circuit and the high-frequency stagger control method thereof, the master control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit arranged in parallel, so that the first PFC circuit and the second PFC circuit remain independent working modes, fault isolation is realized, and the reliability of system operation is improved. Meanwhile, the master control unit MCU1 and the slave control unit MCU2 implement high-frequency stagger control on the first PFC circuit and the second PFC circuit, parallel stagger driving of the two PFC circuits is realized, input current ripple is reduced, power density is improved, load efficiency is improved, and system reliability is enhanced. The application has simple structure, is easy to implement, is low in cost, and is convenient to popularize.

[0103] It should be noted that the above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A dual PFC input power supply circuit comprising two parallel connected PFC circuits, characterized in that, Each of the PFC circuits has a micro control unit MCU, two of the micro control units MCU are used to control the two PFC circuits to work respectively, and a synchronization circuit is arranged between the two micro control units; The two micro control units MCU include a master control unit MCU1 and a slave control unit MCU2, and the synchronization circuit is used for the master control unit MCU1 to send a high-frequency synchronization signal SYN to the slave control unit MCU2, so as to realize the same-frequency staggered control of the driving signals of the two PFC circuits. The master control unit MCU1 includes a first timer, and the first timer is used for period length timing of the master control unit MCU1; the slave control unit MCU2 includes a second timer, and the second timer is used for period length timing of the slave control unit MCU2; and the timing lengths of the first timer and the second timer are the same. The high-frequency staggered control method of the double-PFC input power supply circuit is used to realize the high-frequency staggered control of the switching tubes of the two PFC circuits in the double-PFC input power supply circuit, and the specific steps of the method include: Step one, circuit configuration; the two PFC circuits are arranged in parallel, the output ends of the two micro control units MCU are connected to the first switching tube S1 of the first PFC circuit and the second switching tube S2 of the second PFC circuit respectively, and a synchronization circuit is arranged between the master control unit MCU1 and the slave control unit MCU2; Step two, the master control unit MCU1 generates a first period signal; the device is powered on to start, and the first timer in the master control unit MCU1 and the second timer in the slave control unit MCU2 start; Step three, a high-frequency synchronization signal SYN is generated, and the high-frequency synchronization signal SYN is transmitted from the master control unit MCU1 to the slave control unit MCU2; Step four, the slave control unit MCU2 generates a synchronized second period signal; after the second timer is controlled to clear by the high-frequency synchronization signal SYN, the second timer starts timing again; Step five, the master control unit MCU1 and the slave control unit MCU2 generate staggered waveforms; Step six, the master control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit to work respectively according to the staggered waveforms; The specific steps of step four, in which the slave control unit MCU2 generates a synchronized second period signal, include: Step 4.1, the slave control unit MCU2 receives the high-frequency synchronization signal SYN; Step 4.2, the rising edge of the high-frequency synchronization signal SYN triggers the second timer to clear; Step 4.3, the second timer starts timing again from 0, and the time count value increases from 0 to a predetermined value of a predetermined length; Step 4.4, the slave control unit MCU2 generates a second period signal according to the timing length of the second timer; The specific steps of step five, in which the master control unit MCU1 and the slave control unit MCU2 generate staggered waveforms, include: Step 5.1, the master control unit MCU1 generates a first high-frequency driving signal, and the first high-frequency driving signal spreads to both sides from the half of the first period signal; Step 5.2, the second high-frequency drive signal is generated from the control unit MCU2, and the second high-frequency drive signal is spread from the starting point of the second periodic signal to both sides.

2. The dual PFC input power supply circuit of claim 1, wherein, The two-way PFC circuit includes a first PFC circuit and a second PFC circuit, the input ends of the first PFC circuit and the second PFC circuit are connected to the same AC power end or different AC power ends, and the output ends of the first PFC circuit and the second PFC circuit are connected in parallel to the load end, the first PFC circuit includes a first switch tube S1, and the second PFC circuit includes a second switch tube S2.

3. The dual PFC input power supply circuit of claim 2, wherein, The input end of the main control unit MCU1 is connected to the input end of the first PFC circuit, the output end of the main control unit MCU1 is connected to the gate of the first switch tube S1, and the main control unit MCU1 is used to send a drive signal to the first switch tube S1. The input end of the slave control unit MCU2 is connected to the input end of the second PFC circuit, the output end of the slave control unit MCU2 is connected to the gate of the second switch tube S2, and the slave control unit MCU2 is used to send a drive signal to the second switch tube S2.

4. The dual PFC input power supply circuit of claim 1, wherein, The specific steps of the step two, the main control unit MCU1 generating the first periodic signal, include: Step 2.1, the device is powered on; Step 2.2, the main control unit MCU1 and the slave control unit MCU2 are synchronized by a phase-locked loop PLL clock; Step 2.3, the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2 are started; Step 2.4, the main control unit MCU1 generates a first periodic signal according to the timing duration of the first timer; Step 2.5, the slave control unit MCU2 generates a second periodic signal according to the timing duration of the second timer.

5. The dual PFC input power supply circuit of claim 1, wherein, The specific steps of the step three, generating a high-frequency synchronization signal SYN, include: Step 3.1, the first timer starts timing from 0, and when the time count value increases to a predetermined value of a predetermined time length, the first timer is cleared and starts timing again; Step 3.2, in the main control unit MCU1, when the time count value of the first timer is 0, the high-frequency synchronization signal SYN is flipped from low to high, and when the time count value of the first timer is half of the predetermined time length, the high-frequency synchronization signal SYN is flipped from high to low; Step 3.3, the high-frequency synchronization signal SYN is transmitted from the main control unit MCU1 to the slave control unit MCU2 through a synchronization circuit.

6. The dual PFC input power supply circuit of claim 1, wherein, The specific steps of the step six, the main control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit to work respectively according to staggered wave generation, include: Step 6.1, the main control unit MCU1 samples the input voltage Vin1, the input current Iin1 and the output voltage Vout of the first PFC circuit, runs a PFC control algorithm, and the voltage loop generates a current command according to the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the first high-frequency drive signal according to the current command and the sampled input current Iin1. Step 6.2, the input voltage Vin2, the input current Iin2 and the output voltage Vout of the second PFC circuit are sampled from the control unit MCU2, the PFC control algorithm is run, the current command is generated according to the error of the output voltage Vout in the voltage loop, and the PWM duty ratio of the second high-frequency drive signal is calculated according to the current command and the sampled input current Iin2 in the current loop; Step 6.3, the first high-frequency drive signal and the second high-frequency drive signal are sent to the gate of the first switch tube S1 of the first PFC circuit and the gate of the second switch tube S2 of the second PFC circuit respectively.

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