Pwm signal generation system, clock cycle resolution method, processor, and medium

Abstract

The embodiment of the application relates to the technical field of electronics, in particular to a PWM signal generation system, which comprises a PWM generation circuit and a clock cycle analysis circuit. The embodiment of the application dynamically adjusts the number of buffers of an initial delay line, and adaptively determines a target number according to a delay signal state, thereby greatly shortening the calculation period of the total number of buffers in the PWM generation circuit and avoiding the time-consuming iterative calculation in the traditional scheme. In addition, the logic of deriving the total number of buffers based on the target number can realize accurate matching of the delay time of the buffer and the clock cycle, improve the control accuracy of the PWM duty cycle by combining the fine delay processing of the delay unit on the PWM signal, and make up for the defects of insufficient accuracy of the traditional circuit. The system also integrates a temperature sensor and a voltage sensor, and the microprocessor can correct the deviation of the delay time of the buffer in combination with the environmental parameters, enhance the stability of the system under complex working conditions, and widen the applicable scenarios of the system in the technical field of electronics.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and particularly relate to a PWM signal generation system, a clock cycle analysis method, a processor and a medium. BACKGROUND

[0002] With the rapid development of electronic technology, digital PWM (Pulse Width Modulation) technology has been widely used in the fields of power electronics, motor control, industrial automation, etc. When the engineering needs a digital pulse width modulation signal circuit to output various PWM signals, due to the problem of insufficient precision of the traditional digital pulse width modulation signal circuit, it cannot accurately output various PWM signals. At present, there are many hybrid PWM technology schemes on the market, among which the delay line architecture PWM technology is the current mainstream technology scheme. This architecture is mainly composed of a delay chain composed of a counter, a comparator and a buffer. The counter and the comparator part mainly realize the coarse adjustment function of the PWM duty cycle, and the delay chain undertakes the fine adjustment function of the duty cycle, the upper limit of the adjustment range is one clock cycle, and the precision depends on the delay characteristics of the buffer.

[0003] However, the delay characteristics of a single buffer often cannot meet the requirement of the minimum duty cycle precision of PWM, so the number of buffers in the delay line needs to be reasonably determined. The existing related technology has the problem of long time consumption in determining the number of buffers, which greatly reduces the overall generation efficiency of the PWM signal. SUMMARY

[0004] An object of embodiments of the present application is to provide a PWM signal generation system, a clock cycle analysis method, a processor and a medium to solve the technical problem of low PWM signal generation efficiency in the related art.

[0005] In a first aspect, embodiments of the present application provide a PWM signal generation system, comprising a PWM generation circuit and a clock cycle analysis circuit, the clock cycle analysis circuit comprising a plurality of buffers, a selector module, a first latch, a temperature sensor, a voltage sensor and a microprocessor, the selector module comprising a plurality of selection input terminals, one selection input terminal being electrically connected to the output terminal of one buffer, the total selection output terminal of the selector module being electrically connected to the set terminal of the first latch, the clock terminal of the first latch and the first buffer being configured to input a clock signal, the microprocessor being electrically connected to each buffer, the selector module, the temperature sensor, the voltage sensor and the PWM generation circuit respectively, and the microprocessor being configured to:

[0006] input a preset clock signal into an initial delay line to obtain a delay signal after delay processing, the initial delay line being composed of a reference number of buffers connected in series;

[0007] in response to the delay signal not being high, increasing the number of buffers included in the initial delay line to delay the next clock signal until the delay signal output by the initial delay line is high, at which point the number of buffers included in the initial delay line is determined to be a target number, the total delay time of the target number of buffers being equal to the duty cycle time of the clock signal;

[0008] in response to the delay signal being high, determining the reference number to be the target number;

[0009] determining a total buffer number based on the target number and the duty cycle time, the total delay time of the total buffer number being equal to a clock period of the clock signal, the PWM generation circuit including a delay unit configured to delay a PWM signal of the PWM generation circuit;

[0010] updating the number of buffers included in the delay unit based on the total buffer number.

[0011] Optionally, the microprocessor is configured to input a preset clock signal into the initial delay line to obtain a delay signal subjected to delay processing, including: in response to the PWM generation circuit entering a power-on state, obtaining an initial operating temperature of the buffer and an initial operating voltage for driving the buffer to operate; inputting the initial operating temperature and the initial operating voltage into a preset buffer model to obtain an initial estimated delay time of the buffer; determining a reference number based on a duty cycle time of the clock signal and the initial estimated delay time, wherein a number of buffers equal to the reference number are connected in series to form the initial delay line; and inputting the preset clock signal into the initial delay line to obtain the delay signal subjected to delay processing.

[0012] Optionally, the microprocessor is further configured to: in response to the PWM generation circuit having output a specified number of PWM signals, obtain an intermediate operating temperature of the buffer and an intermediate operating voltage for driving the buffer to operate; and update the total buffer number based on the intermediate operating temperature and the intermediate operating voltage.

[0013] Optionally, the microprocessor is further configured to update the total buffer number based on the intermediate operating temperature and the intermediate operating voltage, including: inputting the intermediate operating temperature and the intermediate operating voltage into the buffer model to obtain an intermediate estimated delay time of the buffer; calculating a time difference value between the intermediate estimated delay time and the initial estimated delay time; in response to an absolute value of the time difference value being greater than or equal to a preset offset difference value, re-determining the total buffer number; and in response to the absolute value of the time difference value being less than the preset offset difference value, maintaining the total buffer number unchanged.

[0014] Optionally, the microprocessor is further configured to: acquire a real-time working temperature of the buffer at each clock cycle and a real-time working voltage driving the buffer to work; in response to an absolute temperature difference between the real-time working temperature and a preset temperature threshold being greater than the preset temperature threshold, perform an updating operation on the total buffer quantity; or in response to an absolute voltage difference between the real-time working voltage and a preset voltage threshold being greater than the preset voltage threshold, perform the updating operation on the total buffer quantity.

[0015] Optionally, the microprocessor is further configured to: construct a model expression of a buffer model, wherein the buffer model is jointly constrained by a temperature delay amount, a voltage delay amount and a fixed process delay amount; acquire a set of calibration parameters, the set of calibration parameters comprising a plurality of pairs of parameter subsets of the buffer under different temperature conditions and different voltage conditions, each pair of the parameter subsets comprising a temperature calibration parameter and a voltage calibration parameter of the buffer under a corresponding working temperature and a corresponding working voltage; determine model coefficients of the model expression of the buffer model based on a preset fitting algorithm, the set of calibration parameters and the model expression of the buffer model; and generate the buffer model based on the model coefficients of the model expression.

[0016] Optionally, the microprocessor is further configured to: in response to the number of buffers contained in the initial delay line being a target number, determine a real delay time of each buffer based on the duty cycle time and the target number; acquire a working temperature and a working voltage corresponding to the real delay time of the buffer; input the real delay time, the working temperature corresponding to the real delay time and the working voltage corresponding to the real delay time into the buffer model to obtain model sample coefficients of the buffer model; and update the buffer model based on the model sample coefficients of the buffer model.

[0017] Optionally, the microprocessor is further configured to update the buffer model based on the model sample coefficients of the buffer model, comprising: acquiring current model coefficients of the buffer model that have been configured; determining final model coefficients based on the model sample coefficients and the current model coefficients; and replacing the current model coefficients with the final model coefficients to obtain an updated buffer model.

[0018] Optionally, the microprocessor is further configured to: acquire real delay times of the buffer in each re-determination operation of the total buffer quantity; and in response to real delay times of a specified consecutive number of times satisfying a time stability condition, control the clock cycle resolution circuit to stop working.

[0019] Optionally, the PWM generation circuit includes a counter, a first comparator, a second comparator, a delay unit, a second latch and a microcontroller, the delay unit includes a first delay line and a second delay line, the microcontroller is communicatively connected with the counter, the first comparator, the second comparator, the first delay line, the second delay line and the microprocessor respectively, the counter is communicatively connected with the first comparator and the second comparator respectively, the first comparator is communicatively connected with the first delay line, the second comparator is communicatively connected with the second delay line, the set end of the second latch is communicatively connected with the output end of the first delay line, and the reset end of the second latch is communicatively connected with the output end of the second delay line.

[0020] In a second aspect, an embodiment of the present application provides a clock period analysis method, applied to the microprocessor as described above, and the method comprises the following steps: inputting a preset clock signal into an initial delay line to obtain a delay signal after delay processing, the initial delay line is composed of a reference number of buffers in series; in response to the delay signal not being high, increasing the number of buffers contained in the initial delay line to delay the next clock signal, until the delay signal output by the initial delay line is high, determining that the number of buffers contained in the initial delay line is a target number, and the total delay time of the target number of buffers is equal to the duty cycle time of the clock signal; in response to the delay signal being high, determining that the reference number is the target number; determining a total buffer number based on the target number and the duty cycle time, and the total delay time of the total buffer number is equal to the clock period of the clock signal, the PWM generation circuit includes a delay unit configured to perform delay processing on the PWM signal of the PWM generation circuit; and updating the number of buffers contained in the delay unit based on the total buffer number.

[0021] In a third aspect, an embodiment of the present application provides a microprocessor, comprising a memory and a processor, the memory is connected to the processor, the processor is used to execute one or more computer programs stored in the memory, and the processor, when executing the one or more computer programs, causes the microprocessor to implement the clock period analysis method as described above.

[0022] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program includes program instructions, and the program instructions, when executed by a processor, cause the processor to execute the clock period analysis method as described above.

[0023] The PWM signal generation system provided by the embodiments of the present application can effectively solve the problems of long time consumption in determining the number of buffers and low efficiency in generating PWM in the prior art, by the cooperative design of the clock cycle analysis circuit and the PWM generation circuit. The embodiments of the present application dynamically adjust the number of buffers of the initial delay line, and adaptively determine the target number according to the state of the delay signal, thereby greatly shortening the calculation period of the total number of buffers in the PWM generation circuit, improving the parameter configuration efficiency, and avoiding the time-consuming iterative calculation in the traditional scheme. In addition, based on the logic of deriving the total number of buffers from the target number, the delay time of the buffer is accurately matched with the clock cycle, and the fine delay processing of the delay unit on the PWM signal is combined, thereby effectively improving the regulation accuracy of the PWM duty cycle, meeting the high-precision requirement of the minimum duty cycle, and making up for the defects of insufficient accuracy of the traditional circuit. The embodiments of the present application also integrate the temperature sensor and the voltage sensor, and the microprocessor can dynamically correct the characteristic deviation of the delay time of the buffer in combination with the environmental parameters, thereby enhancing the stability of the system under complex working conditions, and widening the applicable scenarios of the system in the fields of power electronics and motor control. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 An architecture schematic diagram of a PWM signal generation system provided by the embodiments of the present application is shown in FIG. 1.

[0026] Figure 2 A structure schematic diagram of a delay line provided by the embodiments of the present application is shown in FIG. 2.

[0027] Figure 3 A structure schematic diagram of a selector module provided by the embodiments of the present application is shown in FIG. 3.

[0028] Figure 4 Another architecture schematic diagram of a PWM signal generation system provided by the embodiments of the present application is shown in FIG. 4.

[0029] Figure 5 A flowchart of a clock cycle analysis method provided by the embodiments of the present application is shown in FIG. 5.

[0030] Figure 6 A structure schematic diagram of a microprocessor provided by the embodiments of the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0031] In order to make the purposes, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0032] It should be noted that the various features of the embodiments of the present application can be combined with each other, and all fall within the scope of the present application, if there is no conflict. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the order in the flowchart. Furthermore, the "first", "second", "third", etc. used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0033] In addition to the problems pointed out in the background, the inventors have found that the delay characteristics of a single buffer are easily disturbed by process conditions, working environment (such as temperature, voltage fluctuation), and further cause errors in the waveform of the generated PWM signal. In addition, when the PWM parameters (such as clock period) change, the number of buffers required in the delay line needs to be adjusted adaptively. In the scenario of working with a microprocessor scheme, the number of buffers in the delay line needs to be preconfigured by software. Especially when the PWM device operates in an extremely high or low temperature environment or a scenario with a large temperature difference, the software-level buffer number configuration work will become particularly complex, and in some scenarios, the buffer number needs to be reconfigured in each PWM cycle, which will greatly reduce the overall working efficiency of the device.

[0034] In the following, the embodiments of the present application provide a PWM signal generation system, which includes a PWM generation circuit and a clock period analysis circuit. The PWM generation circuit can be applied to a digital pulse width modulation signal circuit or an electronic device. For example, the electronic device is a switching power supply device, and the digital pulse width modulation signal circuit containing the PWM generation circuit can provide a PWM delay signal for the switching power supply device. The clock period analysis circuit can analyze the equivalent relationship between the clock period of the PWM signal and the number of buffers in the delay line, and send the target buffer number to the PWM generation circuit, so that the PWM generation circuit generates a correct PWM delay signal.

[0035] Please refer to Figure 1The clock cycle resolution circuit 100 comprises a plurality of buffers 11, a selector module 12, a first latch 13, a temperature sensor 14, a voltage sensor 15, and a microprocessor 16. The selector module 12 comprises a plurality of selection input terminals, one of which is electrically connected to the output terminal of one buffer 11. The total selection output terminal of the selector module 12 is electrically connected to the set terminal of the first latch 13. The clock terminal of the first latch 13 and the first buffer 11 are both configured to input a clock signal. The microprocessor 16 is electrically connected to each buffer 11, the selector module 12, the temperature sensor 14, the voltage sensor 15, and the PWM generation circuit 200, respectively.

[0036] The temperature sensor 14 can be a CMOS diode-based micro temperature sensor on a chip. The core reason is that it has strong process compatibility with the digital pulse width modulation signal circuit using the CMOS process, does not need to introduce additional heterogeneous processes, and has the advantages of small size, low power consumption, and wide temperature range. The specific parameters need to meet:

[0037] The temperature measurement range needs to cover the typical working scenarios of the digital pulse width modulation signal circuit, such as the industrial temperature measurement range: -40℃ to 125℃, and the automotive temperature measurement range: -40℃ to 150℃, to ensure that it can still effectively sample in extreme environments. The temperature measurement accuracy supports ±1℃ in the commonly used interval of -20℃ to 85℃ and ±2℃ in the full temperature range, avoiding delay estimation deviation caused by temperature sampling error. The sampling frequency supports 10Hz to 100Hz adjustable, and the default setting of the sampling frequency is 10Hz, which can not only reflect the temperature change in real time, such as the temperature change of 0.5℃ to 1℃ per second in the motor driving scenario, but also control the power consumption below 0.1μA. The output form adopts 10-bit digital quantity, corresponding to a temperature resolution of 0.125℃, which is directly compatible with the digital pulse width modulation signal circuit without additional AD conversion modules.

[0038] Since the delay time of the buffer is most affected by its junction temperature, and the temperature of the buffer array dense area is different from the overall environmental temperature of the PWM signal generation system, the temperature sensor 14 is arranged close to the buffer array composed of a plurality of buffers 11. In the embodiment of the present application, the buffer array is 63 special delay buffers. Symmetrical copper interconnection lines are used for wiring, with a length controlled within 100μm, to avoid temperature sampling delay caused by wiring resistance / capacitance, and to ensure that the deviation between the sampling value and the real-time temperature of the buffer is less than 0.5℃.

[0039] The voltage sensor 15 is used to monitor the supply voltage VDD of the buffer 11 and the clock cycle resolution circuit 100, typically 1.2V to 3.3V. It should be noted that the driving capability of the buffer directly depends on VDD, and if VDD increases by 10%, the delay time of the buffer 11 will decrease by 8% to 12%; if VDD decreases by 10%, the delay time will increase by 10% to 15%. The voltage sensor 15 can use an on-chip low-dropout voltage monitoring unit (LDO-based Voltage Sensor), which has the following advantages:

[0040] The response speed is μs level, such as 5μs, which can capture transient voltage fluctuations, such as power supply spikes during motor start; the measurement accuracy is ±2% within the range of 1.0V to 3.6V, which meets the accuracy requirements of delay estimation, the static power consumption is <0.5μA, the area is <0.005mm², and the area is only 5% of the buffer array area, without additional hardware cost pressure.

[0041] In order to avoid the reference deviation of voltage monitoring, the voltage sensor 15 is built-in on-chip bandgap reference source, which outputs stable 1.25V reference voltage, temperature coefficient <10ppm / ℃, which ensures the consistency of voltage measurement at different temperatures. At the same time, the sampling clock of the voltage sensor 15 and the temperature sensor 14 is synchronized, which uses a system clock divided signal, such as 1MHz divided to 1kHz, to ensure that the temperature-voltage data collected each time is the state at the same time, avoiding time sequence misplacement.

[0042] The microprocessor 16 is configured to input a preset clock signal into an initial delay line and obtain a delay signal after delay processing, and the initial delay line is composed of a reference number of buffers 11 in series. Specifically, the first buffer 11 is input with the preset clock signal, and the preset clock signal is subjected to delay processing by the reference number of buffers 11 to obtain the delay signal. The reference number can be estimated according to the delay time of the buffer 11, and it can be understood that the delay time of a single buffer is extremely short, far lower than the minimum time accuracy required by pulse width modulation. In the embodiment of the present application, the reference number is at least set to 2.

[0043] Please refer to Figure 2 , Figure 2 is a structural schematic diagram of a delay line provided by the embodiment of the present application. In the embodiment of the present application, the total number of buffers 11 in the delay line is set to 63. It should be noted that in the embodiment of the present application, the delay line is composed of 63 buffers 11 in series, and the output of each buffer 11 and the preset clock signal can obtain 64 delay signals, and the 64 delay signals are selected by the selector module 12 to output one delay signal.

[0044] Please refer to Figure 3 , Figure 3Figure 1 is a structural schematic diagram of a selector module 12 provided by an embodiment of the present application. The selector module 12 is composed of multiple four-to-one selectors. Specifically, the four-to-one selector is a selector with four selection input terminals and one output terminal. The overall architecture of the selector module 12 is divided into three layers. The total number of four-to-one selectors in the first layer level 1 is set to 16. The total number of four-to-one selectors in the second layer level 2 is set to 4. The total number of four-to-one selectors in the third layer level 3 is set to 1. The output terminal of the four-to-one selector in the third layer level 3 is connected to the set terminal of the first latch 13. It should be noted that in the embodiment of the present application, the delay line is composed of 63 buffers 11 connected in series. The output of each buffer 11 in combination with a preset clock signal can obtain 64 delay signals. The multiple output terminals of the delay line correspond one by one to the selection input terminals of the 16 four-to-one selectors in the first layer level 1. The initial delay line includes a reference number of buffers 11. After the output terminal of the initial delay line is selected by the corresponding selection input terminal of the selector module 12, the delay signal generated by the output terminal of the reference number of buffers 11 is output to the first latch 13 through the selector module 12.

[0045] For example, the preset clock signal is input to the initial delay line. The initial delay line includes a reference number of buffers 11. If the reference number is 2, the output terminal of the second buffer 11 is connected to the second selection input terminal of the first four-to-one selector in the first layer level 1 of the selector module 12. The output terminal of the first four-to-one selector in the first layer level 1 is connected to the first selection input terminal of the first four-to-one selector in the second layer level 2. The output terminal of the first four-to-one selector in the second layer level 2 is connected to the first selection input terminal of the four-to-one selector in the third layer level 3. The output terminal of the four-to-one selector in the third layer level 3 is connected to the set terminal of the first latch 13. The delay signal generated by the output terminal of the second buffer 11 is output to the first latch 13 through the above-mentioned path.

[0046] It should be noted that the embodiment of the present application completes the selection process of the delay signal through the three-layer four-to-one selector architecture, which can ensure that each delay signal passes through three four-to-one selectors for output, thereby minimizing the wiring error.

[0047] The microprocessor 16 is configured to: in response to the delay signal not being high, increase the number of buffers 11 included in the initial delay line to delay the next clock signal, until the delay signal output through the initial delay line is high, determine that the number of buffers 11 included in the initial delay line is a target number, and the total delay time of the target number of buffers 11 is equal to the duty cycle time of the clock signal; and in response to the delay signal being high, determine that the reference number is the target number.

[0048] Specifically, if the delay signal output by the initial delay line is not high, the microprocessor 16 increases the number of the buffers 11 in the initial delay line by 1, and delays the next clock signal based on the initial delay line until the delay signal output by the initial delay line is high, and determines the number of the buffers 11 in the initial delay line at this time as the target number. If the delay signal output by the initial delay line is high, the microprocessor 16 determines the reference number as the target number.

[0049] The microprocessor 16 is configured to determine the total number of buffers based on the target number and the duty cycle time, the total delay time of the total number of buffers being equal to the clock period of the clock signal, the PWM generation circuit 200 including a delay unit 21 configured to delay the PWM signal of the PWM generation circuit 200, and updating the number of the buffers 11 included in the delay unit based on the total number of buffers.

[0050] Specifically, the microprocessor 16 determines the total number of buffers based on the target number and the duty cycle time. The microprocessor 16 obtains the total number of buffers by dividing the target number by the duty cycle. In the embodiment of the application, the preset duty cycle of the clock signal is 50%, and if the target number is N, the total number of buffers is 2N.

[0051] It should be noted that the total number of buffers obtained based on different duty cycles is different when the target number is the same. For example, if the preset duty cycle of the clock signal is 25% and the target number is N, the total number of buffers is 4N.

[0052] The PWM generation circuit 200 includes a delay unit 21 configured to delay the PWM signal of the PWM generation circuit 200, and the delay unit 21 includes a delay line composed of buffers. The clock period analysis circuit 100 sends the total number of buffers to the PWM generation circuit 200, and the PWM generation circuit 200 sets the total number of buffers as the total number of buffers for which the buffers in the delay unit 21 are enabled, so that the PWM generation circuit 200 generates the required PWM delay signal.

[0053] The PWM signal generation system provided by the embodiment of the present application can effectively solve the problems of long time consumption in determining the number of buffers and low efficiency in generating PWM in the prior art through the cooperative design of the clock cycle analysis circuit 100 and the PWM generation circuit 200. The embodiment of the present application dynamically adjusts the number of buffers of the initial delay line, and adaptively determines the target number according to the delay signal state, thereby greatly shortening the calculation period of the total number of buffers in the PWM generation circuit 200, improving the parameter configuration efficiency, and avoiding the time-consuming iterative calculation in the traditional scheme. In addition, the logic of deriving the total number of buffers based on the target number realizes the accurate matching of the delay time of the buffer and the clock cycle, and in combination with the fine delay processing of the delay unit on the PWM signal, the control accuracy of the PWM duty cycle is effectively improved, the high-precision requirement of the minimum duty cycle can be met, and the defects of insufficient accuracy of the traditional circuit are made up.

[0054] In some embodiments, the microprocessor 16 is configured to input a preset clock signal into the initial delay line and obtain a delay signal subjected to delay processing, including: in response to the PWM generation circuit 200 entering a power-on state, acquiring an initial working temperature of the buffer 11 and an initial working voltage for driving the buffer to work; inputting the initial working temperature and the initial working voltage into a preset buffer model to obtain an initial estimated delay time of the buffer 11; determining a reference number based on a duty cycle time of the clock signal and the initial estimated delay time, wherein the buffer 11 with the reference number is connected in series to form the initial delay line; and inputting the preset clock signal into the initial delay line to obtain the delay signal subjected to delay processing.

[0055] Specifically, when the PWM generation circuit 200 enters the power-on state, the microprocessor 16 collects the initial working temperature of the buffer through the temperature sensor 14, and collects the initial working voltage for driving the buffer to work through the voltage sensor 15, and then inputs the initial working temperature and the initial working voltage into a preset buffer model to obtain the initial estimated delay time of the buffer 11.

[0056] It should be noted that the initial estimated delay time of the buffer 11 is not fixed, and the root cause of the fluctuation of the initial estimated delay time of the buffer 11 is the dynamic change of the PVT (Process, Temperature, Voltage) parameter. When the PVT parameter changes dramatically, the initial estimated delay time of the buffer 11 may deviate from the original benchmark instantaneously, resulting in that the clock cycle analysis circuit 100 needs to iterate multiple times to find the accurate reference number, and during which a short-term PWM duty cycle accuracy deviation occurs.

[0057] The preset buffer model is used to determine the number of the gated buffers 11 in the initial delay line, i.e., the reference number. Each pair of working temperature and working voltage corresponds to an estimated delay time of the buffer 11. It can be understood that the microprocessor 16 inputs the initial working temperature and the initial working voltage into the preset buffer model, and then the initial estimated delay time of the buffer 11 can be obtained. The microprocessor 16 determines the reference number based on the duty cycle time of the clock signal and the initial estimated delay time. Specifically, the reference number can be obtained by dividing the duty cycle time of the clock signal by the initial estimated delay time. In the embodiment of the present application, the default value of the reference number is 26 (at room temperature 25℃), i.e., the initial working temperature is 25℃. The microprocessor 16 sends the reference number to the selector module 12, and the selector module 12 selects the output end of the buffer 11 in the delay line with the reference number. For example, if the reference number is 26, the selector module 12 selects the output end of the 26th buffer 11 in the delay line. The preset clock signal is delayed by the initial delay line composed of the buffers 11 with the reference number, and a delay signal is obtained.

[0058] The embodiment of the present application integrates the temperature sensor 14 and the voltage sensor 15, establishes a buffer model, actively pre-compensates the buffer delay time, predicts the influence of the PVT parameter change on the delay in advance, directly outputs the reference number of the buffer 11 close to the real value, reduces the iteration number of the clock cycle analysis circuit 100, and improves the stability and calibration efficiency of the PWM precision in the extreme environment.

[0059] In some embodiments, the microprocessor 16 is further configured to, in response to that the PWM generation circuit 200 has output a specified number of PWM signals, acquire an intermediate working temperature of the buffer 11 and an intermediate working voltage for driving the buffer to work, and update the total buffer number based on the intermediate working temperature and the intermediate working voltage.

[0060] The specified number can be configured according to actual conditions, and in the embodiment of the application, the specified number can be set to 10. Specifically, the microprocessor 16 synchronously samples once through the temperature sensor 14 and the voltage sensor 15 every 10 PWM clock periods, and if the PWM generation circuit 200 has output 10 PWM signals, the microprocessor 16 collects the intermediate working temperature of the buffer through the temperature sensor 14, and the intermediate working temperature is the actual working temperature T_k of the buffer 11 at the Kth sampling time. At the same time, the microprocessor 16 collects the intermediate working voltage for driving the buffer 11 to work through the voltage sensor 15, and the intermediate working voltage is the actual working voltage V_k for driving the buffer 11 to work at the Kth sampling time, where k is the sampling number. The microprocessor 16 updates the total buffer number based on the intermediate working temperature and the intermediate working voltage. Specifically, the microprocessor 16 inputs the intermediate working temperature and the intermediate working voltage into a preset buffer model to obtain the estimated delay time of the buffer 11 at this time. In the embodiment of the application, the duty cycle of the preset clock signal is 50%, and the clock period of the preset clock signal is known. The microprocessor 16 updates the total buffer number according to the formula N_estk=T_clk / (2*t_buf_estk), where N_estk represents the target number of the buffer 11 at the kth sampling time, T_clk represents the clock period, and t_buf_estk represents the estimated delay time of the buffer at the kth sampling time.

[0061] In some embodiments, the microprocessor 16 is further configured to update the total buffer number based on the intermediate working temperature and the intermediate working voltage, including: inputting the intermediate working temperature and the intermediate working voltage into a buffer model to obtain an intermediate estimated delay time of the buffer 11; calculating a time difference value of the intermediate estimated delay time and the initial estimated delay time; in response to an absolute value of the time difference value being greater than or equal to a preset offset difference value, redetermining the total buffer number; and in response to the absolute value of the time difference value being less than the preset offset difference value, maintaining the total buffer number unchanged.

[0062] After each clock period ends, the microprocessor 16 detects again whether the target number of the buffer 11 deviates by 1 based on the target number N_estk of the buffer 11 at the kth sampling time, and if the deviation is less than 1, no adjustment is made; and if the deviation is greater than or equal to 1, the total buffer number is redetermined. Specifically, the microprocessor 16 collects the intermediate working temperature of the buffer through the temperature sensor 14, and the intermediate working temperature is the actual working temperature T_k of the buffer at the Kth sampling time. At the same time, the microprocessor 16 collects the intermediate working voltage for driving the buffer to work through the voltage sensor 15, and the intermediate working voltage is the actual working voltage V_k for driving the buffer to work at the Kth sampling time, where k is the sampling number.

[0063] The microprocessor 16 inputs the intermediate working temperature and the intermediate working voltage into the buffer model of the buffer 11 to obtain an intermediate estimated delay time of the buffer 11, which is an estimated delay time of the buffer 11 output by the buffer model at this time. The microprocessor 16 further calculates a time difference between the intermediate estimated delay time and the initial estimated delay time, and if an absolute value of the time difference is greater than or equal to a preset offset difference value, the total number of buffers is re-determined. Specifically, in the embodiment of the present application, the clock period is known, and a duty cycle of the clock period is 50%. The microprocessor 16 divides the clock period by twice the intermediate estimated delay time to obtain a target number N of buffers, and re-determines the total number of buffers as 2N. If the absolute value of the time difference is less than the preset offset difference value, the total number of buffers is maintained unchanged. In this way, the number of iterations of the clock period analysis circuit 100 can be reduced, and the working efficiency can be improved.

[0064] In some embodiments, the microprocessor 16 is further configured to: acquire a real-time working temperature of the buffer 11 at each clock period and a real-time working voltage for driving the buffer to work; in response to an absolute temperature difference between the real-time working temperature and a preset temperature threshold being greater than the preset temperature threshold, perform an updating operation on the total number of buffers; or in response to an absolute voltage difference between the real-time working voltage and a preset voltage threshold being greater than the preset voltage threshold, perform the updating operation on the total number of buffers.

[0065] When the microprocessor 16 detects a sudden change in PVT parameters, such as a sudden change in temperature parameters or voltage parameters, the microprocessor 16 triggers a fast pre-compensation mechanism, skips the regular sampling period, and forces an update of the delay time and the total number of buffers, thereby ensuring that the clock cycle resolution circuit 100 responds quickly to the deviation. Specifically, the microprocessor 16 obtains the real-time operating temperature of the buffer 11 at each clock cycle and the real-time operating voltage at which the buffer 11 is driven. When the absolute temperature difference between the real-time operating temperature and a preset temperature threshold is greater than the preset temperature threshold, the preset temperature threshold can be set according to the actual situation of the buffer 11, and in the embodiment of the present application, the preset temperature threshold is set to 5°C. For example, if the temperature of the buffer 11 changes by 5°C within 10 ms, the fast pre-compensation mechanism is triggered, and the real-time operating temperature and the real-time operating voltage at this time are directly input to the preset buffer model to obtain the estimated delay time of the buffer. The clock cycle is divided by twice the estimated delay time of the buffer to obtain the target number N of the buffer, and the total number of buffers is updated to 2N. Alternatively, when the absolute voltage difference between the real-time operating voltage and a preset voltage threshold is greater than the preset voltage threshold, the preset voltage threshold can be set according to the actual situation of the buffer, and in the embodiment of the present application, the preset voltage threshold is set to 0.5V. For example, if the voltage of the buffer changes by 0.5V within an instant, the fast pre-compensation mechanism is triggered, and the real-time operating temperature and the real-time operating voltage at this time are directly input to the preset buffer model to obtain the estimated delay time of the buffer 11. The clock cycle is divided by twice the estimated delay time of the buffer 11 to obtain the target number N of the buffer 11, and the total number of buffers is updated to 2N.

[0066] In some embodiments, the microprocessor 16 is further configured to construct a model expression of the buffer model, wherein the buffer model is jointly constrained by a temperature delay amount, a voltage delay amount, and a fixed process delay amount; obtain a set of calibration parameters, the set of calibration parameters including a plurality of pairs of parameter subsets of the buffer under different temperature conditions and different voltage conditions, each pair of parameter subsets including a temperature calibration parameter and a voltage calibration parameter of the buffer under a corresponding operating temperature and a corresponding operating voltage; determine model coefficients of the model expression based on a preset fitting algorithm, the set of calibration parameters, and the model expression of the buffer model; and generate the buffer model based on the model coefficients of the model expression.

[0067] Specifically, the actual delay time t_buf_act of the buffer 11 is determined by three parts: a process delay amount caused by process deviation, a temperature delay amount dependent on temperature, and a voltage delay amount dependent on voltage, and the three parts are superimposed to form the actual delay time of the buffer 11, i.e., t_buf_act = t_p + t_T(T) + t_V(V).

[0068] Wherein, t_p represents a process delay amount, the same batch of chips due to the subtle differences in process parameters, such as CMOS channel length, oxide layer thickness, the process delay amount of the buffer 11 exists deviation, which is fixed after leaving the factory and needs to be recorded through initial calibration. t_T represents a temperature delay amount, T represents a real-time value collected by the temperature sensor 14 (unit: ℃), t_T(T) is the nonlinear influence of the real-time temperature on the delay time of the buffer. t_V represents a voltage delay amount, V represents a real-time VDD value collected by the voltage sensor 15 (unit: V), t_V(V) is the nonlinear influence of the real-time voltage on the delay time of the buffer.

[0069] The model expression of the buffer model: t_buf_est = t_p + a0 + a1×T + a2×T² + a3×V+ a4×V² + a5×T×V.

[0070] Wherein, t_buf_est represents the estimated delay time of the buffer (unit: ps), a0-a5: model coefficients (unit: ps / ℃, ps / ℃ 2 , ps / V, ps / V 2 , ps / (℃ V) need to be calibrated through experiments respectively.

[0071] The microprocessor 16 obtains the calibration parameter set, specifically, the test personnel build a calibration test environment, place the chip integrated with the PWM generation system in the oven, adjust the oven temperature, which covers-40℃ to 125℃, with a step of 5℃, and at the same time adjust the power supply voltage, which covers 1.0V to 3.6V, with a step of 0.1V, construct a temperature-voltage test matrix, obtain multiple parameter subsets of the buffer 11 under different temperature conditions and different voltage conditions, each parameter subset includes the temperature calibration parameter and the voltage calibration parameter of the buffer 11 under the corresponding working temperature and the corresponding working voltage. Specifically, at each test point (T_i, V_j), the real delay time t_buf_act(i,j) of the buffer 11 is measured based on the clock cycle analysis circuit 100, and the calibration parameter set is obtained. According to the model expression of the calibration parameter set and the buffer model, the microprocessor 16 uses a preset fitting algorithm to calculate the model coefficients a0-a5 of the model expression. In the embodiment of the present application, the preset fitting algorithm is the least square method, that is, the microprocessor 16 uses the least square method to fit the parameters (T_i, V_j, t_buf_act(i,j)) of the calibration parameter set to determine the model coefficients a0-a5, and finally determine the buffer model.

[0072] It should be noted that the model coefficients a0-a5 and the process delay amount t_p are written into the non-volatile memory together, and the microprocessor 16 can directly obtain them when the clock cycle analysis circuit 100 is powered on.

[0073] In some embodiments, the microprocessor 16 is further configured to, in response to the number of the buffers 11 contained in the initial delay line being the target number, determine the real delay time of each buffer based on the duty cycle time and the target number; obtain the working temperature and the working voltage corresponding to the real delay time of the buffer; input the real delay time, the working temperature corresponding to the real delay time and the working voltage into the buffer model to obtain the model sample coefficients of the buffer model; and update the buffer model based on the model sample coefficients of the buffer model.

[0074] Specifically, the total delay time of the target number of buffers is equal to the preset duty cycle time of the clock signal. In the embodiments of the present application, the duty cycle of the clock cycle is 50%, and the clock cycle is known. When the number of the buffers 11 contained in the initial delay line is the target number, the real delay time t_buf_act of the current buffer 11 can be deduced. Specifically, the clock cycle is divided by 2 times the target number of the buffers 11 to obtain the real delay time t_buf_act of the current buffer. The microprocessor 16 fine tunes the buffer model with the real delay time t_buf_act and the corresponding working temperature and working voltage as new samples, obtains the fine-tuned model sample coefficients, and updates the buffer model according to the model sample coefficients. It should be noted that, with the continuous updating of the buffer model, the estimated delay time of the buffer 11 will be more accurate, further reducing the time deviation between the estimated delay time and the real delay time output by the model, so that the initial estimated delay time of the buffer 11 under the corresponding environment can be directly obtained after the clock cycle analysis circuit 100 is powered on, the number of iterations is reduced, the analysis time is shortened, and even the analysis is not needed.

[0075] In some embodiments, the microprocessor 16 is further configured to update the buffer model based on the model sample coefficients of the buffer model, including: obtaining the current model coefficients of the buffer model which have been configured; determining the final model coefficients based on the model sample coefficients and the current model coefficients; replacing the final model coefficients with the current model coefficients to obtain the updated buffer model.

[0076] Specifically, the microprocessor 16 obtains the current model coefficient of the buffer model from the non-volatile memory, and determines the final model coefficient based on the model sample coefficient and the current model coefficient. Specifically, the microprocessor 16 corrects the two kinds of model coefficients by using a sliding average algorithm to determine the final model coefficient. The sliding average algorithm performs weighted average on the model sample coefficient and the current model coefficient, so that the final model coefficient is closer to the real trend. Specifically, the weight value of the current model coefficient is set to β, and the weight value of the model sample coefficient is set to 1-β. In the embodiment of the present application, β is set to 0.9, that is, the final model coefficient is equal to the sum of the product of 0.9 and the current model coefficient and the product of 0.1 and the model sample coefficient. The microprocessor 16 replaces the current model coefficient with the final model coefficient to obtain the updated buffer model.

[0077] In some embodiments, the microprocessor 16 is further configured to: obtain the real delay time of the buffer 11 in each determination of the total buffer number; and control the clock period resolution circuit to stop working in response to the real delay time of a specified number of consecutive times satisfying a time stability condition.

[0078] It can be understood that the microprocessor 16 periodically updates the total buffer number. For example, the microprocessor 16 synchronously samples once every 10 PWM clock periods through the temperature sensor 14 and the voltage sensor 15, inputs the working temperature and working voltage of the buffer at this time into the buffer model, obtains the estimated delay time of the buffer 11, and determines the total buffer number based on the clock period and the estimated delay time.

[0079] Further, the microprocessor 16 obtains the real delay time of the buffer in each determination of the total buffer number. Specifically, in the embodiment of the present application, the duty cycle of the clock period is 50%, and the clock period is known. The microprocessor 16 divides the clock period by twice the target number of the buffer 11 to obtain the real delay time of the current buffer. If the average of the real delay time in the determination of the total buffer number for three consecutive times is equal to the average of the real delay time in the determination of the total buffer number for the last three consecutive times, it is determined that the external environment is stable, and the microprocessor 16 controls the clock period resolution circuit 100 to stop working.

[0080] In some embodiments, please refer to Figure 4 , Figure 4is another structure schematic diagram of a PWM generating circuit provided by an embodiment of the present application. The PWM generating circuit 200 comprises a counter 22, a first comparator 23, a second comparator 24, a delay unit 21, a second latch 25 and a microcontroller 26. The delay unit 21 comprises a first delay line 211 and a second delay line 212. The microcontroller 26 is communicatively connected with the counter 22, the first comparator 23, the second comparator 24, the first delay line 211, the second delay line 212 and the microprocessor 16 respectively. The counter 22 is communicatively connected with the first comparator 23 and the second comparator 24 respectively. The first comparator 23 is communicatively connected with the first delay line 211. The second comparator 24 is communicatively connected with the second delay line 212. The set end of the second latch 25 is communicatively connected with the output end of the first delay line 211. The reset end of the second latch 25 is communicatively connected with the output end of the second delay line 212.

[0081] Specifically, the counter 22 is communicatively connected with the microcontroller 26. The counter 22 is configured with an original counting period. The microcontroller 26 sends a clock signal to the counter 22. The counter 22 counts based on the clock signal to output a counting value.

[0082] The first comparator 23 is communicatively connected with the counter 22 and the microcontroller 26 respectively. Specifically, the first comparator 23 comprises two input ends. One input end is communicatively connected with the output end of the counter 22. The other input end is communicatively connected with the microcontroller 26. The microcontroller 26 can configure a first comparison threshold value (for example, the expression of the first comparison threshold value is "=0") for the other input end of the first comparator 23. For example, the first comparison threshold value is 0 or 1 or 2, etc. When the counter 22 starts to receive the clock signal to count, if the first comparison threshold value is 0, when the counter 22 outputs the counting value i=0, the first comparator 23 outputs a high level. When the counter 22 outputs the counting value i≠0, the first comparator 23 outputs a low level. For another example, if the first comparison threshold value is 1, when the counter 22 outputs the counting value i=0, the first comparator 23 outputs a low level. When the counter 22 outputs the counting value i=1, the first comparator 23 outputs a high level.

[0083] The second comparator 24 is connected to the counter 22 and the microcontroller 26 respectively, and specifically, the second comparator 24 includes two input ends, one of which is connected to the output end of the counter 22, and the other of which is connected to the microcontroller 26, and the microcontroller 26 can configure a second comparison threshold value (for example, the expression of the second comparison threshold value is "=NUM") for the other input end of the second comparator 24. The second comparison threshold value is greater than the first comparison threshold value, and for example, the second comparison threshold value is 5 or 6 or 7 or 8, etc. For example, if the second comparison threshold value is 8, when the counter 22 outputs the count value i=8, the second comparator 24 outputs a high level, and when the counter 22 outputs the count value i≠8, the second comparator 24 outputs a low level.

[0084] The delay unit 21 is connected to the first comparator 23 and the second comparator 24 respectively and is also controlled by the microcontroller 26, and is used to delay the output of the high level output by the first comparator 23 and the second comparator 24 respectively.

[0085] Specifically, the delay unit 21 includes a first delay line 211 and a second delay line 212, and the microcontroller 26 configures a first delay time for the first delay line 211 according to the total buffer quantity sent by the microprocessor 16. When the count value output by the counter 22 is equal to the first comparison threshold value of the first comparator 23, the first comparator 23 outputs a high level to the first delay line 211, and the first delay line 211 delays the high level by the first delay time and then outputs it to the set end of the second latch 25. The microcontroller 26 configures a second delay time for the second delay line 212. When the count value output by the counter 22 is equal to the second comparison threshold value of the second comparator 24, the second comparator 24 outputs a high level to the second delay line 212, and the second delay line 212 delays the high level by the second delay time and then outputs it to the reset end of the second latch 25.

[0086] The microcontroller 26 selects a corresponding number of buffers in the first delay line 211 according to the total buffer quantity to delay the output of the high level output by the first comparator 23, wherein the delay time of each buffer is the same, the sum of the delay times of the plurality of buffers is a total delay time, the total delay time is less than a preset clock period, and the total buffer quantity multiplied by the delay time of the buffer is equal to the first delay time.

[0087] The microcontroller 26 selects a corresponding number of buffers in the second delay line 212 according to the total buffer quantity to delay the output of the high level output by the second comparator 24, wherein the delay time of each buffer is the same, the sum of the delay times of the plurality of buffers is a total delay time, the total delay time is less than a preset clock period, and the total buffer quantity multiplied by the delay time of the buffer is equal to the second delay time.

[0088] In some embodiments, the delay unit 21 further comprises a first selector and a second selector. The first selector and the second selector are multiple-to-one selectors, for example, the first selector and the second selector are 64-to-1 selectors. For another example, the first selector and the second selector adopt the three-layer architecture of the selector module 12, each layer comprising a plurality of 4-to-1 selectors. The first selector comprises a plurality of selection input terminals and an output terminal, a channel input terminal is in communication connection with the output terminal of a buffer, and the output terminal of the first selector is in communication connection with the set terminal of the second latch 25. The output terminal of the second selector is in communication connection with the reset terminal of the second latch 25. The first selector is configured to select a corresponding number of buffers in the first delay line 211 according to the total number of buffers to delay and output the high level output by the first comparator 23. The second selector is configured to select a corresponding number of buffers in the second delay line 212 according to the total number of buffers to delay and output the high level output by the second comparator 24.

[0089] The latch 25 can be any type of latch, for example, the latch 25 comprises an SR latch, a D flip-flop, a JK latch, etc. The microcontroller 26 can control the above-mentioned devices to work cooperatively to generate a PWM signal.

[0090] As another aspect of the embodiments of the present application, the embodiments of the present application provide a clock cycle analysis method, which is applied to the microprocessor described above. Please refer to Figure 5 , Figure 5 The clock cycle analysis method provided by the embodiments of the present application comprises the following steps:

[0091] S51: input a preset clock signal into an initial delay line to obtain a delay signal processed by delay, and the initial delay line is composed of a reference number of buffers connected in series.

[0092] S52: in response to the delay signal not being a high level, increase the number of buffers contained in the initial delay line to delay the next clock signal, and when the delay signal output by the initial delay line is a high level, determine that the number of buffers contained in the initial delay line is a target number, and the total delay time of the target number of buffers is equal to the duty cycle time of the clock signal.

[0093] S53: in response to the delay signal being a high level, determine that the reference number is the target number.

[0094] S54: determine a total number of buffers based on the target number and the duty cycle time, and the total delay time of the total number of buffers is equal to the clock cycle of the clock signal, and the PWM generation circuit comprises a delay unit configured to delay the PWM signal of the PWM generation circuit.

[0095] S55: update the number of buffers contained in the delay unit based on the total number of buffers.

[0096] In step S51, the microprocessor inputs a preset clock signal into the initial delay line, and obtains a delay signal after delay processing, wherein the initial delay line is composed of a reference number of buffers in series. Specifically, the first buffer is input with the preset clock signal, and the preset clock signal is subjected to delay processing by the reference number of buffers to obtain the delay signal. The reference number can also be set to 26, which is a default number based on an initial working temperature of 25°C.

[0097] In step S52, if the delay signal output by the initial delay line is not high, the microprocessor increases the number of buffers in the initial delay line by one, and delays the next clock signal based on the initial delay line. If the delay signal output by the initial delay line is not high, the number of buffers in the initial delay line is increased by one again, until the delay signal output by the initial delay line is high, and the number of buffers in the initial delay line at this time is determined as the target number.

[0098] In step S53, if the delay signal output by the initial delay line is high, the microprocessor determines that the reference number is the target number.

[0099] In step S54, the microprocessor 16 determines the total number of buffers based on the target number and the duty cycle time. The microprocessor 16 obtains the total number of buffers by dividing the target number by the duty cycle. In the embodiment of the present application, the duty cycle of the preset clock signal is 50%, and if the target number is N, the total number of buffers can be obtained as 2N.

[0100] It should be noted that the total number of buffers obtained based on different duty cycles is different when the target number is the same. For example, if the duty cycle of the preset clock signal is 25% and the target number is N, the total number of buffers can be obtained as 4N.

[0101] In step S55, the PWM generation circuit includes a delay unit for delaying the PWM signal of the PWM generation circuit. The microprocessor sends the total number of buffers to the microcontroller of the PWM generation circuit, and the microcontroller updates the number of buffers in the delay unit according to the total number of buffers to delay the PWM signal, and finally generates the required PWM delay signal.

[0102] It should be noted that in the above various embodiments, the above steps do not necessarily have a certain order. Those skilled in the art can understand from the description of the embodiments of the present application that the above steps can have different execution orders in different embodiments, i.e., they can be executed in parallel, or exchanged, etc.

[0103] Referring to Figure 6 , Figure 6 is a structural schematic diagram of a microprocessor provided by an embodiment of the present application. The microprocessor includes one or more processors 61 and a memory 62. The memory 62 is connected to the one or more processors 61, for example, connected to the processors 61 through a bus.

[0104] The processor 61 is configured to support the microprocessor to perform corresponding functions in the methods in the above method embodiments. The processor can be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The above hardware chip can be an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0105] The memory 62 is used to store program codes and the like. The memory 62 can include volatile memory (VM), for example, random access memory (RAM); the memory 62 can also include non-volatile memory (NVM), for example, read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory can also include a combination of the above kinds of memories.

[0106] The memory 62 can be used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as program instructions / modules corresponding to the clock cycle resolution method in the embodiments of the present application. The processor 61 performs the clock cycle resolution method by running the non-volatile software programs, instructions, and modules stored in the memory, that is, implements the clock cycle resolution method provided by the above method embodiments.

[0107] The memory 62 can include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required by a function. In some embodiments, the memory 62 can optionally include a memory remotely arranged relative to the processor, which can be connected to the processor 61 through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0108] The one or more modules are stored in the memory 62, and when executed by the one or more processors 61, perform the clock cycle resolution method in any of the above method embodiments, for example, perform the method steps described in the above method embodiments.

[0109] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, the computer program includes program instructions, and the program instructions, when executed by a computer, cause the computer to perform the method described in the above embodiments.

[0110] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0111] The above disclosure is only the preferred embodiments of the present application, and of course cannot limit the scope of the rights of the present application, so the equivalent changes made according to the claims of the present application still fall within the scope of the present application.

Claims

1. A PWM signal generation system, characterized in that, The circuit includes a PWM generation circuit and a clock cycle analysis circuit. The clock cycle analysis circuit includes multiple buffers, a selector module, a first latch, a temperature sensor, a voltage sensor, and a microprocessor. The selector module includes multiple selection input terminals, one of which is electrically connected to the output terminal of a buffer. The overall selection output terminal of the selector module is electrically connected to the set terminal of the first latch. The clock terminal of the first latch and the first buffer are both configured to input a clock signal. The microprocessor is electrically connected to each buffer, the selector module, the temperature sensor, the voltage sensor, and the PWM generation circuit. The microprocessor is configured to: A preset clock signal is input into the initial delay line to obtain a delayed signal after delay processing. The initial delay line is composed of a reference number of buffers connected in series. In response to the delayed signal not being high, the number of buffers included in the initial delay line is increased to delay the next clock signal until the delayed signal output from the initial delay line is high. Then, the number of buffers included in the initial delay line is determined to be the target number, and the total delay time of the target number of buffers is equal to the duty cycle time of the clock signal. In response to the delay signal being high, the reference quantity is determined to be the target quantity; The total number of buffers is determined based on the target number and the duty cycle time. The total delay time of the total number of buffers is equal to the clock period of the clock signal. The PWM generation circuit includes a delay unit, which is configured to delay the PWM signal of the PWM generation circuit. The number of buffers contained in the delay unit is updated based on the total number of buffers, wherein updating the number of buffers contained in the delay unit based on the total number of buffers includes setting the total number of buffers to the total number of buffers in the delay unit.

2. The PWM signal generation system according to claim 1, characterized in that, The microprocessor is configured to input a preset clock signal into an initial delay line to obtain a delayed signal after delay processing, including: In response to the PWM generation circuit entering the power-on state, the initial operating temperature of the buffer and the initial operating voltage driving the buffer to work are obtained; The initial operating temperature and the initial operating voltage are input into a preset buffer model to obtain the initial estimated delay time of the buffer. The number of references is determined based on the duty cycle of the clock signal and the initial estimated delay time, wherein the buffers of the number of references are connected in series to form an initial delay line; Input the preset clock signal into the initial delay line to obtain the delayed signal after delay processing.

3. The PWM signal generation system according to claim 2, characterized in that, The microprocessor is also configured to: In response to the PWM generation circuit outputting a specified number of PWM signals, the intermediate operating temperature of the buffer and the intermediate operating voltage driving the buffer are obtained; The total number of buffers is updated based on the intermediate operating temperature and the intermediate operating voltage.

4. The PWM signal generation system according to claim 3, characterized in that, The microprocessor is also configured to update the total number of buffers based on the intermediate operating temperature and the intermediate operating voltage, including: The intermediate operating temperature and the intermediate operating voltage are input into the buffer model to obtain the intermediate estimated delay time of the buffer; Calculate the time difference between the intermediate estimated delay time and the initial estimated delay time; In response to the absolute value of the time difference being greater than or equal to a preset offset difference, the total number of buffers is re-determined; In response to the absolute value of the time difference being less than a preset offset difference, the total number of buffers remains unchanged.

5. The PWM signal generation system according to claim 3, characterized in that, The microprocessor is also configured to: The real-time operating temperature of the buffer and the real-time operating voltage that drives the buffer are obtained in each clock cycle. In response to the absolute temperature difference between the real-time operating temperature and the preset temperature threshold being greater than the preset temperature threshold, an update operation is performed on the total number of buffers; or, In response to the absolute voltage difference between the real-time operating voltage and the preset voltage threshold being greater than the preset voltage threshold, an update operation is performed on the total number of buffers.

6. The PWM signal generation system according to claim 2, characterized in that, The microprocessor is also configured to: Construct a model expression for a buffer model, wherein the buffer model is subject to the combined constraints of temperature delay, voltage delay, and a fixed process delay. Obtain a calibration parameter set, which includes multiple pairs of parameter subsets of the buffer under different temperature and voltage conditions. Each pair of parameter subsets includes the temperature calibration parameters and voltage calibration parameters of the buffer under the corresponding operating temperature and voltage. Based on the preset fitting algorithm, the calibration parameter set, and the model expression of the buffer model, the model coefficients of the model expression are determined; The buffer model is generated based on the model coefficients of the model expression.

7. The PWM signal generation system according to claim 6, characterized in that, The microprocessor is also configured to: In response to the target number of buffers included in the initial delay line, the actual delay time of each buffer is determined based on the duty cycle time and the target number; Obtain the operating temperature and operating voltage corresponding to the actual delay time of the buffer; The actual delay time, the corresponding operating temperature, and the operating voltage are input into the buffer model to obtain the model sample coefficients of the buffer model. The buffer model is updated based on the model sample coefficients of the buffer model.

8. The PWM signal generation system according to claim 7, characterized in that, The microprocessor is also configured to update the buffer model based on the model sample coefficients of the buffer model, including: Obtain the current model coefficients that have been configured for the buffer model; The final model coefficients are determined based on the model sample coefficients and the current model coefficients. The final model coefficients are used to replace the current model coefficients to obtain the updated buffer model.

9. The PWM signal generation system according to claim 2, characterized in that, The microprocessor is also configured to: Obtain the actual delay time of the buffer in each operation of re-determining the total number of buffers; In response to the actual delay time satisfying the time stability condition for a specified number of consecutive times, the clock cycle analysis circuit is controlled to stop working.

10. The PWM signal generation system according to any one of claims 1 to 9, characterized in that, The PWM generation circuit includes a counter, a first comparator, a second comparator, a delay unit, a second latch, and a microcontroller. The delay unit includes a first delay line and a second delay line. The microcontroller is communicatively connected to the counter, the first comparator, the second comparator, the first delay line, the second delay line, and the microprocessor. The counter is communicatively connected to the first comparator and the second comparator. The first comparator is communicatively connected to the first delay line, and the second comparator is communicatively connected to the second delay line. The set terminal of the second latch is communicatively connected to the output terminal of the first delay line, and the reset terminal of the second latch is communicatively connected to the output terminal of the second delay line.

11. A clock cycle analysis method, characterized in that, Applied to a microprocessor as described in any one of claims 1 to 10, the method comprises: A preset clock signal is input into the initial delay line to obtain a delayed signal after delay processing. The initial delay line is composed of a reference number of buffers connected in series. In response to the delayed signal not being high, the number of buffers included in the initial delay line is increased to delay the next clock signal until the delayed signal output from the initial delay line is high. Then, the number of buffers included in the initial delay line is determined to be the target number, and the total delay time of the target number of buffers is equal to the duty cycle time of the clock signal. In response to the delay signal being high, the reference quantity is determined to be the target quantity; The total number of buffers is determined based on the target number and the duty cycle time. The total delay time of the total number of buffers is equal to the clock period of the clock signal. The PWM generation circuit includes a delay unit, which is configured to delay the PWM signal of the PWM generation circuit. The number of buffers contained in the delay unit is updated based on the total number of buffers, wherein updating the number of buffers contained in the delay unit based on the total number of buffers includes setting the total number of buffers to the total number of buffers in the delay unit.

12. A microprocessor, characterized in that, The device includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, and the processor, when executing the one or more computer programs, causing the microprocessor to implement the clock cycle parsing method as described in claim 11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the clock cycle parsing method as described in claim 11.

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