Digital noise coupling continuous time sigma-modulator based on split channel CTSAR

Abstract

A digital noise coupling continuous time sigma-modulator based on a split-path CTSAR comprises a loop filter, a split-path CTSAR quantizer and a digital-to-analog converter (DAC) arranged between an input end and an output end, wherein the splitting path CTSAR quantizer feeds back the quantization result of the first X bits to the DAC in one period and takes the quantization result of the first X bits as the output of the modulator at the same time, and the residual N-X bits are used as own digital noise coupling to quantize the residual voltage. Through decomposition processing of a loop filter output path and a capacitor path of a charge redistribution type digital-to-analog converter (CDAC), power consumption is further saved on the premise that a driving buffer is not needed.

Description

Technical Field

[0001] This invention relates to a technology in the field of analog-to-digital conversion, specifically a continuous-time Σ-Δ modulator for a split-path continuous-time successive approximation (CTSAR) quantizer that applies digital noise coupling technology. Background Technology

[0002] In existing continuous-time Σ-Δ modulators, the quantizers are mostly discrete-time successive approximation (DTSAR) quantizers. These quantize residual quantization errors by consuming excess timing data for digital noise coupling techniques. The resulting delay, combined with the inherent delay of the DTSAR quantizer, introduces significant excessive loop delay (ELDC) in the loop. Addressing this delay requires dedicated ELDC compensation, leading to additional hardware overhead and power consumption. Furthermore, to save power, the final stage of the loop filter can use a transconductance-capacitor (Gm-C) integrator. However, since the Gm-C integrator operates in open-loop mode, it cannot drive the charge redistribution digital-to-analog converter (CDAC) of the successive approximation (SAR) quantizer. To solve this problem, an output buffer needs to be added after the Gm-C integrator to drive the SAR quantizer's CDAC, resulting in additional hardware overhead and power consumption. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes a digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR. By combining a CTSAR quantizer with digital noise coupling technology, performance is significantly improved without introducing ELDC. Furthermore, by decomposing the output path of the loop filter and the output path of the CDAC, power consumption is further reduced without the need for a drive buffer.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR, comprising: a loop filter, a split-path CTSAR quantizer, and a digital-to-analog converter (DAC) disposed between the input and output terminals, wherein: the split-path CTSAR quantizer feeds back the first X quantization results to the DAC in one cycle and uses the first X quantization results as the output of the modulator, and uses the remaining NX bits as its own digital noise coupling to quantize the residual voltage, wherein: N>X>0.

[0006] The split-path CTSAR quantizer includes a multi-input port comparator, a digital logic circuit, and a CDAC. The two non-inverting inputs of the multi-input port comparator are connected to the output of the CDAC and the output of the loop filter, respectively. The inverting input is grounded, and the output is connected to the digital logic circuit. The digital logic circuit outputs X bits of the quantization comparison result to the DAC and modulator output, and controls the switching of the first X bits of the CDAC and the outputs of NX bits to the last NX bits of the CDAC used for digital noise coupling technology according to specific logic.

[0007] The loop filter described above uses a Gm-C integrator as its last stage.

[0008] Technical effect

[0009] This invention significantly improves the noise shaping order of the system and enhances the signal-to-noise ratio and other performance characteristics by employing a split-path CTSAR quantizer in a continuous-time Σ-Δ modulator and introducing digital noise coupling technology, while simultaneously saving power consumption and hardware overhead. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the system of the present invention;

[0011] Figure 2 This is a schematic diagram of the split-path CTSAR quantizer structure;

[0012] Figure 3 This is a time allocation diagram of the quantizer over a full sampling period;

[0013] Figure 4 This is a schematic diagram of the state of the SAR quantizer after the first sub-cycle of the quantization phase in an example embodiment.

[0014] Figure 5 This is a schematic diagram of the state of the SAR quantizer after the digital noise coupling stage in an example embodiment;

[0015] Figure 6 This is a schematic diagram of the first half of the reset phase of the SAR quantizer in the second sampling cycle, as shown in the example.

[0016] Figure 7 This is a schematic diagram of the state of the SAR quantizer in the second half of the reset phase of the second sampling cycle, as shown in the example.

[0017] Figure 8 The output spectrum of a split-path CTSAR quantizer employing 8-bit digital noise coupling technology is shown.

[0018] Figure 9 The output spectrum of a split-path DTSAR quantizer employing 8-bit digital noise coupling technology is shown.

[0019] Figure 10 The output spectrum of a split-path CTSAR quantizer using a 5-bit quantizer without introducing digital noise coupling technology is shown. Detailed Implementation

[0020] like Figure 1 As shown in the figure, this embodiment relates to a digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR, which includes: a loop filter with a Gm-C integrator as the last stage, an N-bit split-path CTSAR quantizer, and an X-bit digital-to-analog converter (DAC) disposed between the input and output for feedback.

[0021] like Figure 2 As shown, the split-path CTSAR quantizer includes: a multi-input port comparator, a digital logic circuit, and an N-bit charge redistribution digital-to-analog converter (CDAC). The two non-inverting inputs of the multi-input port comparator are connected to the output of the CDAC and the output of the loop filter, respectively. The inverting input is grounded, and the output is connected to the digital logic circuit. The digital logic circuit outputs the first X bits of the multi-input port comparator's comparison results to the system output and the X-bit DAC, respectively, and performs real-time control of the CDAC's switching based on the comparison results according to specific logic.

[0022] In this embodiment, N is 8 and X is 5.

[0023] like Figure 2 As shown, the CDAC includes: a quantization section of the first X bits and a digital noise coupling section of the last NX bits, which are respectively connected to positive and negative reference voltages. Each bit in the quantization section and the digital noise coupling section includes two sets of capacitors with a capacitance value of binary weighted size. Each capacitor is controlled by a pair of switches connected to digital logic circuits.

[0024] In this embodiment, the capacitance values ​​of the capacitors in the 8-bit CDAC are 128C, 64C, 32C, 16C, 8C, 4C, 2C, and 1C from the highest to the lowest bit. The last group of CDACs with a capacitance value of 1C is only used to supplement the sum of the total capacitance of the single-sided CDAC to 256C with a binary weight and participate in charge redistribution, where C is the capacitance value per unit capacitance.

[0025] Half of the two sets of capacitors, i.e., the upper half of the CDAC, is fixedly connected to the positive reference voltage (V) via a switch. refp The other half of the capacitor, i.e., the lower half of the CDAC, is fixedly connected to the negative reference voltage (V) via a switch. refm The positive and negative reference voltages are at opposite levels, i.e., V refp +V refm =0.

[0026] like Figure 3 As shown, the digital logic circuit controls the switching of each capacitor to achieve reset, quantization, and digital noise coupling within a sampling cycle, specifically including:

[0027] Step 1: The reset phase during the first sampling cycle of the quantizer's operation differs from subsequent reset phases. The on / off states of the CDAC switches during the reset phase of the first sampling cycle are as follows: Figure 2 As shown. All switches for the upper half of the CDAC are connected to Vrefp, and all switches for the lower half of the CDAC are connected to V... refm The CDAC output is connected to ground potential (GND). The total charge stored at the CDAC output node... for: = =0.

[0028] Step 2: At the start of the quantization phase, the CDAC output is disconnected from ground (GND) until the next reset phase. During this time, the CDAC output node is floating, and the node voltage remains at ground potential as before the disconnection. According to the principle of charge conservation, the total charge on this node remains unchanged before and after the switch is opened, i.e., the total charge is still 0. Let the output voltage of the loop filter be V. lpf The CDAC output voltage is V. cdac In the first sub-cycle of the quantization phase, that is Figure 3 When the 128C capacitance CDAC switch shown begins its set phase, the multi-input port comparator will connect V to the two positive input terminals respectively. lpf With V cdac The summation is compared with the ground potential connected to the negative input terminal. When V lpf If the value is greater than 0, then the comparison process is V. lpf +V cdac When the value is greater than 0, the multi-input port comparator outputs a high digital level. The digital logic circuit stores this voltage result and uses a control switch to change the upper half of the 128C capacitance CDAC from a value that is equal to 0. Connected to switch to Connected, such as Figure 4 As shown. Since the output node of the CDAC is in a floating state, according to the principle of charge conservation, the total charge on this node remains unchanged before and after disconnection, that is, the total charge is still 0. After solving the setting problem = / 2. Conversely, when V lpf If <0, then the comparison process is V lpf + When the value is less than 0, the multi-input port comparator outputs a low digital level. The digital logic circuit stores this voltage result and uses a control switch to change the lower half of the 128C capacitance CDAC from a low level to a low level. Connected to switch to Connected, by applying the principle of charge conservation, the result after setting can be obtained. = / 2, which means - For V lpf The initial approximation involves the quantizer quantizing the most significant bit of the loop filter output. After the first sub-cycle of the quantization phase is set... = / 2, the second sub-cycle of the quantification phase, i.e. Figure 4 When the 64C capacitance CDAC switch shown begins its set phase, the same operation occurs: the multi-input port comparator will connect the V values ​​of the two positive input terminals respectively. lpf and The summation is compared with the ground potential connected to the negative input terminal. When V lpf + When the value is >0, the multi-input port comparator outputs a high potential. The digital logic circuit stores this potential result and uses a control switch to change the upper half of the 64C capacitance CDAC from a value that is equal to or higher than the value of the input multiplier. Connected to switch to Connected, similarly according to the charge conservation equation, we have 0, the solution is = / 4. Implementation - For V lpf To further approximate the output, the quantizer performs quantization on the second-highest bit of the loop filter output. Following the same logic operation, this continues until the fifth sub-cycle of the quantization phase, i.e., after the 8C capacitor value CDAC setting phase is completed. For V lpf It achieved five successive approximations, when for / 32, assuming the quantizer has completed the output V of the loop filter. lpf 5-bit quantization, quantization error =V lpf -(- / 32), at this point, the digital logic circuit outputs the stored 5-bit comparison result to the system output and DAC. The loop delay is only one quantization sub-cycle, requiring no ELDC compensation.

[0029] Step 3: The digital noise coupling stage begins. The quantizer operates according to the same logic as in the quantization stage. The digital logic circuit stores the results of three comparisons and sets the three sets of CDACs used for digital noise coupling. The difference is that this stage is... =- / 32 initial state for V lpf By approximating successively, when the final = / 256, this process- The changed value is the quantization error three-dimensional quantization value The size of this value in this example At this time, the conduction states of each switch of the CDAC are as follows: Figure 5 As shown. Afterwards, the quantizer enters a new reset phase to prepare for the quantization phase of the next cycle. At the beginning of this phase, the digital logic circuit reverses the switching state of the noise-coupled part, that is, it reverses the switching state of the noise-coupled part. Connected switches switch to Connected with Connected switches switch to Connected, the switches of all upper-side CDACs in the five CDACs used for the quantization loop filter output are connected. All lower half CDAC switches connected The CDAC output is connected to ground potential, such as... Figure 6 As shown. After all CDAC capacitors are fully charged, the CDAC output is disconnected from the ground. In the noise coupling section, the switches of all upper-side CDACs are connected. All lower half CDAC switches connected ,like Figure 7 As shown. According to the CDAC output node charge conservation equation, we have... Solving for = *7 / 256= ,for- In other words, it was subtracted from the previous cycle. That is, the first-order digital noise coupling transfer function (1- was implemented before the quantization stage began.) Therefore, following the above behavior, the next cycle's quantization phase and digital noise coupling phase proceed, repeating in a continuous cycle.

[0030] The digital logic circuit stores the digital code value of the comparison result of the multi-input port comparator and outputs the stored 5-bit digital code of the comparison result to the system output terminal and DAC when the quantization stage is completed. According to the above logic, the switching of CDAC and the on / off of the switch connected to CDAC output node are controlled during the reset stage, quantization stage and digital noise coupling stage.

[0031] Through specific practical experiments, an ideal simulation model was built in Virtuoso, with a loop filter order of 2 and an oversampling rate of 20. Figure 8The image shows the 8-bit split-path CTSAR quantizer used in this embodiment. The first 5 bits are used to quantize the loop filter output, and the last 3 bits are used for the system output spectrum of digital noise coupling. Figure 9 The image shows the output spectrum of a system using an 8-bit split-path DTSAR quantizer, where the first 5 bits are used to quantize the loop filter output and the last 3 bits are used for digital noise coupling. Figure 10 The figure shows the output spectrum of a system using a 5-bit split-path CTSAR quantizer and noiseless coupling technology.

[0032] Simulation comparison clearly shows that, with the same quantizer and quantization bit depth, the graphs obtained using digital noise coupling technology are similar to those obtained using digital noise coupling technology. Figure 9 The signal-to-noise ratios were 93.82 dB and 98.29 dB, respectively, both significantly better than those without digital noise coupling technology. Figure 10 78dB. Additionally, it can be seen that... Figure 9 Because a DTSAR quantizer is used, there is a significant loop delay, resulting in a spike in the output spectrum around 5MHz, which affects loop stability. In contrast, the output spectrum of this embodiment is... Figure 8 The absence of spikes at high frequencies indicates that the loop delay did not significantly alter the noise transfer function, and the loop stability remained unaffected.

[0033] Compared with existing technologies, this invention combines the advantages of low latency of CTSAR quantizer and easy implementation of digital noise coupling technology, improves noise shaping effect without consuming additional loop delay, saves hardware overhead and power consumption, and splits the loop filter output path and CDAC output, respectively connected to the positive input of the multi-input port comparator. The output of the loop filter does not need to drive the CDAC capacitor, so there is no need for an output buffer, thus saving power consumption and hardware overhead.

[0034] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR, characterized in that, include: The loop filter, the split-path CTSAR quantizer, and the digital-to-analog converter (DAC) located between the input and output terminals are connected in sequence. The split-path CTSAR quantizer feeds back the first X quantization results to the DAC in one cycle and uses the first X quantization results as the output of the modulator. It uses the remaining NX bits as its own digital noise coupling to quantize the residual voltage, where N>X>0.

2. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 1, characterized in that, The split-path CTSAR quantizer includes a multi-input port comparator, a digital logic circuit, and a CDAC. The two non-inverting inputs of the multi-input port comparator are connected to the output of the CDAC and the output of the loop filter, respectively. The inverting input is grounded, and the output is connected to the digital logic circuit. The digital logic circuit outputs X bits of the quantization comparison result to the DAC and modulator output, and controls the switching of the first X bits of the CDAC and the outputs of NX bits to the last NX bits of the CDAC used for digital noise coupling technology according to specific logic.

3. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 1, characterized in that, The loop filter described above uses a Gm-C integrator as its last stage.

4. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 1, characterized in that, The CDAC includes: a quantization section of X bits connected to positive and negative reference voltages respectively, and a digital noise coupling section of NX bits. Each bit in the quantization section and the digital noise coupling section includes two sets of capacitors with a binary weighted value. Each capacitor is controlled by a pair of switches connected to digital logic circuits.

5. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 1 or 4, characterized in that, In the CDAC, one half of the two sets of capacitors, i.e. the upper half of the CDAC, is fixedly connected to a positive reference voltage via a switch; the other half of the capacitors, i.e. the lower half of the CDAC, is fixedly connected to a negative reference voltage via a switch, and the positive and negative reference voltages have opposite values. The digital logic circuit controls the switching of each capacitor, realizing reset, quantization, and digital noise coupling within a sampling cycle.

6. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 5, characterized in that, During the reset, all switches of the upper half of the CDAC are connected to V. refp All lower-side CDAC switches are connected to V. refm The CDAC output is connected to ground potential (GND), and the total charge stored at the CDAC output node is... for: = =0.

7. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 5, characterized in that, The quantization mentioned refers to the following: the CDAC output is disconnected from ground (GND) until the next reset phase. During this time, the CDAC output node is in a floating state, and the node voltage remains at the ground potential before disconnection. The output voltage of the loop filter is V. lpf The CDAC output voltage is V. cdac In the first sub-cycle of the quantization phase, the multi-input port comparator will connect the V values ​​of the two positive inputs respectively. lpf With V cdac The summation is then compared with the ground potential connected to the negative input terminal: When V lpf If the value is greater than 0, then the comparison process is V. lpf +V cdac When the value is greater than 0, the multi-input port comparator outputs a high digital level. The digital logic circuit stores this voltage result and uses a control switch to change the upper half of the 128C capacitance CDAC from a value that is equal to 0. Connected to switch to Since the total charge is still 0, when connected, we have... After solving the setting problem = / 2; Conversely, when V lpf If <0, then the comparison process is V lpf + When the value is less than 0, the multi-input port comparator outputs a low digital level. The digital logic circuit stores this voltage result and uses a control switch to change the lower half of the 128C capacitance CDAC from a low level to a low level. Connected to switch to Connect them, and solve for the set bit. = / 2, which means - For V lpf The initial approximation is achieved by the split-path CTSAR quantizer, which quantizes the highest bit of the loop filter output. After the first sub-cycle of the quantization phase is set = / 2, at the start of the second sub-cycle of the quantization phase, i.e., the setting phase of the 64C capacitance CDAC switch, the multi-input port comparator will connect the V values ​​of the two positive input terminals respectively. lpf and The summation is then compared with the ground potential connected to the negative input terminal: When V lpf + When the value is >0, the multi-input port comparator outputs a high potential. The digital logic circuit stores this potential result and uses a control switch to change the upper half of the 64C capacitance CDAC from a value that is equal to or higher than the value of the input. Connected to switch to If connected, then 0, the solution is = / 4, to achieve - For V lpf To further approximate the target, the split-path CTSAR quantizer achieves the second-highest bit quantization of the loop filter output. Following the same logical operation, this continues until the fifth sub-cycle of the quantization phase, i.e., after the 8C capacitor value CDAC setting phase is completed. For V lpf It achieved five successive approximations, when for / 32, assuming the split-path CTSAR quantizer completes the output V of the loop filter. lpf 5-bit quantization, quantization error =V lpf -(- / 32), at this time the digital logic circuit outputs the stored 5-bit comparison result digital code to the system output terminal and DAC.

8. The digital noise-coupled continuous-time Σ-Δ modulator based on split-path CTSAR according to claim 5, characterized in that, The aforementioned digital noise coupling refers to: storing the results of three comparisons through digital logic circuits and setting three sets of CDACs used for digital noise coupling, and then... =- / 32 initial state for V lpf By approximating successively, when the final = / 256, this process- The changed value is the quantization error three-dimensional quantization value ,Right now Then, the split-path CTSAR quantizer enters a new reset phase to prepare for the quantization phase of the next cycle. At the beginning of this phase, the digital logic circuit reverses the switching state of the noise-coupled part, that is, it reverses the switching state of the noise-coupled part. Connected switches switch to Connected with Connected switches switch to Connected, the switches of all upper-side CDACs in the five CDACs used for the quantization loop filter output are connected. All lower half CDAC switches connected The CDAC output is connected to ground potential. Once all CDAC capacitors are fully charged, the CDAC output is disconnected from ground potential. The switches of all upper-side CDACs in the noise coupling section are connected. All lower half CDAC switches connected According to the CDAC output node charge conservation equation, we have Solving for = *7 / 256= ,for- In other words, it was subtracted from the previous cycle. That is, the first-order digital noise coupling transfer function (1- was implemented before the quantization stage began.) ; Therefore, following the above behavior, the next cycle of quantization and digital noise coupling will proceed, and this process will continue indefinitely.

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