Semiconductor process method
By optimizing the multilayer film structure and pulse-mode etching process, the imbalance between the core and non-core regions in the SADP process was solved, thereby improving the quality and etching effect of semiconductor devices.
Patent Information
- Application Number
- CN202511103889.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-12-12
AI Technical Summary
Traditional photolithography cannot meet the miniaturization requirements of semiconductor devices. In the SADP process, there is an imbalance between the core area and non-core area in terms of critical dimensions and etching depth, which affects the device quality.
By employing a multilayer film structure and a pulsed etching process, the bias power and gas combination are optimized through longitudinal and transverse etching steps to control the etching rate and selectivity, thereby reducing imbalance and depth loading effects.
It improves the imbalance between the core area and the non-core area, thereby enhancing the quality and etching effect of semiconductor devices.
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Figure CN121123114A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor process method. BACKGROUND
[0002] In the field of semiconductor, plasma etching technology is widely used in large-scale integrated circuits to realize the pattern transfer from photoresist to wafer and complete the construction of semiconductor devices. However, with the continuous pursuit of processing performance and computing power, the size of semiconductor devices is continuously miniaturized, and the traditional photolithography technology has been unable to meet the needs of chip manufacturing. SADP (Self-Aligned Double Patterning) process emerges as a kind of advanced multiple photolithography technology.
[0003] SADP process refers to using self-alignment technology to multiply the pattern density by one-time photolithography combined with non-photolithography process. The core is to achieve the reduction of feature size by means of spacer, so as to realize higher line width resolution. However, SADP process is affected by factors such as critical dimension (CD), aperture ratio, process recipe, etc. The core region and non-core region will produce deviation in critical dimension, etching depth, etc., resulting in larger imbalance (IMB), which ultimately affects the device structure and reduces the quality of the device. SUMMARY
[0004] The purpose of the present application is to provide a semiconductor process method to improve the technical problem of imbalance between the core region and the non-core region in the related art, which affects the quality of the semiconductor device.
[0005] The semiconductor process method provided by the present application comprises:
[0006] A film layer structure is provided, which comprises a silicon oxynitride film layer, a carbon film layer and a silicon oxide film layer. The carbon film layer has a plurality of and is arranged on the upper surface of the silicon oxynitride film layer. The silicon oxide film layer comprises a first silicon oxide film layer on the upper surface of the carbon film layer, a side wall film layer on the side of the carbon film layer and a second silicon oxide film layer on the upper surface of the silicon oxynitride film layer.
[0007] In the first etching step, the first silicon oxide film layer and the second silicon oxide film layer are etched longitudinally to expose the upper surface of the carbon film layer and the upper surface of the silicon oxynitride film layer below the second silicon oxide film layer, and a part of the thickness of the side wall film layer is etched transversely. In the process, the bias power is in pulse mode.
[0008] In the second etching step, the carbon film layer is etched to expose the silicon oxynitride film layer below the carbon film layer, and the side wall film layer is retained.
[0009] The third etching step involves etching the silicon oxynitride film layer using the sidewall film layer as a mask.
[0010] Furthermore, in the first etching step, the excitation power ranges from 400 to 800 W, the bias power ranges from 25 to 100 W, the pulse frequency of the bias power ranges from 100 to 500 Hz, and the pulse percentage ranges from 15% to 50%.
[0011] Furthermore, in the first etching step, the process gas includes CF4 and CHF3, wherein the flow rate of CF4 is in the range of 50 to 300 sccm and the flow rate of CHF3 is in the range of 50 to 200 sccm.
[0012] Furthermore, in the first etching step, the process pressure ranges from 5 to 25 mT, the process temperature ranges from 30 to 80 °C, and the process time ranges from 20 to 120 s.
[0013] Furthermore, in the second etching step, the bias power is 0.
[0014] Furthermore, in the second etching step, the process gas includes O2 and N2, wherein the flow rate of O2 ranges from 100 to 300 sccm and the flow rate of N2 ranges from 50 to 200 sccm.
[0015] Furthermore, in the second etching step, the process pressure ranges from 5 to 30 mT, the process temperature ranges from 30 to 80 °C, the excitation power ranges from 800 to 1400 W, and the process time ranges from 40 to 80 s.
[0016] Furthermore, in the third etching step, the excitation power ranges from 300 to 600 W, and the bias power ranges from 50 to 200 W.
[0017] Furthermore, in the third etching step, the process gases include CHF3, SF6 and N2, wherein the flow rate of CHF3 is in the range of 100 to 300 sccm, the flow rate of SF6 is in the range of 5 to 50 sccm, and the flow rate of N2 is in the range of 50 to 300 sccm.
[0018] Furthermore, in the third etching step, the process pressure ranges from 5 to 20 mT, the process temperature ranges from 25 to 40 °C, and the process time ranges from 5 to 30 s.
[0019] The semiconductor process method provided by this invention can produce the following beneficial effects:
[0020] The semiconductor process method provided by the present invention optimizes the process formula and adopts a pulse mode for the bias power in the first etching step, that is, the etching step for the silicon oxide film layer.
[0021] When the bias power is turned on during the cycle, it can enhance the physical bombardment of the plasma on the silicon oxide film, accelerate the longitudinal etching rate and reduce the transverse etching rate. This can accelerate the etching rate of the first silicon oxide film on top of the carbon film and the second silicon oxide film above the silicon oxynitride film, and reduce the etching rate of the sidewall films on both sides of the non-core area. In this way, the depth loading effect caused by the sidewall films being transversely etched into place, i.e., pushed into place, while the second silicon oxide film still has residue can be reduced.
[0022] When the bias power is off during the cycle, the plasma mainly performs lateral etching on the sidewall films on both sides of the non-core region, while the longitudinal etching of the second silicon oxide film is weakened. This can both increase the critical size of the non-core region and reduce the critical size deviation between the core region and the non-core region, and control the loss of the silicon oxynitride film, thereby controlling the depth loading effect caused by the loss of the silicon oxynitride film. Ultimately, it can improve the imbalance generated during the etching process of the silicon oxide film and improve the quality of semiconductor devices. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0024] Figure 1 A flowchart illustrating a semiconductor process method provided in an embodiment of the present invention;
[0025] Figure 2 The film structure prior to implementing the semiconductor process method provided in the embodiments of the present invention;
[0026] Figure 3 The film structure after the first etching step of the semiconductor process method provided in the embodiments of the present invention;
[0027] Figure 4 The film structure after the second etching step of the semiconductor process method provided in the embodiments of the present invention;
[0028] Figure 5 The film structure after the third etching step of the semiconductor process method provided in the embodiments of the present invention.
[0029] Explanation of reference numerals in the attached figures:
[0030] 100 - oxynitride film; 200 - carbon film; 300 - silicon oxide film; 310 - first silicon oxide film; 320 - sidewall film; 330 - second silicon oxide film. Detailed Implementation
[0031] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0032] In the SADP process of related technologies, when the silicon oxide film layer at the top of the mandrel region is opened to expose the carbon film layer 200, the silicon oxide film layer in the non-mandrel region is usually opened simultaneously, exposing the silicon oxynitride film layer 100. The critical dimension difference between the mandrel region and the non-mandrel region is mainly optimized by controlling the etching time. Specifically, this is achieved by controlling the lateral or transverse etching of the sidewall spacers (sidewall films 320) on both sides of the non-mandrel region. However, when the critical dimension of the non-mandrel region is significantly smaller than that of the mandrel region, more etching time is required to laterally etch the sidewall spacers in the non-mandrel region to increase its critical dimension. However, this can easily damage the silicon oxynitride film layer in the non-mandrel region, leading to a depth loading effect after the carbon film layer is removed, which affects the subsequent etching effect.
[0033] To address the above issues, this embodiment provides a semiconductor process method that can improve the critical size differences and depth loading effects between the core region and the non-core region during SADP etching, thereby improving the imbalance between the core region and the non-core region, and further reducing the adverse effects of the imbalance on the semiconductor device structure and improving the quality of the semiconductor device.
[0034] The semiconductor process method provided in this embodiment, such as Figure 1 As shown, and in combination Figures 2 to 5 As shown, the semiconductor process includes:
[0035] S100, providing a film structure, the film structure including a silicon oxynitride film 100, a carbon film 200 and a silicon oxide film 300, the carbon film 200 having a plurality of spaced carbon films 100, the silicon oxide film 300 including a first silicon oxide film 310 located on the upper surface of the carbon film 200, a sidewall film 320 located on the side of the carbon film 200 and a second silicon oxide film 330 located on the upper surface of the silicon oxynitride film 100;
[0036] S200, First etching step, longitudinal etching of the first silicon oxide film layer 310 and the second silicon oxide film layer 330 to expose the upper surface of the carbon film layer 200 and the upper surface of the silicon oxynitride film layer 100 below the second silicon oxide film layer 330, and transverse etching of part of the thickness of the sidewall film layer 320; during the process, the bias power is in pulse mode.
[0037] S300, second etching step, etching carbon film layer 200 to expose silicon oxynitride film layer 100 below carbon film layer 200, while retaining sidewall film layer 320;
[0038] S400, the third etching step, using the sidewall film layer 320 as a mask, etch the silicon oxynitride film layer 100.
[0039] The semiconductor process method provided in this embodiment optimizes the process formulation. In the first etching step, that is, the etching step for the silicon oxide film layer 300, the bias power adopts a pulse mode.
[0040] When the bias power is turned on during the cycle, it can enhance the physical bombardment of the silicon oxide film 300 by the plasma, accelerate the longitudinal etching rate and reduce the transverse etching rate. This can accelerate the etching rate of the first silicon oxide film 310 (i.e., the silicon oxide film in the core region) on top of the carbon film 200 and the second silicon oxide film 330 (i.e., the silicon oxide film in the non-core region) above the silicon oxynitride film 100, and reduce the etching rate of the sidewall films 320 on both sides of the non-core region. In this way, the depth loading effect caused by the sidewall film 320 being transversely etched into place, i.e., pushed into place, while the second silicon oxide film 330 still has residue can be reduced.
[0041] When the bias power is off during the cycle, the plasma mainly performs lateral etching on the sidewall film 320 on both sides of the non-core region, while the longitudinal etching on the second silicon oxide film 330 is weakened. This can both increase the critical size of the non-core region and reduce the critical size deviation between the core region and the non-core region, and control the loss of the silicon oxynitride film 330, thereby controlling the depth loading effect caused by the loss of the silicon oxynitride film 330. Ultimately, this can improve the imbalance generated during the etching of the silicon oxide film 300 and improve the quality of the semiconductor device.
[0042] Specifically, in this embodiment, in the first etching step, the excitation power ranges from 400 to 800 W, the bias power ranges from 25 to 100 W, the pulse frequency range of the bias power ranges from 100 to 500 Hz, and the pulse ratio ranges from 15% to 50%. Preferably, the excitation power range can be 550 to 650 W, the bias power range can be 50 to 75 W, the pulse frequency range of the bias power can be 250 to 350 Hz, and the pulse ratio range can be 25% to 40%. In this step, the high-power excitation power is paired with the low-power bias power. The high-power excitation power can achieve a strong chemical etching effect, while the bias power, although relatively low compared to the excitation power, is not excessively low. Therefore, when the bias power is turned on within the cycle, it can effectively enhance the physical bombardment of the plasma, accelerate the longitudinal etching rate, and reduce the lateral etching rate. In addition, it should be noted that the pulse frequency and pulse ratio of the bias power can be adjusted according to specific needs. For example, when the thickness of the sidewall film layer 320 that needs to be pushed laterally is small, the pulse ratio can be increased to reduce lateral etching while keeping the pulse frequency unchanged.
[0043] In the first etching step of this embodiment, the process gases include CF4 and CHF3, wherein the flow rate of CF4 ranges from 50 to 300 sccm, and the flow rate of CHF3 ranges from 50 to 200 sccm. Compared with the carbon film layer 200 and the silicon oxynitride film layer 100, the combination of CF4 and CHF3 with varying process parameters can achieve a higher etching rate for silicon oxide, which is beneficial for the plasma etching of the silicon oxide film layer 300.
[0044] Furthermore, in the first etching step of this embodiment, the process pressure ranges from 5 to 25 mT, the process temperature ranges from 30 to 80°C, and the process time ranges from 20 to 120 s. Preferably, the process pressure range can be 10 to 20 mT, the process temperature range can be 50 to 60°C, and the process time can be 60 to 80 s.
[0045] Specifically, in this embodiment, the bias power is 0 in the second etching step, that is, the lower electrode or bias electrode is turned off during the removal of the carbon film layer 200. This setting can reduce longitudinal etching, thereby further avoiding the loss of the silicon oxynitride film layer 100.
[0046] In the second etching step of this embodiment, the process gases include O2 and N2, wherein the flow rate of O2 ranges from 100 to 300 sccm, and the flow rate of N2 ranges from 50 to 200 sccm. Preferably, the flow rate of O2 can range from 150 to 250 sccm, and the flow rate of N2 can range from 100 to 150 sccm. The combination of O2 and N2 can accelerate the etching reaction and significantly improve the selectivity of the carbon film layer 200 to the silicon oxide film layer 300 and the silicon oxynitride film layer 100, avoiding the loss of the silicon oxynitride film layer 100. At the same time, it also helps to remove residues and byproducts and keep the reaction chamber clean.
[0047] In the second etching step of this embodiment, the process pressure ranges from 5 to 30 mT, the process temperature ranges from 30 to 80°C, the excitation power ranges from 800 to 1400 W, and the process time ranges from 40 to 80 s. Preferably, the process pressure range can be 10 to 20 mT, the process temperature range can be 50 to 60°C, the excitation power range can be 1000 to 1200 W, and the process time range can be 50 to 60 s. In this step, a higher excitation power enhances the etching of the carbon film layer 200, thereby increasing the etching rate of the carbon film layer 200.
[0048] Specifically, in this embodiment, in the third etching step, the excitation power ranges from 300 to 600 W, and the bias power ranges from 50 to 200 W. Preferably, the excitation power range can be 400 to 500 W, and the bias power range can be 100 to 150 W. In this step, by using a higher excitation power and a higher bias power, the two work together to improve the chemical etching effect and physical bombardment of the silicon oxynitride film 100, thereby increasing the etching rate of the silicon oxynitride film 100.
[0049] In the third etching step of this embodiment, the process gases include CHF3, SF6, and N2. The flow rate of CHF3 is in the range of 100–300 sccm, the flow rate of SF6 is in the range of 5–50 sccm, and the flow rate of N2 is in the range of 50–300 sccm. Preferably, the flow rate of CHF3 can be in the range of 150–250 sccm, the flow rate of SF6 can be in the range of 20–35 sccm, and the flow rate of N2 can be in the range of 150–200 sccm. CHF3 and SF6 serve as the primary etching gases for etching silicon oxynitride, while N2 serves as an inert gas to assist in the etching process.
[0050] In the third etching step of this embodiment, the process pressure ranges from 5 to 20 mT, the process temperature ranges from 25 to 40°C, and the process time ranges from 5 to 30 s. Preferably, the process pressure range can be 10 to 15 mT, the process temperature range can be 30 to 35°C, and the process time can be 15 to 20 s.
[0051] In summary, the semiconductor process method provided in this embodiment, by optimizing the process formulation, uses a low-bias power pulse mode in the first etching step, specifically the etching step for the silicon oxide film layer 300. This allows for the opening of the first silicon oxide film layer 310 at the top of the core region and the second silicon oxide film layer 330 in the non-core region, while simultaneously increasing the lateral etching sidewall film layer 320 and ensuring low loss in the underlying silicon oxynitride film layer 100. This achieves the adjustment and improvement of the imbalance between the core and non-core regions, as well as the optimization of the depth loading effect. It can be used in SADP etching processes to improve the imbalance after SADP etching. Of course, the semiconductor process method provided in this embodiment is not limited to SADP etching processes but can also be used in other etching processes to reduce critical dimension differences, improve parity effects, or improve imbalances.
[0052] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0053] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semiconductor manufacturing process, characterized in that, include: A film structure is provided, the film structure including a silicon oxynitride film layer (100), a carbon film layer (200) and a silicon oxide film layer (300), the carbon film layer (200) having a plurality of spaced carbon film layers (100) disposed on the upper surface of the silicon oxynitride film layer (100), the silicon oxide film layer (300) including a first silicon oxide film layer (310) located on the upper surface of the carbon film layer (200), a sidewall film layer (320) located on the side of the carbon film layer (200) and a second silicon oxide film layer (330) located on the upper surface of the silicon oxynitride film layer (100); In the first etching step, the first silicon oxide film layer (310) and the second silicon oxide film layer (330) are vertically etched to expose the upper surface of the carbon film layer (200) and the upper surface of the silicon oxynitride film layer (100) below the second silicon oxide film layer (330), and a portion of the thickness of the sidewall film layer (320) is horizontally etched; during the process, the bias power is in pulse mode; In the second etching step, the carbon film layer (200) is etched to expose the silicon oxynitride film layer (100) beneath the carbon film layer (200) while retaining the sidewall film layer (320). In the third etching step, the silicon oxynitride film layer (100) is etched using the sidewall film layer (320) as a mask.
2. The semiconductor process method according to claim 1, characterized in that, In the first etching step, the excitation power ranges from 400 to 800 W, the bias power ranges from 25 to 100 W, the pulse frequency range of the bias power ranges from 100 to 500 Hz, and the pulse ratio ranges from 15% to 50%.
3. The semiconductor process method according to claim 2, characterized in that, In the first etching step, the process gases include CF4 and CHF3, wherein the flow rate of CF4 is in the range of 50 to 300 sccm and the flow rate of CHF3 is in the range of 50 to 200 sccm.
4. The semiconductor process method according to claim 3, characterized in that, In the first etching step, the process pressure ranges from 5 to 25 mT, the process temperature ranges from 30 to 80 °C, and the process time ranges from 20 to 120 s.
5. The semiconductor process method according to claim 1, characterized in that, In the second etching step, the bias power is 0.
6. The semiconductor process method according to claim 5, characterized in that, In the second etching step, the process gases include O2 and N2, wherein the flow rate of O2 is in the range of 100 to 300 sccm and the flow rate of N2 is in the range of 50 to 200 sccm.
7. The semiconductor process method according to claim 6, characterized in that, In the second etching step, the process pressure ranges from 5 to 30 mT, the process temperature ranges from 30 to 80 °C, the excitation power ranges from 800 to 1400 W, and the process time ranges from 40 to 80 s.
8. The semiconductor process method according to claim 1, characterized in that, In the third etching step, the excitation power ranges from 300 to 600 W, and the bias power ranges from 50 to 200 W.
9. The semiconductor process method according to claim 8, characterized in that, In the third etching step, the process gases include CHF3, SF6 and N2, wherein the flow rate of CHF3 is in the range of 100 to 300 sccm, the flow rate of SF6 is in the range of 5 to 50 sccm, and the flow rate of N2 is in the range of 50 to 300 sccm.
10. The semiconductor process method according to claim 9, characterized in that, In the third etching step, the process pressure ranges from 5 to 20 mT, the process temperature ranges from 25 to 40 °C, and the process time ranges from 5 to 30 s.