Memory device channel hole formation using doped film layers

Abstract

Methods of fabricating memory device via holes using doped film layers are disclosed. A method may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a via hole through the vertical stack, forming an oxide-nitride-oxide layer along sidewalls of the via hole, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch stop layer, and annealing the vertical stack.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 470,647, filed June 2, 2023, entitled "Fluorine Doping of Manos Structure to Control State Spread", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the processing of three-dimensional NAND devices, and more specifically, to the formation of channel holes in memory devices using doped film layers. Background Technology

[0004] A memory design known as NAND flash memory is a non-volatile flash memory storage architecture that does not require power to maintain the data it stores. NAND flash memory is used in many products, such as solid-state devices and portable electronic devices. To improve density and reduce the size of NAND memory, the traditional two-dimensional NAND architecture has transitioned to three-dimensional (3D) NAND stacking. Unlike two-dimensional (2D) planar NAND technology, where individual memory cells are stacked together on separate horizontal substrates, 3D NAND uses multiple layers of alternating conductive and dielectric materials with intersecting vertical channels that are stacked vertically.

[0005] Logic scaling to store more bits in a cell is one way to increase memory capacity and reduce bit cost in 3D NAND memory. However, inherent channel effects increase the threshold voltage distribution and reduce on-current by increasing channel resistance. This disclosure is provided in consideration of these and other factors. Summary of the Invention

[0006] In view of the foregoing, in some embodiments, the method may include forming a channel via through a vertical stack, wherein the vertical stack comprises a plurality of alternating material layers, and forming a tunneling layer along the sidewalls of the channel via. The method may further include forming a channel layer over an oxide-nitride-oxide layer, forming an etch-stop layer over the channel layer, forming a doped film layer over the etch-stop layer, and annealing the vertical stack.

[0007] In some methods, fabricating a three-dimensional (3D) NAND memory structure may include providing a substrate and forming a vertical stack over the substrate, the vertical stack comprising a plurality of alternating material layers. The method may further include forming channel vias through the vertical stack, forming an oxide-nitride-oxide layer along the sidewalls and bottom of the channel vias, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch-stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch-stop layer, and annealing the vertical stack.

[0008] In some embodiments, a method of forming a memory device may include forming a vertical stack over a substrate, the vertical stack comprising a plurality of alternating material layers, and forming a via through the vertical stack. The method may further include forming an oxide-nitride-oxide layer along the sidewalls and bottom of the via, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch-stop layer over the silicon layer, forming a fluorine-doped silicon film over the etch-stop layer, and annealing the vertical stack including the fluorine-doped silicon film. Attached Figure Description

[0009] Figure 1 A top plan view of a processing system according to some embodiments is shown.

[0010] Figures 2A-2D The illustration depicts the progressive stages of generating a channel-based memory structure according to some implementation methods.

[0011] Figures 3A-3E The diagram illustrates the progressive stages of generating one or more channels of a memory structure according to some implementations.

[0012] Figure 4 A flowchart illustrating a method for manufacturing a 3D NAND memory structure according to some embodiments is shown.

[0013] The accompanying drawings are not necessarily to scale. They are illustrative only and are not intended to depict specific parameters of this disclosure. The drawings depict exemplary embodiments of this disclosure and are therefore not to be construed as limiting the scope.

[0014] Furthermore, for clarity, certain elements in some features may be omitted or not drawn to scale. For clarity, cross-sectional views may be presented as "slices" or "partially visible" cross-sectional views, omitting certain background lines that would be visible in the "true" cross-sectional view. Furthermore, for clarity, some reference numerals may be omitted in certain figures. Detailed Implementation

[0015] The methods, systems, and apparatus according to this disclosure will now be described in more full below with reference to the accompanying drawings, in which many embodiments are shown. The methods, systems, and apparatus may be implemented in many different forms and are not to be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0016] This embodiment relates to a 3-D NAND device comprising a fluorine-doped metal-alumina-silicon nitride-silicon dioxide-silicon (MANOS) structure to control state expansion. More specifically, this embodiment provides an integration scheme to deposit fluorine-doped silicon (Si) within one or more stacking trenches, which serves as a solid source to allow fluorine to diffuse and passivate the Si channels / tunneling SiO interfaces in the 3D NAND structure. Fluorine passivation increases the on-current, enabling further wordline stacking and also improving the subthreshold swing and threshold voltage, which narrows the material-inherent distribution to reduce the power required to compress sixteen (16) states and more. The fluorine-doped silicon is thick enough to fill the top channel apertures but still creates voids internally. An annealing step of the structure causes chlorine to diffuse within the channels to passivate the channels and tunnel through the oxide interfaces. The fluorine-doped silicon film is then removed by etching, and the voids expand the removal processing window.

[0017] Figure 1 This is a top plan view showing one embodiment of a processing system 100 for deposition, etching, baking, and curing chambers according to some embodiments. As shown, a pair of front-opening standard chambers 102 supply substrates of various sizes. The substrates are received by a robotic arm 104 and placed into a low-pressure holding region 106 before being placed into one of the substrate processing chambers 108a-108f located in series sections 109a-109c. A second robotic arm 110 can be used to transfer substrate wafers from the holding region 106 to the substrate processing chambers 108a-108f and back. Each substrate processing chamber 108a-106f can be equipped to perform a number of substrate processing operations, including etching processes and cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processing as described herein.

[0018] The substrate processing chambers 108a-108f may include one or more system components for depositing, annealing, curing, and / or etching material films, such as fluorine-doped layers, on a substrate or wafer. In one configuration, two pairs of processing chambers, such as 108c-108d and 108e-108f, may be used to deposit materials (e.g., one or more films) on the substrate, and a third pair of processing chambers, such as 108a-108b, may be used to cure, anneal, or process the deposited films. In another configuration, all three pairs of chambers, such as 108a-108f, may be configured to deposit and cure films on the substrate. Any or more of the described processes may be performed in additional chambers separate from the manufacturing systems shown in different embodiments. It will be understood that the processing system 100 is contemplated with additional configurations for the deposition, etching, annealing, and curing chambers for the material films.

[0019] Furthermore, any number of other processing systems can be utilized with respect to this disclosure, which can be incorporated into a chamber for performing any particular operation. In some embodiments, a chamber system that provides access to multiple processing chambers while maintaining a vacuum environment in various sections (such as the aforementioned holding and transfer areas) allows operations to be performed in multiple chambers while maintaining a specific vacuum environment between separate processes.

[0020] Processing system 100, or more specifically, the chambers incorporated in processing system 100 or other processing systems, can be used to produce structures according to some embodiments of this disclosure. For example, processing system 100 can be used to produce memory arrays by performing operations such as deposition, etching, sputtering, polishing, cleaning, etc., in various substrate processing chambers 108a-108f.

[0021] Figure 2A This illustration depicts a side cross-sectional view of a memory device (hereinafter referred to as "device") 200 in an early stage of processing according to one or more embodiments described herein. Device 200 may be a partial stack of alternating oxide-nitride layers formed for, for example, a 3D NAND flash memory array. Figure 2A The layers can be formed one after another, using any deposition or layer-forming technique, such that one layer sits on top of the previous layer. In this example, these layers can be formed on a substrate 201 of silicon material (such as epitaxial silicon or a single-crystal silicon wafer). A silicon oxide layer 202 can be formed on top of the substrate 201, followed by a silicon nitride layer 204. In some embodiments, the silicon oxide layer 202 and the silicon nitride layer 204 may represent initial layers on the substrate 201, and these layers may be thicker than the alternating oxide-nitride layers formed thereon. Next, alternating layers of silicon oxide layer 206 and silicon nitride layer 208 can be formed in the stack.

[0022] The stepwise formation of substrate 201, silicon oxide layer 206, silicon nitride layer 208, and other materials described below can be collectively referred to as stack 224. For example... Figure 2A As shown, stack 224 can be initially topped out to a finite height. For example, the finished stack 224 can have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, initially forming all these layers would result in a stack 224 with an excessively high aspect ratio, making it impossible to reliably form narrow channel holes and other vias throughout the entire stack 224. Therefore, stack 224 can be formed in a series of tiers, where alternating silicon oxide layers 206 and silicon nitride layers 208 correspond to the first tier 205.

[0023] like Figure 2A As further shown, stack 224 can be etched to form a plurality of channel holes 203 through alternating silicon oxide layers 206 and silicon nitride layers 208. Channel holes 203 can be formed by covering a portion of the stack with a mask (not shown) and performing an etching process to remove material exposed by the mask. Any etching process can be used, and some embodiments may use dielectric etch. Etching through alternating silicon oxide layers 206 and silicon nitride layers 208 benefits from dielectric etch because the desired aspect ratio of the channel holes 203 for device channels is relatively high (i.e., the vertical depth of the channel holes 203 is relatively high compared to the horizontal width of the channel holes 203). Generally, the depth of the channel holes 203 can be controlled based on the number of silicon oxide layers 206 and the number of silicon nitride layers 208 to be etched. For example, the allowable time for running the etching process can be determined by the number of silicon oxide layers 206 and the number of silicon nitride layers 208, as well as the thickness of these layers. For example, in some embodiments, the via 203 may be etched down to the silicon nitride layer 204. In other embodiments, the via 203 may be etched down to the silicon oxide layer 202, or down to the top of the substrate 201. (Illustrated in...) Figure 2A The non-limiting example in the example terminates the etching at the top of the silicon nitride layer 204.

[0024] Figure 2B This illustration depicts how bottom stamping etching, according to some embodiments, can be used to penetrate substrate 201 to expose the silicon of substrate 201. In some embodiments, in Figure 2B The dielectric etching used can terminate the via etching before etching through the substrate 201. A second etching process can then be performed, causing the via 203 to extend downward into the substrate 201. This additional etching can be a directional etching perpendicular to the bottom of the via 203, and can be referred to herein as “underpass etching.” Underpass etching allows the silicon material of the substrate 201 to be exposed at the bottom of the via 203.

[0025] In some embodiments, under-punch etching may represent an etching separate from the etching used to form the channel hole 203. For example, under-punch etching may be performed in a conductor etching chamber rather than a dielectric etching chamber, which may have better critical size consistency and profile control compared to dielectric etching used to initially form the channel hole 203 for device channels. Under-punch can thus extend the channel hole 203 downward into the substrate 201 to expose the silicon material. For example, under-punch etching may extend to the top surface of the substrate 201, or alternatively, may extend through the substrate 201 below the top surface of the substrate 201. Alternatively, other embodiments may use a single etching process to etch the full length of the channel hole 203 downward into the substrate 201, thus extending the channel hole 203 downward into the substrate 201. Figures 2A-2B The results are combined into a single processing step. The exposed silicon material on substrate 201 can be used in a later step to epitaxially grow silicon through channels, which forms 3D NAND flash memory cells.

[0026] Figure 2C The diagram illustrates how stack 224 can be expanded by adding a second stack 213 on top of the first stack 205, wherein the second stack 213 may include additional silicon oxide layers 207 and silicon nitride layers 209. These additional layers may be formed layer by layer on top of the first stack 205. Although not shown, a support layer may first be formed within the via 203, providing a base on which the second stack 213 can be constructed. After the addition of the additional oxide layers 207 and nitride layers 209 of the second stack 213, a plurality of vias 211, 219 may be etched into the second stack 213, as shown. Note that these vias 211, 219 may be formed using a similar mask as previously used to etch the vias 203 in the first stack 205. By progressively etching these layers, a very high aspect ratio can be achieved regardless of the depth of the vias 211, 219 in the full stack 224.

[0027] In reality, stack 224 can include a large number of layers, a large number of vias, and can be used to form hundreds of 3D NAND flash memory cells. However, these figures have been simplified to show the formation of a single epitaxial silicon channel and adjacent support structures or slits in the memory array. For example, a real stack could include thousands of channels, more than 100 layers of alternating oxide and nitride layers, and multiple slits and support structures. These layers can be formed in multiple processes by stepwise etching performed on each batch of layers as they are added to the partial stack. Therefore, although Figure 2COnly two combined partial stacks are illustrated; it should be understood that many additional partial stacks may be stacked and etched to form channel holes 203 through stack 224. For example, some embodiments may include a combination of two partial stacks, each having approximately 128 layers of alternating oxide-nitride layers for a total of 256 layers of alternating oxide-nitride layers.

[0028] Figure 2D An optional support feature 210, which may be formed in one of a plurality of holes (e.g., hole 211) according to some embodiments, is illustrated to provide support between stacks 224 during subsequent processing steps. The support feature 210 may be selectively deposited in one of the plurality of holes to form a robust structure through the first stack 205 and the second stack 213. For example, some embodiments may use a metal (such as tungsten) to form the support feature 210. Some embodiments may use a dielectric fill (such as a SiOx or MANOS stack) for the support feature 210. Any deposition process may be used to form the support feature 210. Note that the support feature 210 may extend downward into the substrate 201 by the aforementioned etching process overshooting the final silicon oxide layer 202. When the silicon nitride layer 204 is removed, the support feature 210 retains the layers of the stack 224 from collapsing. Furthermore, when the silicon nitride layer 204 is subsequently removed, the support feature 210 extending downward into the substrate 201 prevents any movement of the upper layers of the stack 224.

[0029] Figure 2D Further illustration shows an initial layer of epitaxial silicon 212 formed in one of the vias 219 according to some embodiments. As described above, the bottom punch etching into the substrate 201 to an additional depth exposes the silicon material of the substrate 201 to the via 219. Because the monocrystalline silicon of the substrate 201 is exposed, the layer of epitaxial silicon 212 can be grown in the via using epitaxial processes such as silicon epitaxial deposition or growing a thin layer of monocrystalline silicon over the monocrystalline silicon substrate 201. For example, in some embodiments, the epitaxial process can be performed by chemical vapor deposition. Materials such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other chemically derived silicon can be provided to the deposition chamber to progressively form the epitaxial silicon 212 grown on top of the substrate 201. The height of the epitaxial silicon 212 may exceed the silicon oxide layer 202 but lie below the next silicon oxide layer 206 in the stack 224. For example, the height of the epitaxial silicon 212 may be within the sacrificial nitride layer 204.

[0030] Figure 3A A more detailed drawing Figure 2DHole 219. For clarity, the remainder of device 200 is not shown. Since hole 219 can now be used as a channel for forming vertical pillars for 3D NAND memory cells, hole 219 is also referred to herein as a channel hole. As shown, a tunneling layer 214 may be formed along one or more sidewalls 222 of channel hole 219 and along bottom 223, wherein tunneling layer 214 and channel hole 219 extend through first stack 205 and second stack 213 of stack 224. Tunneling layer 214 may be formed by depositing a first blocking dielectric or oxide 226, a charge-trapping nitride (e.g., silicon nitride) 228, and a second tunneling dielectric or oxide 230. These three layers may be collectively referred to as an ONO layer or tunneling layer 214 in this disclosure. The first and second oxide layers 226, 230 in tunneling layer 214 may provide offset for the conduction band and valence band of transistor devices for memory cells. Although not limited, in some embodiments, channel hole 219 may be approximately 20 µm deep. As shown in the figure, the sidewalls 222 of the channel hole 219 may be non-parallel. More specifically, the sidewalls 222 of the channel hole 219 generally converge toward the bottom 223 of the channel hole 219.

[0031] Atomic layer deposition can be used to form various layers of the tunneling layer 214, and therefore the tunneling layer 214 will be relatively thin compared to the alternating oxide-nitride layers of the stack 224. This process can facilitate the tunneling layer 214 on the epitaxial silicon 212 ( Figure 2D The epitaxial silicon 212 is grown on the sidewalls 222 and bottom 223 of the channel hole 219 above the top. Because the epitaxial silicon 212 terminates before the alternating silicon oxide layer 206 and silicon nitride layer 208, the interior of the channel for the 3D NAND memory cell can be covered by the tunneling layer 214.

[0032] Figure 3A The deposition of a channel liner 232 within the channel via 219, above the tunneling layer 214, is further illustrated. The channel liner 232 may be a silicon layer formed using atomic layer deposition, and is therefore relatively thin compared to the alternating oxide-nitride layers of the stack 224. This process facilitates the growth of the channel liner 232 above the tunneling layer 214.

[0033] Figure 3B An etch stop layer 234 is formed above / along the channel liner 232. In some embodiments, the etch stop layer 234 may be a SiO layer formed using atomic layer deposition, and therefore may be relatively thin (e.g., about 5 nm).

[0034] Figure 3CThe formation of a fluorine-doped layer 240 is shown above the etch-stop layer 234 and tunneling layer 214 within the channel aperture 219. The fluorine-doped layer 240 can be a film formed using chemical vapor deposition (CVD) and can be formed above the sidewalls 222 and bottom 223 of the channel aperture 219. More specifically, a silicon film can be deposited within the channel aperture 219 and then implanted with fluorine. That is, fluorine atoms can be guided into the outer surface of the silicon film. In other embodiments, a silicon film in which fluorine has already been incorporated can be deposited. In some non-limiting embodiments, the fluorine-doped silicon film contains approximately 3-6% fluorine. At this ratio, the conduction current can increase by approximately 5 times while the variability decreases by approximately 6σ. Furthermore, the fluorine concentration in the channel / Tox can be approximately 4e20 cm⁻³, while the fluorine concentration within Tox can be less than 4e20 cm⁻³.

[0035] like Figure 3C As further illustrated, after the formation of the fluorine-doped layer 240, one or more holes may appear in the channel vias 219. In some embodiments, a first hole 246A may be formed in the first stack 205, while a second hole 246B may be formed in the second stack 213. As shown, a first portion 248 of the fluorine-doped layer 240 extends between the sidewalls of the etch-stop layer 234 to surround the second hole 246B. While not limited, the first hole 246A may be formed toward the top portion of the first stack 205, while the second hole 246B may be formed toward the middle portion of the second stack 213.

[0036] After the fluorine-doped layer 240 is formed, an annealing process can then be performed. In some embodiments, the annealing process can be performed at a temperature greater than 500°C. In a non-limiting example, the annealing process can be performed at 650°C for between 45 and 80 seconds. The annealing process facilitates the diffusion of fluorine into the channels.

[0037] Figure 3D The diagram illustrates the fluorine-doped layer 240 of the stack 224 after annealing. Figure 3C Selective removal of the fluorine-doped layer 240. In this example, wet etching, such as tetramethylammonium hydroxide (TMAH) chemical etching, can be used. Wet etching can selectively remove the fluorine-doped layer 240 relative to the etch stop layer 234. Other embodiments may use dry etching or other processes configured to selectively remove the fluorine-doped layer 240.

[0038] Figure 3E The selective removal of the etch stop layer 234 is illustrated according to some embodiments. In this example, wet or dry etching can be used to selectively remove the etch stop layer 234 relative to the channel pad 232.

[0039] Although not shown, according to some embodiments, the channel hole 219 may then be filled with an interstitial filler material. To protect the tunneling layer 214 and the channel liner 232 during subsequent etching processes, the channel hole 219 may be filled with an interstitial filler material, which may be SiO. The interstitial filler material 216 may be formed directly on top of the channel liner 232.

[0040] Although not shown, further processing may be performed later on device 200 to complete the memory array. These operations are beyond the scope of this disclosure and are therefore omitted for brevity.

[0041] Figure 4 A flowchart 400 illustrates a method for manufacturing a 3D NAND memory structure according to some embodiments. This method can be used in, for example... Figure 1 The process is performed in various processing chambers within the illustrated semiconductor processing system.

[0042] In block 401, the method may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate. In some embodiments, the alternating material layers include alternating layers of oxide materials and nitride materials. In some embodiments, the alternating material layers include alternating layers of oxide materials and metals, wherein the metals form gate electrodes for individual memory cells.

[0043] In block 402, the method may include etching or forming channel holes extending through multiple alternating material layers. In some embodiments, the channel holes extend to the top surface of the substrate.

[0044] In block 403, the method may include forming an oxide / nitride / oxide + polysilicon (ONOP) tunneling layer around the channel hole, wherein the ONOP layer contacts a plurality of alternating material layers.

[0045] In block 404, the method may include etching a termination layer along the ONOP layer. In some embodiments, the etch termination layer may be deposited via ALD. In some embodiments, the etch termination layer may be SiO.

[0046] In block 405, the method may include forming a fluorine-doped layer over the etch stop layer. In some embodiments, the fluorine-doped layer is a fluorine-doped film formed via CVD. In some embodiments, one or more gaps or pores may be formed in the fluorine-doped layer.

[0047] In block 406, the method may include performing an annealing process on the stack and the fluorine-doped layer.

[0048] In block 407, the method may include removing the fluorine-doped layer and the etch stop layer from the channel via. In various embodiments, one or more wet or dry etching processes may be performed to remove the fluorine-doped layer and the etch stop layer.

[0049] It should be understood that Figure 4 The specific steps illustrated provide a particular method for manufacturing a 3D NAND memory structure according to various embodiments. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments may perform the above steps in a different order. Furthermore, Figure 4 The individual steps illustrated may include multiple sub-steps, which can be performed through various sequences suitable for that individual step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and alternatives also fall within the scope of this disclosure.

[0050] In various implementations, design tools may be provided and configured to create datasets for patterning semiconductor layers of devices such as those described herein. For example, datasets may be created to generate photomasks used during photolithography operations to pattern layers of structures such as those described herein. Such design tools may include a collection of one or more modules and may also include hardware, software, or combinations of the foregoing. Thus, for example, a tool may be a collection of any combination or permutation of one or more software modules, hardware modules, software / idea modules, or the foregoing. As another example, a tool may be a computing device or other apparatus running software, or implemented in hardware.

[0051] For convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” and “longitudinal” will be used in this document to describe the relative placement and orientation of components and their constituent parts, as seen in the illustrations. This terminology will include specifically mentioned words, their derivatives, and words with similar meanings.

[0052] Furthermore, it should be noted that individual implementations may have been described as processes depicted as flowcharts, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may have described operations as being processed sequentially, many operations may be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. When an operation is completed, the process terminates, but may have additional steps not included in the illustrations. A process may correspond to a method, function, procedure, subroutine, subroutine, etc. When a process corresponds to a function, its endpoint may correspond to the function returning to the calling function or the main function.

[0053] As used herein, elements or operations described in the singular and prefixed with "a" or "an" are to be understood as including multiple elements or operations until explicitly excluded by the description. Furthermore, "one embodiment" of this disclosure is not intended to be limiting. Additional embodiments may be incorporated into the features described.

[0054] Furthermore, the terms "substantial" or "truly" and "approximately" are used interchangeably in some embodiments and can be described using any relative measurement acceptable to those skilled in the art. For example, these terms can serve as comparisons to a reference parameter to indicate deviations from the intended function. While the steps are limited, deviations from the reference parameter can be, for example, amounts less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0055] Furthermore, those skilled in the art will understand that when an element, such as a layer, region, or substrate, is described as being formed, deposited, or disposed "above," "on top of," or "on top of" another element, the element may be directly located on top of the other element or there may be an intermediate element present. Conversely, when an element is described as "directly on top of," "directly above," or "directly on top of" another element, there is no intermediate element present.

[0056] This disclosure is not limited to the specific embodiments described herein. In fact, various other embodiments and modifications of this disclosure will be apparent to those skilled in the art from the foregoing description and drawings, in addition to those described herein. Therefore, these other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, this disclosure has been described herein in a specific context and for a specific purpose within a specific environment. Those skilled in the art will recognize that the benefits are not limited thereto, and that this disclosure can be advantageously implemented in any number of environments for any number of purposes. Therefore, the appended claims should be interpreted in accordance with the full scope and spirit of this disclosure as described herein.

Claims

1. A method comprising the following steps: Forming channel holes through vertically stacked layers, the vertical stack comprising multiple alternating material layers; A tunneling layer is formed along the sidewall of the channel hole; A channel liner is formed above the tunneling layer; An etch stop layer is formed above the channel liner; A doped film layer is formed above the etch stop layer; and Annealing the vertical stack.

2. The method of claim 1, further comprising the step of: after the vertical stack is annealed, selectively removing the doped film layer relative to the etch stop layer.

3. The method of claim 2 further comprises the step of: removing the etch stop layer after the doped film layer has been removed.

4. The method of claim 2, wherein wet etching is used to remove the doped film layer.

5. The method of claim 1, wherein the step of forming the doped film layer comprises the following steps: A silicon film is deposited directly on top of the etch stop layer; and Fluorine ions are guided into the silicon film to form a fluorine-doped silicon film.

6. The method according to claim 5, further comprising the step of forming pores in the fluorine-doped silicon film.

7. The method of claim 6, further comprising forming the vertical stack over the substrate by means of the following steps: The first stack forming the plurality of alternating material layers; and A second stack of the plurality of alternating material layers is formed over the first stack of the plurality of alternating material layers.

8. The method of claim 7, wherein the pores in the fluorine-doped silicon film are formed in the first stack of the plurality of alternating material layers, and wherein the second pores in the fluorine-doped silicon film are formed in the second stack of the plurality of alternating layers.

9. The method of claim 1, wherein the plurality of alternating material layers comprises alternating layers of oxides and nitrides.

10. A method for forming a three-dimensional (3D) NAND memory structure, the method comprising the steps of: A vertical stack is formed above a substrate, the vertical stack comprising multiple alternating material layers; Forming channel holes through the vertically stacked structures; A tunneling layer is formed along the sidewalls and bottom of the channel hole, wherein the tunneling layer comprises a first oxide, a nitride, and a second oxide; A silicon layer is formed above the tunneling layer; An etch stop layer is formed over the silicon layer; A fluorine-doped silicon layer is formed above the etch stop layer; and Annealing the vertical stack.

11. The method of claim 10, further comprising the following steps: After the vertical stack is annealed, the fluorine-doped silicon layer is selectively removed relative to the etch stop layer, wherein wet etching is used to remove the etch stop layer; and After the fluorine-doped silicon layer is removed, the etch stop layer is removed.

12. The method of claim 10, wherein the step of forming the fluorine-doped silicon layer comprises the following steps: A silicon film is deposited directly on top of the etch stop layer; and Fluorine ions are guided into the silicon film to form a fluorine-doped film.

13. The method of claim 12, wherein the step of forming the vertical stack over the substrate comprises the following steps: The first stack forming the plurality of alternating material layers; and A second stack of alternating material layers is formed over a first stack of alternating material layers, wherein pores in the fluorine-doped film are formed in the first stack of alternating material layers, and wherein second pores in the fluorine-doped film are formed in the second stack of alternating material layers.

14. The method of claim 10, wherein the plurality of alternating material layers comprises alternating layers of oxides and nitrides.

15. A method of forming a memory device, the method comprising the steps of: A vertical stack is formed above a substrate, the vertical stack comprising multiple alternating material layers; Forming channel holes through the vertically stacked structures; An oxide-nitride-oxide layer is formed along the sidewalls and bottom of the channel hole; A silicon layer is formed over the oxide-nitride-oxide layer; An etch stop layer is formed over the silicon layer; A fluorine-doped silicon film is formed above the etch stop layer; and Annealing includes the vertical stacking of the fluorine-doped silicon films.

16. The method of claim 15, further comprising the step of: After the vertical stack is annealed, the fluorine-doped silicon film is selectively removed relative to the etch stop layer; and After the fluorine-doped silicon film is removed, the etch stop layer is removed.

17. The method of claim 16, wherein wet etching is used to remove the fluorine-doped layer.

18. The method of claim 15, wherein the step of forming the vertical stack over the substrate comprises the following steps: The first stack forming the plurality of alternating material layers; and A second stack of alternating material layers is formed over a first stack of alternating material layers, wherein pores in the fluorine-doped film are formed in the first stack of alternating material layers, and wherein second pores in the fluorine-doped film are formed in the second stack of alternating material layers.

19. The method of claim 15, wherein the plurality of alternating material layers comprises alternating layers of oxides and nitrides.

20. The method of claim 15, wherein the annealing is performed at a temperature greater than 500 °C, and wherein the concentration of fluorine in the fluorine-doped silicon film is between 3% and 6%.

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