Coaxial vias in glass core architectures

Abstract

The present disclosure relates to coaxial vias in glass core architectures. In one embodiment, a substrate includes a glass core layer having a plurality of coaxial through glass vias (TGVs). The coaxial TGV includes a first conductive portion and a second conductive portion with a dielectric therebetween. The outer conductive portion of the coaxial TGV may be formed using a plated metal, while the inner conductive portion of the TGV may be formed using a metal sinter paste.

Description

BACKGROUND

[0001] The continued growth of computing devices and mobile devices will continue to increase the demand for greater bandwidth density and semiconductor package reliability within semiconductor packages. Some integrated circuit packages can implement a glass core, which can provide advantages over traditional packages with an organic material core (e.g., the glass core is thicker and can better resist warping through manufacturing processes). Through glass vias (TGVs) can provide electrical connections through the glass core, for example, to connect metallization layers on either side of the glass core. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figure 1 An example substrate with coaxial through glass vias (TGVs) is shown in accordance with an embodiment herein.

[0003] Figures 2A-2F An example process of forming coaxial TGVs is shown in accordance with an embodiment herein.

[0004] Figure 3 An example package substrate with a glass core having coaxial TGVs therein is shown in accordance with an embodiment herein.

[0005] Figure 4 An example multi-die package with a glass core having coaxial TGVs therein is shown in accordance with an embodiment herein.

[0006] Figure 5 Another example multi-die package with a glass core having coaxial TGVs therein is shown in accordance with an embodiment herein.

[0007] Figures 6A-6B An example system that can incorporate the glass core architectures described herein is shown.

[0008] Figure 7 is a top view of a wafer and die that can be included in a microelectronic assembly in accordance with any of the embodiments disclosed herein.

[0009] Figure 8 is a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly in accordance with any of the embodiments disclosed herein.

[0010] Figure 9 is a block diagram of an example electrical device that can include a microelectronic assembly in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0011] Integrated circuit devices continue to shrink in size, and as a result of this shrink, improving device performance has focused in two directions: (1) using thinned chips to enable chip stacking, and (2) increasing input / output (I / O) density in the substrate for multi-chip integration. With the use of rigid carrier wafers (such as glass-based handle wafers) in temporary bonding and debonding techniques, fabrication of these ever-growing devices has been made possible. However, one of the challenges associated with temporary bonding and debonding techniques is warpage or shrinkage control after the rigid carrier is removed. Upon debonding the rigid glass carrier after bump formation, the substrate can be expected to warp due to CTE (coefficient of thermal efficiency) mismatch and built-in residual stress between various components (e.g., between silicon (2.6 ppm / °C), ABF (~39 ppm / °C), and copper (17 ppm / °C)). This can impact back-end processes for bump formation and assembly processes.

[0012] One way to address the above issues is to use glass as a permanent substrate core, as glass is stiffer than organic core materials (e.g., glass can have an elastic modulus of ~60-90 GPa compared to an elastic modulus of ~25-30 GPa for organic core materials). A permanent glass core can limit warpage, and as a result can maintain TTV requirements to enable smaller pitch scaling.

[0013] Through glass via (TGV) provides electrical connections through a glass core substrate, for example, to provide electrical connections between metallization layers on either side of the core. Current TGVs are implemented as full-plated TGVs, where the through hole is completely filled with plated metal (e.g., copper) after a seed layer has been deposited by sputtering. Because the seed sputtering step is a line-of-sight process, it can require a given taper angle of the hole in the glass layer to ensure sufficient seed coverage. The taper angle results in a top-to-bottom CD difference (Delta) (i.e., a varying diameter of the TGV), which can become a limiting factor for downscaling of pitch. This issue becomes more pronounced at higher core thicknesses, where the taper angle results in a larger top-to-bottom CD difference of the TGV.

[0014] Furthermore, full-plated TGVs can suffer from thermo-mechanical stress related challenges due to the large CTE mismatch between copper and glass and the large volume of copper. More specifically, the large CTE mismatch between plated copper and glass results in radial stresses upon heating and tensile stresses upon cooling, which degrades the reliability of the glass core substrate. This problem has been addressed in structures with similar CTE mismatch, such as through-silicon vias (TSVs), by including a liner for stress absorption, but the increased volume of copper in TGVs relative to TSVs makes the liner material and thickness selection a challenging process. To date, both organic and organosilicate liners have proven ineffective as stress release layers for TGVs.

[0015] Embodiments herein can include coaxial TGV structures to address these or other issues. Example coaxial TGV structures according to embodiments herein can include a conformal copper outer layer as a first electrical path, a sintered copper core portion as a second electrical path, and a stress release insulating layer between the two electrical paths to improve thermo-mechanical stress. The coaxial TGV structures can provide one or more advantages over conventional full-plated TGVs, including: (1) providing two different electrical paths per TGV, which can reduce the impact of TGV tapering on pitch shrinkage; (2) including a stress release layer, which can reduce the likelihood of thermo-mechanically induced failures at the glass-copper interface; and (3) reducing the volume of plated copper per TGV (which has a relatively high CTE) in favor of sintered copper, which has a relatively lower CTE, which can also reduce the likelihood of thermo-mechanically induced failures.

[0016] Figure 1 An example substrate 100 having a coaxial through-glass via (TGV) 101 according to embodiments herein is shown. In particular, Figure 1A top view and cross-sectional view of TGV 101 in substrate 100 are shown. TGV 101 is formed in layer 102 of substrate 100, which may form the core layer of an integrated circuit package substrate, as further described below. TGV 101 extends from the top surface of layer 102 to the bottom surface of layer 102, as shown. Layer 102 may comprise glass or a glass-based material and may comprise silicon (e.g., at least 23% by weight) and oxygen (e.g., at least 26% by weight). Layer 102 may be amorphous, and in some embodiments, layer 102 may comprise one or more additive elements (e.g., at least 5% by weight), such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. Layer 102 may be formed from one or more of the following example materials: aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, or fused silicon dioxide. In some embodiments, layer 102 may further include one or more additives, such as, for example, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, layer 102 may be made of spin-coated glass (SOG) material.

[0017] The coaxial TGV 101 includes a first metal portion 106 and a second metal portion 110, with a dielectric layer 108 therebetween, such as Figure 1 As shown. The first metal portion 106 may be a conformal metal layer on the glass layer 102 (or, as shown, on the substrate 104 between the glass layer 102 and the metal). The first metal portion 106 may be deposited via seed layer sputtering followed by electroplating, or by other suitable methods. However, the second metal portion 110 may be formed using sintered metal. For example, in some embodiments, the second metal portion 110 may be formed using copper sintering paste, while the first metal portion 106 may be copper-plated. The second metal portion 110 may include the same or different metal material as the first metal portion 106. The thickness of the first and second metal portions may depend on the overall circuit design and / or electrical processing requirements (e.g., current processing) of the TGV 101. As an example, the first metal portion 106 may have a thickness of approximately 15-25 μm, the dielectric layer 108 may be approximately 10-25 μm thick, and the second metal portion 110 may have a thickness / diameter of approximately 10-20 μm.

[0018] As shown, each of the first metal portion 106, the second metal portion 110, and the dielectric layer 108 between the first and second metal portions extends substantially from a top surface of the layer 102 to a bottom surface of the layer 102. The first metal portion 106 can be referred to as an outer layer of the coaxial TGV 101, while the second metal portion 110 can be referred to as an inner layer of the coaxial TGV, with the dielectric layer 108 acting as an insulator between the inner and outer layers of the coaxial TGV.

[0019] Further, as shown, the first metal portion 106 can be generally annular in cross-section, while the second metal portion 110 is generally cylindrical (round in cross-section). For example, in the example shown, the first metal portion 106 maintains an annular cross-section throughout the thickness of the TGV, but the radius of the annular shape can vary along different cross-sections of the TGV (due to the tapering of the hole (which can also be referred to as an opening) in the glass layer 102). Although the sharp corner is shown in the first metal portion 106 as facing toward the middle of the glass layer 102, in some embodiments, the angle can be more rounded, and the shape of the first metal portion 106 can be more hourglass-shaped. Conversely, in the example shown, the second metal portion 110 maintains a generally cylindrical shape with a generally constant radius throughout the cross-section of the TGV. Further, as shown in the top view, the first metal portion 106 and the second metal portion 110 can be generally concentric with one another. Figure 1

[0020] As used above or elsewhere herein, or in other contexts, “generally” can refer to an approximation of a referenced shape or other morphology. For example, the first metal portion 106 can not maintain a perfectly annular cross-sectional shape with perfectly concentric inner and outer cross-sectional radii throughout the cross-section of the TGV; however, the cross-section of the first metal portion 106 can be substantially annular throughout. Likewise, the second metal portion 110 can not be perfectly cylindrical, i.e., it can not have a perfectly round morphology and / or can not have a precisely constant radius over the entire thickness of the TGV; however, it can be considered substantially cylindrical in that the radius can not vary by more than + / - 5% or 10% throughout the TGV.

[0021] In some embodiments, the second metal portion 110 can further include a filler material, such as a filler in a sintering paste material used to form the portion 110. The filler in the copper sintering paste can be varied to adjust the sintered copper CTE or to adjust the sintered copper electrical properties (e.g., by including magnetic particles). Example filler materials that can be used in the second metal portion 110 can include one or more of the following: diamond, BN (boron nitride), AI2O3 (aluminum oxide), MgO (magnesium oxide), and SiO2 (silicon dioxide). x . ​

[0022] The dielectric layer 108 can serve as a stress-relieving layer between the two metal portions of the TGV 101. The dielectric layer 108 may comprise a polymeric material, such as one or more of the following: polyimide, polybenzoxazole, polycarbonate, benzocyclobutene (BCB), poly(vinylpyridine) (PVP), polyphenols, polyethers, and polyacrylates (including any combination of the aforementioned polymers). In some embodiments, the dielectric layer 108 may comprise an Ajinomoto deposited film (ABF).

[0023] In some embodiments, a dielectric layer 104 may be present between the TGV 101 and the glass core (e.g., between the first metal portion 106 and layer 102 as shown). Layer 104 may comprise one or more of the following materials: polymers (e.g., parylene), SiO₂, etc. x SiN x and carbon-doped SiO x Layer 104 can be deposited using physical or chemical vapor deposition methods.

[0024] Figures 2A-2F An example process 200 for forming a coaxial TGV according to embodiments herein is illustrated. The illustrated example process may include more, fewer, or different operations than those shown or described below. In some embodiments, one or more of the illustrated operations include multiple operations, sub-operations, etc. Therefore, Figures 2A-2F The illustrations may represent different stages in the manufacturing process of a device (e.g., an integrated circuit packaging substrate). Although process 200 is shown with respect to a single TGV, it should be understood that process 200 can be applied to multiple TGVs formed simultaneously (e.g., in the same glass layer) or otherwise formed.

[0025] First refer to Figure 2A Holes 201 are formed in the glass layer 202. Holes 201 can be formed via laser drilling and wet etching processes, similar to those used to form holes in the glass layer for full TGV plating. A dielectric liner 203 can then be formed on the inside of the holes 201, such as... Figure 2B As shown. The liner 203 can be used as a stress-reducing layer for the metal layer 204 and / or as an adhesion-promoting layer for the metal layer 204. For example... Figure 2C As shown, metal layer 204 can be deposited on substrate 203. In some embodiments, metal layer 204 can be deposited by first depositing a seed layer (e.g., via sputtering) and then electroplating a conformal metal layer.

[0026] Then, a dielectric material 206 can be formed within the remaining portion of the hole 201, such as... Figure 2DAs shown. In some embodiments, the dielectric material 206 may be an organic dielectric material, such as, for example, ABF, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), poly(vinylpyridine) (PVP), etc. Although not shown, in some embodiments, a polishing step may then be performed to planarize the dielectric surface.

[0027] Next, as Figure 2E As shown, a hole 207 is formed in the dielectric material 206. In some embodiments, the hole 207 can be formed by a laser drilling process. Then, as... Figure 2F As shown, a metal layer 208 can be formed within the via 207. The metal layer 208 can be formed without using a seed layer because there is no taper requirement for these vias. In some embodiments, the metal layer 208 can be formed using a sintered metal paste (e.g., copper sintered paste), which can be varied to adjust the CTE or electrical properties of the sintered paste (e.g., by including magnetic particles). For example, in some embodiments, one or more filler materials can be included in the sintered metal paste. The paste material can then be sintered to form the final metal layer 208, which is the second part of the coaxial TGV structure. In some embodiments, an additional polishing step can be performed to planarize the top and bottom surfaces of the substrate before proceeding with a typical deposition process (which may include forming a deposited layer / metallization layer on each side of the substrate).

[0028] Figure 3 An example package substrate 300 is shown, comprising a glass core 302 having a coaxial TGV 320 according to an embodiment herein. Each TGV 320 includes a coaxial configuration similar to that of the TGV described above, including a first conductive layer 322 that can be formed by electroplating, a second conductive layer 326 that can be formed by sintering, and a dielectric layer 324 between the conductive layers 322 and 326. Each of these layers can be formed in the same or similar manner as described above. The substrate 300 also includes a dielectric liner 304 between the TGV 320 and the glass core 302.

[0029] Build-up layers 306A, 306B are formed on the top and bottom sides of the glass core 302, respectively: build-up layer 306A on the top side of the glass core 302 and build-up layer 306B on the bottom side of the glass core 302. The build-up layers 306A, 306B include metallization layers (e.g., 307) connected by vias (e.g., 309) that, together with the TGV 320, electrically couple the solder bumps 308 at the top of the package substrate 300 with the pads 310 at the bottom of the substrate. In certain cases, for example, integrated circuit dies can be coupled to the top side of the package substrate 300 and connected to the solder bumps 308, and the package substrate 300 can be coupled to a circuit board (e.g., a motherboard, a motherboard, etc.) via the pads 310 at the bottom of the package substrate 300. For example, the package substrate 300 can be included as a package substrate 604 in the system 600 of Figure 6A The package substrate 300 also includes a landing side capacitor 312 coupled on the bottom side of the package substrate 300.

[0030] Figure 4 An example multi-die package 400 having a glass core 402 with coaxial TGVs 420 is shown in accordance with embodiments herein. Each TGV 420 includes a coaxial morphology similar to that of the TGVs described above, including a first conductive layer 422 that can be formed via electroplating, a second conductive layer 426 that can be formed via sintering, and a dielectric layer 424 between the conductive layers 422, 426. Each of these layers can be formed in the same or similar manner as described above. The package 400 also includes a dielectric liner 404 between the TGVs 420 and the glass core 402.

[0031] The package 400 also includes build-up layers 406A, 406B formed on the top and bottom sides of the glass core 402, respectively, with build-up layer 406A formed on the top side of the glass core 402 and build-up layer 406B formed on the bottom side of the glass core 402. The layers 406A, 406B include metallization layers connected by vias similar to the examples described above that, together with the TGVs 420, electrically couple integrated circuit (IC) dies 412A, 412B at the top of the multi-die package 400 with pads 410 at the bottom of the package 400.

[0032] In addition, the package 400 includes a bridge component 414 in the build-up layer 406A that electrically couples the first IC die 412A with the second IC die 412B. The bridge component 414 can include passive and / or active components to interconnect the IC dies 412A, 412B. In certain embodiments, the bridge component 414 can be Embedded Multi-die Interconnect Bridge (EMIB). In some cases, the multi-die package 400 can be coupled to a circuit board (e.g., a motherboard, a motherboard, etc.) via the pads 410 at the bottom of the package 400. For example, the package 400 can be included as a multi-die package 614 into a system 610 of Figure 6B

[0033] Figure 5 Another example multi-die package 500 having glass cores 502 with coaxial TGVs 520 therein is shown in accordance with embodiments herein. Each TGV 520 includes a similar coaxial morphology to that of the TGVs described above, including a first conductive layer 522 that can be formed via electroplating, a second conductive layer 526 that can be formed via sintering, and a dielectric layer 524 between the conductive layers 522, 526. Each of these layers can be formed in the same or similar manner as described above. The package 500 also includes a dielectric liner 504 between the TGVs 520 and the glass cores 502.

[0034] The multi-die package 500 also includes build-up layers 506A, 506B formed on the top and bottom sides of the glass cores 502, respectively, where the build-up layer 506A is formed on the top side of the glass core 502 and the build-up layer 506B is formed on the bottom side of the glass core 502. The layers 506A, 506B include metallized layers connected by vias that, together with the TGVs 520, electrically couple integrated circuit (IC) dies 512A, 512B at the top of the multi-die package 500 to pads 510 at the bottom of the package 500.

[0035] The multi-die package 500 also includes a bridge component 514 similar to the bridge component 414 of the multi-die package 400; however, the bridge component 514 includes vias 516 from a top surface of the bridge component 514 to a bottom surface of the bridge component 514. The vias 516 can connect the IC dies 512A, 512B to particular traces, pillars, etc. within the build-up layer 506A. In certain embodiments, the bridge component 514 can be an Embedded Multi-die Interconnect Bridge (EMIB). In some cases, the multi-die package 500 can be coupled to a circuit board (e.g., a motherboard, a motherboard, etc.) via the pads 510 at the bottom of the package 500. For example, the package 500 can be included as a multi-die package 614 into a system 610 of Figure 6B

[0036] Figures 6A-6B Example systems 600, 610 that can include the glass core architectures described herein are shown. Figure 6A ​​The example system 600 includes a circuit board 602, which in some embodiments can be implemented as a motherboard or mainboard of a computer system. The example system 600 also includes a package substrate 604, with an integrated circuit die 606 attached to the package substrate 604. The die 606 can be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., Figure 7 The die 702 of the example system 700, Figure 8 The integrated circuit device 800) and / or one or more other suitable components. The die 606 can include one or more computing system components, such as one or more processor units (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller. In some embodiments, the die 606 can include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. In addition to including one or more processor units, the die 606 can also include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as the processor units, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor units. These separate integrated circuit dies can be referred to as “chiplets.” The package substrate 604 can provide electrical connections between the die 606 and the circuit board 602.

[0037] Similar to the system 600, the system 610 also includes a circuit board 612, which in some embodiments can be implemented as a motherboard or mainboard of a computer system. The system 610 also includes a multi-die package 614 that includes multiple integrated circuits / dies (e.g., 606), and interconnects between the dies in one or more metallization layers. The multi-die package 614 can include, for example, one or more silicon interposers, one or more silicon bridge interposers (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)), or a combination thereof.

[0038] The host circuit boards 602, 612 can provide electrical connections to other components of a computer system (e.g., memory, storage, network interfaces, peripherals, power supplies, etc.). The host circuit boards can include one or more traces and circuit components to provide interconnects between such computer system components.

[0039] Figure 7This is a top view of a wafer 700 and a die 702 that can be implemented or implemented in conjunction with any of the embodiments disclosed herein. The wafer 700 may be made of semiconductor material and may include one or more dies 702 having integrated circuit structures formed on the surface of the wafer 700. Each die 702 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After the semiconductor product is manufactured, the wafer 700 may undergo a dicing process, in which the dies 702 are separated from each other to provide discrete “chips” of the integrated circuit product. A die 702 may include one or more transistors (e.g., discussed below). Figure 8 The wafer 700 or die 702 may include some transistors in transistor 840, support circuitry for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 700 or die 702 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 702. For example, a memory array formed by multiple memory devices may be combined with a processor unit (e.g., Figure 9 The processor unit 902 or other logic units configured to store information in a memory device or execute instructions stored in a memory array are formed on the same die 702.

[0040] Figure 8 This can be a cross-sectional side view of an integrated circuit device 800 that may be included in any of the embodiments disclosed herein. One or more integrated circuit devices 800 may be included in one or more dies 702 ( Figure 7 The integrated circuit device 800 can be formed on the die substrate 802 (e.g., ...). Figure 7 On a 700 wafer, and may be included in a die (e.g., Figure 7The die substrate 802 can be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 802 can include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the die substrate 802 can be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV can also be used to form the die substrate 802. While several examples of materials that can form the die substrate 802 are described herein, any material that can be used as the basis for the integrated circuit device 800 can be used. The die substrate 802 can be a single-cut die (e.g., Figure 7 702 die) or wafer (e.g., Figure 7 A portion of the 700 wafer.

[0041] Integrated circuit device 800 may include one or more device layers 804 disposed on a die substrate 802. Device layer 804 may include features of one or more transistors 840 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 802. Transistor 840 may include, for example, one or more source and / or drain (S / D) regions 820, a gate 822 for controlling current flow between S / D regions 820, and one or more S / D contacts 824 for transmitting electrical signals to / from the S / D regions 820. Transistor 840 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. Transistor 840 is not limited to... Figure 8 The types and configurations described herein may include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or combinations thereof. Non-planar transistors may include: FinFET transistors, such as dual-gate transistors or tri-gate transistors; and gate-around or all-around transistors, such as nanoribbon, nanosheet, or nanowire transistors.

[0042] Return to Figure 8 The transistor 840 may include a gate 822 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one or more stacked layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0043] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using high-k materials, an annealing process may be performed on the gate dielectric to improve its quality.

[0044] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 840 is a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. For other purposes, additional metal layers, such as barrier layers, may be included.

[0045] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals discussed below with reference to NMOS transistors (e.g., for work function regulation). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals discussed above with reference to PMOS transistors (e.g., for work function regulation).

[0046] In some embodiments, when considered as a cross-section of the transistor 840 along the source-channel-drain direction, the gate electrode may be formed of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 802 and two sidewall portions substantially perpendicular to the top surface of the die substrate 802. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 802 and does not include the sidewall portions substantially perpendicular to the top surface of the die substrate 802. In other embodiments, the gate electrode may be formed of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may be formed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0047] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to surround the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0048] The S / D region 820 may be formed adjacent to the gate 822 of the individual transistor 840 within the die substrate 802. The S / D region 820 can be formed using, for example, implantation / diffusion processes or etching / deposition processes. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 802 to form the S / D region 820. Following the ion implantation process may be an annealing process to activate the dopants and allow them to diffuse further into the die substrate 802. In the latter process, the die substrate 802 may be etched to form a trench at the location of the S / D region 820. An epitaxial deposition process may then be performed to fill the trench with the material used to fabricate the S / D region 820. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide may be used to fabricate the S / D region 820. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials may be used to form the S / D region 820, such as germanium or group III-V materials or alloys. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 820.

[0049] It can be achieved through one or more interconnect layers set on device layer 804 (in Figure 8 The interconnect layers 806-810 transmit electrical signals, such as power and / or input / output (I / O) signals, to and / or from devices (e.g., transistor 840) in the device layer 804. For example, conductive features of the device layer 804 (e.g., gate 822 and S / D contact 824) may be electrically coupled to the interconnect structure 828 of the interconnect layers 806-810. One or more interconnect layers 806-810 may form a metallization stack (also referred to as an "ILD stack") 819 of the integrated circuit device 800.

[0050] Interconnection structure 828 can be arranged within interconnection layers 806-810 to transmit electrical signals according to a variety of designs; in particular, the arrangement is not limited to... Figure 8 The specific configuration of the interconnect structure 828 shown is illustrated. Although Figure 8A specific number of interconnect layers 806-810 are shown, but embodiments of this disclosure include integrated circuit devices having more or fewer interconnect layers than those shown.

[0051] In some embodiments, the interconnect structure 828 may include lines 828a and / or vias 828b filled with a conductive material such as a metal. Line 828a may be arranged to transmit electrical signals in a direction substantially parallel to the plane of the surface on which the device layer 804 is formed of the die substrate 802. For example, line 828a may be used to transmit electrical signals from... Figure 8 The via 828b transmits electrical signals in the direction of entering and exiting the page and / or in the direction of traversing the page. The via 828b can be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the die substrate 802 on which the device layer 804 is formed. In some embodiments, the via 828b can electrically couple lines 828a of different interconnect layers 806-810 together.

[0052] Interconnect layers 806-810 may include dielectric material 826 disposed between interconnect structures 828, such as Figure 8 As shown. In some embodiments, the dielectric material 826 disposed between interconnect structures 828 in different interconnect layers 806-810 may have different compositions; in other embodiments, the composition of the dielectric material 826 between different interconnect layers 806-810 may be the same. Device layer 804 may also include dielectric material 826 disposed between transistor 840 and the bottom layer of metallization stack. The dielectric material 826 included in device layer 804 may have a different composition than the dielectric material 826 included in interconnect layers 806-810; in other embodiments, the composition of the dielectric material 826 in device layer 804 may be the same as the dielectric material 826 included in any one of interconnect layers 806-810.

[0053] A first interconnect layer 806 (referred to as metal 1 or "M1") may be formed directly on device layer 804. In some embodiments, the first interconnect layer 806 may include a line 828a and / or a via 828b, as shown. The line 828a of the first interconnect layer 806 may be coupled to a contact of device layer 804 (e.g., S / D contact 824). The via 828b of the first interconnect layer 806 may be coupled to a line 828a of a second interconnect layer 808.

[0054] The second interconnect layer 808 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 806. In some embodiments, the second interconnect layer 808 may include vias 828b to couple lines 828a of the second interconnect layer 808 to lines 828a of the third interconnect layer 810. Although for clarity, lines 828a and vias 828b are structurally defined as lines within their respective interconnect layers, in some embodiments, lines 828a and vias 828b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0055] Based on similar techniques and configurations described in conjunction with the second interconnect layer 808 or the first interconnect layer 806, a third interconnect layer 810 (referred to as metal 3 or "M3") (and additional interconnect layers as needed) may be formed on the second interconnect layer 808. In some embodiments, the "higher" (i.e., further away from device layer 804) interconnect layers in the metallization stack 819 of the integrated circuit device 800 may be thicker than the lower interconnect layers in the metallization stack 819, wherein lines 828a and vias 828b in the higher interconnect layers are thicker than lines and vias in the lower interconnect layers.

[0056] The integrated circuit device 800 may include a solder resist 834 (e.g., polyimide or a similar material) and one or more conductive contacts 836 formed on interconnect layers 806-810. Figure 8 In this diagram, conductive contact 836 is shown in the form of a bonding pad. Conductive contact 836 may be electrically coupled to interconnect structure 828 and configured to transmit electrical signals from one or more transistors 840 to an external device. For example, solder bonding portions may be formed on one or more conductive contacts 836 to mechanically and / or electrically couple an integrated circuit die including integrated circuit device 800 to another component (e.g., a printed circuit board or package substrate, such as 612). Integrated circuit device 800 may include additional or alternative structures to transmit electrical signals from interconnect layers 806-810; for example, conductive contact 836 may include other similar features (e.g., posts) for transmitting electrical signals to external components.

[0057] In some embodiments where the integrated circuit device 800 is a double-sided die, the integrated circuit device 800 may include another metallization stack (not shown) on opposite sides of one or more device layers 804. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 806-810 to provide conductive paths (e.g., including conductive lines and vias) between one or more device layers 804 and additional conductive contacts (not shown) on the side of the integrated circuit device 800 opposite the conductive contacts 836.

[0058] In other embodiments where the integrated circuit device 800 is a double-sided die, the integrated circuit device 800 may include one or more through-silicon vias (TSVs) through the die substrate 802; these TSVs may contact one or more device layers 804 and may provide a conductive path between one or more device layers 804 and additional conductive contacts (not shown) on the side of the integrated circuit device 800 opposite to the conductive contacts 836. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from the conductive contacts on the side of the integrated circuit device 800 opposite to the conductive contacts 836 to transistors 840 and any other components integrated into the die, and the metallization stack 819 may be used to transmit I / O signals from the conductive contacts 836 to transistors 840 and any other components integrated into the die.

[0059] Multiple integrated circuit devices 800 can be stacked, wherein one or more TSVs in each stacked device provide connectivity between one device in the stack and any other device. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM dies can provide connectivity between the respective HBM and the base integrated circuit die. Conductive contacts can provide additional connectivity between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

[0060] Figure 9 This may be a block diagram of an example electrical device 900 that may include one or more embodiments disclosed herein. For example, any suitable component of the electrical device 900 may include one or more of the integrated circuit device 800 or integrated circuit die 702 disclosed herein. Multiple components in Figure 9 The components are shown as included in electrical device 900, but any one or more of these components may be omitted or copied to suit the application. In some embodiments, some or all of the components included in electrical device 900 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-a-chip (SoC) die.

[0061] Additionally, in various embodiments, electrical equipment 900 may not include... Figure 9The electrical device 900 may include one or more components as shown, but may include interface circuitry for coupling to one or more components. For example, the electrical device 900 may not include display device 906, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 906 may be coupled. In another set of examples, the electrical device 900 may not include audio input device 924 or audio output device 908, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 924 or audio output device 908 may be coupled.

[0062] Electrical device 900 may include one or more processor units 902 (e.g., one or more processor cells). As used herein, the terms "processor cell," "processing unit," or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processor unit 902 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Thus, a processor unit may be referred to as an XPU (or xPU).

[0063] Electrical device 900 may include memory 904, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard disk drive. In some embodiments, memory 904 may include memory located on the same integrated circuit die as processor unit 902. The memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), final level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0064] In some embodiments, electrical device 900 may include one or more processor units 902 that are heterogeneous or asymmetric to another processor unit 902 in electrical device 900. Various differences may exist between processor units 902 in the system in terms of a range of advantages, including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences can effectively demonstrate that they themselves are asymmetric and heterogeneous among the processor units 902 in electrical device 900.

[0065] In some embodiments, electrical device 900 may include communication component 912 (e.g., one or more communication components). For example, communication component 912 may manage wireless communication to facilitate the transmission of data to and from electrical device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data via a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not include any wiring, although in some embodiments they may not include wiring.

[0066] Communication component 912 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects, and any revisions, updates, and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are often referred to as WiMAX networks. WiMAX is an acronym for Global Interoperability for Microwave Access, and it is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. Communication component 912 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 912 may operate according to Enhanced Data Rate GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication component 912 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocols designated 3G, 4G, 5G, and higher generations. In other embodiments, communication component 912 may operate according to other wireless protocols. Electrical device 900 may include antenna 922 to facilitate wireless communication and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0067] In some embodiments, communication component 912 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 912 may include multiple communication components. For example, a first communication component 912 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 912 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 912 may be dedicated to wireless communications, and the second communication component 912 may be dedicated to wired communications.

[0068] Electrical device 900 may include battery / power circuit 914. Battery / power circuit 914 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 900 to an energy source (e.g., AC line power) separate from electrical device 900.

[0069] Electrical device 900 may include display device 906 (or the corresponding interface circuitry discussed above). Display device 906 may include one or more embedded or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0070] Electrical device 900 may include audio output device 908 (or the corresponding interface circuitry as discussed above). Audio output device 908 may include any embedded or wired or wirelessly connected external device that generates audible indicators, such as a speaker, headphones, or earbuds.

[0071] Electrical device 900 may include audio input device 924 (or corresponding interface circuitry as discussed above). Audio input device 924 may include any embedded or wired or wirelessly connected device that generates signals representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output). Electrical device 900 may include Global Navigation Satellite System (GNSS) device 918 (or corresponding interface circuitry as discussed above), such as a Global Positioning System (GPS) device. As is known in the art, GNSS device 918 can communicate with satellite-based systems and can determine the geographical location of electrical device 900 based on information received from one or more GNSS satellites.

[0072] Electrical device 900 may include other output devices 1910 (or corresponding interface circuits as discussed above). Examples of other output devices 1910 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0073] Electrical device 900 may include other input devices 920 (or corresponding interface circuits as discussed above). Examples of other input devices 920 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single-field-of-view or stereo cameras), trackballs, trackpads, touchpads, keyboards, cursor control devices such as mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, quick-response (QR) code readers, electrocardiogram (ECG) sensors, photoplethysmography (PPG) sensors, skin conductance sensors, any other sensors, or radio frequency identification (RFID) readers.

[0074] Electrical device 900 can have any desired form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablets, laptops, 2-in-1 foldable computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs), ultra-mobile personal computers, portable game consoles, etc.), desktop electrical devices, servers, rack-mount computing solutions (e.g., blade, tray, or sliding computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, fixed game consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems as part of a vehicle, smart home appliance, consumer electronics or device, or manufacturing equipment). In some embodiments, electrical device 900 can be any other electronic device that processes data. In some embodiments, electrical device 900 can include multiple discrete physical components. Considering the range of devices that electrical device 900 can present in various embodiments, in some embodiments, electrical device 900 may be referred to as a computing device or computing system.

[0075] The following provides illustrative examples of techniques described throughout this disclosure. Embodiments of these techniques may include any one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components illustrated in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes, and / or methods as illustrated in the examples below.

[0076] Example 1 is an apparatus comprising: a glass layer defining an opening between a first side of the glass layer and a second side of the glass layer opposite to the first side; a first conductive layer electrically coupling the first side of the glass layer and the second side of the glass layer within the opening; a second conductive layer electrically coupling the first side of the glass layer and the second side of the glass layer within the first conductive layer; and a dielectric between the first conductive layer and the second conductive layer.

[0077] Example 2 includes the subject of Example 1, wherein the second conductive layer comprises sintered metal.

[0078] Example 3 includes the subject of Example 2, wherein the second conductive layer further includes a filler material.

[0079] Example 4 includes the subject of Example 3, wherein the filler material comprises one of diamond, boron nitride, aluminum oxide, magnesium oxide, and silicon oxide.

[0080] Example 5 includes the subject of any one of Examples 1-4, wherein the dielectric comprises an organic material.

[0081] Example 6 includes the subject matter of Example 5, wherein the organic material comprises one or more of polyimide, polybenzoxazole, polycarbonate, benzocyclobutene (BCB), poly(vinylpyridine) (PVP), polyphenol, polyether, and polyacrylate.

[0082] Example 7 includes the subject of any one of Examples 1-6, wherein the first conductive layer has a generally annular cross-section and the second conductive layer has a generally circular cross-section.

[0083] Example 8 includes the subject matter of any one of Examples 1-7, wherein the dielectric is a first dielectric, and the device further includes a second dielectric between the glass layer and the first conductive layer.

[0084] Example 9 includes the subject of Example 8, wherein the second dielectric comprises a polymer.

[0085] Example 10 includes the subject matter of Example 8, wherein the second dielectric comprises silicon; and one of oxygen and nitrogen.

[0086] Example 11 includes the subject matter of any one of Examples 1-10, and further includes: a stacked layer on the glass layer, wherein a first metal trace in the stacked layer is connected to the first conductive layer, and a second metal trace in the stacked layer is connected to the second conductive layer.

[0087] Example 12 is a device comprising any one of the means described in Examples 1-11 and an integrated circuit die coupled to said means.

[0088] Example 13 is an apparatus comprising: a glass core layer including a plurality of through-glass vias (TGVs), at least one TGV comprising: an inner conductive layer extending from a top surface of the glass core layer to a bottom surface of the glass core layer; an outer conductive layer extending from the top surface to the bottom surface; a dielectric located between the inner conductive layer and the outer conductive layer and extending from the top surface to the bottom surface; and a stacked layer on the glass core layer and including metal traces, wherein a first metal trace of the stacked layer is connected to the inner conductive layer, and a second metal trace of the stacked layer is connected to the outer conductive layer.

[0089] Example 14 includes the subject of Example 13, wherein the second conductive layer comprises sintered metal.

[0090] Example 15 includes the subject of Example 14, wherein the second conductive layer further includes a filler material.

[0091] Example 16 includes the subject matter of Example 15, wherein the filler material comprises one of diamond, boron nitride, aluminum oxide, magnesium oxide, and silicon oxide.

[0092] Example 17 includes the subject matter of any one of Examples 13-16, wherein the dielectric comprises an organic material.

[0093] Example 18 includes the subject matter of any one of Examples 13-17, wherein the first conductive layer has a generally annular cross-section and the second conductive layer has a generally circular cross-section.

[0094] Example 19 is a device comprising any one of the means described in Examples 13-18 and an integrated circuit die coupled to said means.

[0095] Example 20 is a system comprising: an integrated circuit die; and a packaging substrate including: circuitry for interconnecting the integrated circuit die with a circuit board, the packaging substrate including: a glass core layer; a plurality of coaxial through-glass vias (TGVs) in the glass core layer, the coaxial TGVs extending from a top surface of the glass core layer to a bottom surface of the glass core layer and including: an outer conductive layer; an inner conductive layer; and a dielectric between the inner conductive layer and the outer conductive layer.

[0096] Example 21 includes the subject matter of Example 20, and further includes: a dielectric between the outer conductive layer and the glass core layer.

[0097] Example 22 includes the subject matter of any one of Examples 20-21, wherein the integrated circuit die includes a processor.

[0098] Example 23 includes the subject of any of Examples 20-22, and also includes: a circuit board coupled to a package substrate.

[0099] Example 24 is a method of forming a substrate, comprising: forming a hole in a glass layer extending from a first side of the glass layer to a second side of the glass layer; conformally depositing a first metal layer on an inner surface of the hole; forming a dielectric material within the first metal layer; forming a hole in the dielectric material; and forming a second metal layer in the hole in the dielectric material.

[0100] Example 25 includes the subject matter of Example 24, wherein forming the first metal layer includes electroplating, and forming the second metal layer includes heating and sintering paste.

[0101] Example 26 includes the subject matter of Example 25, wherein the sintering paste comprises sintered metal and one or more filler materials.

[0102] Example 27 includes the subject of any one of Examples 24-26, and further includes: forming a stacked layer comprising a plurality of metal traces, wherein a first metal trace is connected to the first metal layer and a second metal trace is connected to the second metal layer.

[0103] Example 28 includes products manufactured by any of the processes in Examples 24-27.

[0104] In the foregoing description, terms commonly used by those skilled in the art have been used to describe various aspects of the illustrative embodiments in order to convey the essence of the work to those skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced using only some of the described aspects. Specific quantities, materials, and configurations have been set forth for purposes of explanation to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without all the specific details. In other instances, well-known features have been omitted or simplified to avoid obscuring the illustrative embodiments.

[0105] Furthermore, the concepts described herein are illustrated in the accompanying drawings by way of example rather than limitation. It should be understood that in the examples further shown and described below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components. Additionally, it should be understood that although the transistor designs shown in some figures have orthogonal (e.g., vertical) boundaries for their source / drain regions, electrodes, etc., the embodiments herein may achieve such boundaries in a substantially orthogonal manner (e.g., differing from orthogonality by + / - 5 or 10 degrees) due to manufacturing methods used to produce such devices or for other reasons. Reference numerals may be repeated between certain figures where deemed appropriate to indicate corresponding or similar elements.

[0106] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). For the purposes of this disclosure, the phrase "A, and at least one of B and C" means (A and B), (A and C), or (A and B and C).

[0107] As used herein, the terms “above,” “below,” “between,” “above,” and “on” can refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with that other layer or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with both layers or may have one or more intermediate layers. Conversely, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intermediate features.

[0108] As used herein, the phrase “located on” in the context of a first layer or component being located on a second layer or component means that the first layer or component is directly and physically attached to the second layer or component (with no layer or component between the first and second layers or components) or is physically attached to the second layer or component through one or more intermediate layers or components. As used herein, the term “adjacent” means layers or components that are physically in contact with each other. That is, there are no layers or components between said adjacent layers or components. For example, layer X adjacent to layer Y means a layer that is physically in contact with layer Y.

[0109] The above description may use the phrases "in one embodiment" or "in an embodiment," which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this disclosure are synonymous.

[0110] The term “coupling” and its derivatives may be used in this document. “Coupling” can mean one or more of the following: “Coupling” can mean two or more elements in direct physical or electrical contact. However, “coupling” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between the elements referred to as being coupled to each other. The term “direct coupling” can mean two or more elements in direct contact.

[0111] In various embodiments, the phrase “first feature is formed, deposited or otherwise disposed on second feature” may mean that the first feature is formed, deposited or disposed on second feature, and at least a portion of the first feature may be in direct contact (e.g., direct physical and / or electrical contact) or indirect contact (e.g., having one or more other features between the first and second features) with at least a portion of the second feature.

[0112] Where this disclosure refers to an element called "a" or "first" or its equivalent, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Furthermore, ordinal numbers used for identified elements (e.g., first, second, or third) are used to distinguish elements and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular location or order of such elements unless expressly stated otherwise.

Claims

1. An apparatus comprising: A glass layer that defines an opening between a first side of the glass layer and a second side of the glass layer opposite to the first side; A first conductive layer is located within the opening, and the first conductive layer electrically couples the first side of the glass layer and the second side of the glass layer. A second conductive layer is located within the first conductive layer, and the second conductive layer electrically couples the first side of the glass layer to the second side of the glass layer. as well as A dielectric material is disposed between the first conductive layer and the second conductive layer.

2. The apparatus according to claim 1, wherein, The second conductive layer comprises sintered metal.

3. The apparatus according to claim 2, wherein, The second conductive layer also includes a filler material.

4. The apparatus according to claim 3, wherein, The filler material includes one of diamond, boron nitride, aluminum oxide, magnesium oxide, and silicon oxide.

5. The apparatus according to claim 1, wherein, The dielectric includes organic materials.

6. The apparatus according to claim 5, wherein, The organic materials include one or more of polyimide, polybenzoxazole, polycarbonate, benzocyclobutene (BCB), poly(vinylpyridine) (PVP), polyphenol, polyether, and polyacrylate.

7. The apparatus according to claim 1, wherein, The first conductive layer has a generally annular cross-section, and the second conductive layer has a generally circular cross-section.

8. The apparatus according to claim 1, wherein, The dielectric is a first dielectric, and the device further includes a second dielectric between the glass layer and the first conductive layer.

9. The apparatus according to claim 8, wherein, The second dielectric comprises a polymer.

10. The apparatus according to claim 8, wherein, The second dielectric includes: Silicon; and One of oxygen and nitrogen.

11. The apparatus according to any one of claims 1-10, further comprising a deposited layer on the glass layer, wherein, The first metal trace in the stacked layer is connected to the first conductive layer, and the second metal trace in the stacked layer is connected to the second conductive layer.

12. An apparatus comprising the device according to claim 1 and an integrated circuit die coupled to the device.

13. An apparatus comprising: The glass core layer includes multiple through-glass vias (TGVs), at least one of which includes: An inner conductive layer extends from the top surface of the glass core layer to the bottom surface of the glass core layer; An outer conductive layer extending from the top surface to the bottom surface; and A dielectric material located between the inner conductive layer and the outer conductive layer, extending from the top surface to the bottom surface; and A stacked layer on the glass core layer and including metal traces, wherein a first metal trace of the stacked layer is connected to the inner conductive layer, and a second metal trace of the stacked layer is connected to the outer conductive layer.

14. The apparatus according to claim 13, wherein, The inner conductive layer comprises sintered metal.

15. The apparatus according to claim 14, wherein, The inner conductive layer also includes a filler material.

16. The apparatus according to claim 15, wherein, The filler material includes one of diamond, boron nitride, aluminum oxide, magnesium oxide, and silicon oxide.

17. The apparatus according to claim 13, wherein, The dielectric includes organic materials.

18. The apparatus according to any one of claims 13-17, wherein, The outer conductive layer has a generally annular cross-section, and the inner conductive layer has a generally circular cross-section.

19. An apparatus comprising the means of claim 13 and an integrated circuit die coupled to the means of claim 13.

20. A system comprising: Integrated circuit die; as well as A packaging substrate, including circuitry for interconnecting the integrated circuit die with a circuit board, the packaging substrate comprising: Glass core layer; Multiple coaxial through-glass vias (TGVs) are provided in the glass core layer, the coaxial TGVs extending from the top surface of the glass core layer to the bottom surface of the glass core layer, and include: an outer conductive layer; an inner conductive layer; and a dielectric between the inner conductive layer and the outer conductive layer.

21. The system of claim 20, further comprising a dielectric between the outer conductive layer and the glass core layer.

22. The system of claim 20 or 21, further comprising a circuit board coupled to the package substrate, wherein, The integrated circuit die includes a processor.

23. A method of forming a substrate, comprising: A hole is formed in the glass layer, the hole extending from a first side of the glass layer to a second side of the glass layer; A first metal layer is conformally deposited on the inner surface of the hole; A dielectric material is formed within the first metal layer; A hole is formed in the dielectric material; as well as A second metal layer is formed in the pores of the dielectric material.

24. The method according to claim 23, wherein, Forming the first metal layer includes electroplating, and forming the second metal layer includes heating and sintering paste.

25. The method according to claim 23 or 24, further comprising: A stacked layer comprising multiple metal traces is formed, wherein a first metal trace is connected to the first metal layer and a second metal trace is connected to the second metal layer.

Images