Layered packaging structure and layered packaging method of power device

Abstract

The application relates to a layered packaging structure and a layered packaging method of a power device. The layered packaging structure of the power device comprises a driving circuit layer, a power circuit layer and a chip layer which are sequentially stacked, the driving circuit layer can be electrically connected with the power circuit layer through a first hole, and the driving circuit layer can be electrically connected with the chip layer through a second hole and a third hole, so that the driving circuit layer can drive the chip layer to work. Compared with a traditional scheme of realizing electrical connection based on a bonding wire, the layered packaging structure of the power device is a three-dimensional space layout structure, there is no conductive line between the layers, the interlayer electric field concentration can be avoided, the electrical connection between the layers depends on the first hole, the second hole and the third hole, so that the direct connection of the driving circuit layer and the power circuit layer, the direct connection of the driving circuit layer and the chip layer and the direct connection of the power circuit layer and the chip layer are realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power devices, in particular to a layered packaging structure and a layered packaging method of a power device. BACKGROUND

[0002] With the rapid development of the new energy industry, SiC (Silicon Carbide) power devices have great advantages in high-voltage, high-frequency and high-temperature application fields due to their excellent performance such as high breakdown electric field strength, high electron saturation drift speed and high thermal conductivity. However, the parasitic inductance of the SiC power module is high under the traditional packaging technology of the SiC power module. SUMMARY

[0003] Therefore, it is necessary to provide a layered packaging structure and a layered packaging method of a power device capable of reducing parasitic inductance.

[0004] In a first aspect, a layered packaging structure of a power device is provided, comprising: a driving circuit layer, a power circuit layer and a chip layer which are stacked in sequence.

[0005] The driving circuit layer has a first hole and a second hole, the power circuit layer has a third hole, and the first hole, the second hole and the third hole are filled with conductive paste; the projection of the second hole on the driving circuit layer on the power circuit layer coincides with the third hole.

[0006] The driving circuit layer is connected to the power circuit layer through the first hole, the driving circuit layer is connected to the chip layer through the second hole and the third hole, and the power circuit layer is connected to the chip layer through the third hole; the driving circuit layer is used to drive the chip layer.

[0007] In one of the embodiments, the driving circuit layer comprises: a first driving circuit layer and a second driving circuit layer which are stacked in sequence.

[0008] The first driving circuit layer is arranged farther away from the power circuit layer than the second driving circuit layer.

[0009] The first hole comprises a first sub-hole on the first driving circuit layer and a second sub-hole on the second driving circuit layer, and the projection of the first sub-hole on the second driving circuit layer coincides with the second sub-hole.

[0010] The first driving circuit layer is connected to the power circuit layer through the first sub-hole and the second sub-hole, and the second driving circuit layer is connected to the chip layer through the second hole and the third hole; the first driving circuit layer and the second driving circuit layer are both used to drive the chip layer.

[0011] In one of the embodiments, the first driving circuit layer comprises: a first ceramic plate and a first driving circuit circuit integrated on the first ceramic plate.

[0012] The signal lines of the first drive circuit extend to the first sub-holes;

[0013] The second drive circuit layer comprises a second ceramic plate and a second drive circuit integrated on the second ceramic plate;

[0014] The signal lines of the second drive circuit extend to the second holes.

[0015] In one embodiment, the first drive circuit comprises a first upper bridge circuit and a first lower bridge circuit arranged independently, and the second drive circuit comprises a second upper bridge circuit and a second lower bridge circuit arranged independently;

[0016] The projection of the circuit region where the first upper bridge circuit is located on the second drive circuit coincides with the circuit region where the second upper bridge circuit is located, and the projection of the circuit region where the first lower bridge circuit is located on the second drive circuit coincides with the circuit region where the second lower bridge circuit is located; wherein the distance between the first upper bridge circuit and the first lower bridge circuit is greater than or equal to the insulation distance under a preset voltage requirement;

[0017] The signal lines of the first upper bridge circuit extend to the first upper bridge holes in the first sub-holes, and the signal lines of the first lower bridge circuit extend to the first lower bridge holes in the first sub-holes; the signal lines of the second upper bridge circuit extend to the second upper bridge holes in the second holes, and the signal lines of the second lower bridge circuit extend to the second lower bridge holes in the second holes.

[0018] In one embodiment, the power circuit layer comprises a third upper bridge circuit and a third lower bridge circuit arranged independently, and a third ceramic plate integrating the third upper bridge circuit and the third lower bridge circuit;

[0019] The signal lines and the power lines are vertically routed; wherein the signal lines comprise the signal lines of the first drive circuit and the signal lines of the second drive circuit, and the power lines comprise the power lines of the third upper bridge circuit and the power lines of the third lower bridge circuit;

[0020] The signal lines of the third upper bridge circuit extend to the third upper bridge holes in the third holes, and the signal lines of the third lower bridge circuit extend to the third lower bridge holes in the third holes.

[0021] In a second aspect, a layered packaging method of a power device comprises:

[0022] A drive circuit layer and a power circuit layer are provided; wherein the drive circuit layer has first holes and second holes, the power circuit layer has third holes, and the first holes, the second holes and the third holes are filled with conductive paste;

[0023] The driving circuit layer and the power circuit layer are stacked to obtain a laminated structure; wherein the second hole on the driving circuit layer is projected on the power circuit layer and overlaps the third hole;

[0024] The laminated structure is sintered in an environment with a temperature in a range of 600-900 DEG C to obtain a low-temperature co-fired ceramic plate;

[0025] A chip layer is prepared, and the low-temperature co-fired ceramic plate is stacked with the chip layer;

[0026] The low-temperature co-fired ceramic plate and the chip layer are sintered to obtain a power device.

[0027] In one of the embodiments, the preparation steps of the driving circuit layer and the power circuit layer include:

[0028] A ceramic slurry is prepared based on a ceramic powder and a slurry;

[0029] A first carrier film and a second carrier film are prepared;

[0030] The ceramic slurry is uniformly coated on the first carrier film and the second carrier film respectively by a casting machine to obtain a first green ceramic tape and a second green ceramic tape;

[0031] Holes are punched on the first green ceramic tape to form the first hole and the second hole;

[0032] Holes are punched on the second green ceramic tape to form the third hole;

[0033] The first hole, the second hole and the third hole are filled with conductive slurry respectively;

[0034] The driving circuit layer is formed by driving circuit printing on the first green ceramic tape;

[0035] The power circuit layer is formed by power circuit printing on the second green ceramic tape.

[0036] In one of the embodiments, the punching method is one of mechanical punching, laser punching or photoetching punching.

[0037] In one of the embodiments, the first carrier film includes a first sub-carrier film and a second sub-carrier film, and the first green ceramic tape includes a first sub-green ceramic tape and a second sub-green ceramic tape;

[0038] The step of punching holes on the first green ceramic tape to form the first hole and the second hole includes:

[0039] The first sub-hole is formed by punching holes on the first sub-green ceramic tape;

[0040] The second sub green ceramic belt is punched to form a second sub hole and a second hole; wherein the first hole includes the first sub hole and the second sub hole, and the projection of the first sub hole on the second sub green ceramic belt coincides with the second sub hole.

[0041] In one of the embodiments, after the step of stacking the driving circuit layer and the power circuit layer to obtain the laminated structure, and before the step of sintering the laminated structure, further comprising:

[0042] placing the laminated structure in air or inert gas;

[0043] increasing the heating temperature of the laminated structure at a preset change rate until the temperature of the laminated structure is maintained in the temperature range of 300-500°C.

[0044] The layered packaging structure of the power device includes: a driving circuit layer, a power circuit layer and a chip layer stacked in sequence, the driving circuit layer can be electrically connected with the power circuit layer through the first hole, and the driving circuit layer can be electrically connected with the chip layer through the second hole and the third hole, so that the driving circuit layer can drive the chip layer to make the power device work. Compared with the traditional scheme of realizing electrical connection based on bonding wire, the layered packaging structure of the power device is a three-dimensional space layout structure, there is no conductive line between the layers, the electrical connection between the layers depends on the first hole, the second hole and the third hole, thereby realizing the direct connection of the driving circuit layer and the power circuit layer, the direct connection of the driving circuit layer and the chip layer, and the direct connection of the power circuit layer and the chip layer. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0046] Figure 1 One of the structural block diagrams of the layered packaging structure of the power device of an embodiment;

[0047] Figure 2 One of the structural block diagrams of the layered packaging structure of the power device of an embodiment;

[0048] Figure 3 One of the structural block diagrams of the layered packaging structure of the power device of an embodiment;

[0049] Figure 4 One of the structural block diagrams of the first driving circuit layer of an embodiment;

[0050] Figure 5 a structure block diagram of a second drive circuit layer of an embodiment;

[0051] Figure 6 a schematic diagram of a substrate of a first drive circuit layer and a second drive circuit layer of an embodiment;

[0052] Figure 7 a structure block diagram of a power circuit layer of an embodiment;

[0053] Figure 8 a schematic diagram of a substrate of a power circuit layer of an embodiment;

[0054] Figure 9 a flow chart of a layered packaging method of a power device of an embodiment. DETAILED DESCRIPTION

[0055] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description and the accompanying drawings. In the Figures, embodiments of the application are illustrated by way of example. It is to be expressly understood that the drawings are for illustrative purposes and are not a limitation on the scope of the application. It is to be further expressly understood that the specific embodiments presented herein are merely representative of the application and should not be construed as limiting the scope of the application.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0057] It should be understood that the terms "first", "second" and so on as used herein can be used to describe various elements or circuits, but these elements or circuits are not limited by these terms. These terms are only used to distinguish the first element or circuit from another element or circuit. For example, without departing from the scope of the application, the first upper bridge circuit can be referred to as the second upper bridge circuit, and similarly, the second upper bridge circuit can be referred to as the first upper bridge circuit. The first upper bridge circuit and the second upper bridge circuit are both upper bridge circuits, but they are not the same upper bridge circuit.

[0058] It should be understood that "connection" in the following embodiments means that if the circuits, modules, units, etc. connected to each other have transmission of electrical signals or data, it should be understood as "electrical connection", "communication connection", etc.

[0059] It should be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of an element" means part or all of the element.

[0060] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. Also, the term "and / or" includes any and all combinations of associated items.

[0061] Under the traditional packaging, the electromagnetic compatibility problem exists in the power device, and the improvement of the power density is limited. When the power device includes multiple chips, the difficulty of thermal management is great, and the problem of uneven device junction temperature exists, thereby causing the reliability of the power device to decrease.

[0062] The existing SiC power module generally adopts the electrical connection mode of copper wire or aluminum wire bonding with a wire diameter of 12-20 μm. Such electrical connection mode will generate a large voltage spike in the case of a very high switching frequency. Meanwhile, when the driving circuit corresponding to the power module and the main power circuit of the power module are wired on the same plane, a serious electromagnetic coupling problem is caused, and there is also a problem that the rising edge ringing amplitude of the driving signal exceeds 30% of the power voltage. In order to reduce electromagnetic coupling, most power modules adopt a laminated design, and organic substrates such as FR-4 substrate (Flame Retardant 4, glass fiber reinforced epoxy resin substrate of 4th class), BT resin substrate (Bismaleimide Triazine Resin Substrate, bismaleimide triazine resin substrate) and DBC ceramic substrate (Direct Bonded Copper Ceramic Substrate, directly bonded copper ceramic substrate) or DBC substrate are mostly used. However, the dielectric loss of the organic substrate increases significantly under high temperature and high frequency, and the reliability is poor. Although the thermal conductivity of the DBC substrate is relatively high, the multi-layer wiring capability of the DBC substrate is limited, and it is difficult to realize complex circuit integration.

[0063] In the prior art, the length of the wire bonding of the power module is too long, which causes the parasitic inductance of the driving circuit to be in the numerical range of 5-10 nH, the stray inductance of the main circuit to be in the numerical range of ≥10 nH, and the switching loss to account for a large proportion of the total loss at a high switching frequency.

[0064] Further, the wire bonding of the power module is prone to fatigue fracture in the power cycle, and the wire bonding is limited in size and has limited current carrying capacity. Moreover, the height of the bonding wire limits the thickness of the power module.

[0065] In one specific embodiment, as Figure 1As shown, a layered packaging structure 10 of a power device is provided, comprising: a driving circuit layer 102, a power circuit layer 104 and a chip layer 106 which are sequentially stacked.

[0066] The driving circuit layer has a first hole 108 and a second hole 110, and the power circuit layer has a third hole 112, and the first hole, the second hole and the third hole are filled with conductive paste; the projection of the second hole on the power circuit layer coincides with the third hole. The conductive paste is a ceramic paste with low dielectric constant.

[0067] The driving circuit layer is connected with the power circuit layer through the first hole, the driving circuit layer is connected with the chip layer through the second hole and the third hole, and the power circuit layer is connected with the chip layer through the third hole; the driving circuit layer is used to drive the chip layer.

[0068] The first hole is filled with conductive paste, so that the electrical signal between the driving circuit layer and the power circuit layer can be transmitted through the first hole; similarly, the second hole and the third hole are also filled with conductive paste, that is, the second hole and the third hole support the transmission of electrical signal, so that the driving circuit layer can be connected with the chip layer through the second hole and the third hole, and the power circuit layer can be connected with the chip layer through the third hole. It should be noted that the number of the first hole, the second hole and the third hole is at least one.

[0069] The greater the contact area between the conductive paste in the second hole and the conductive paste in the third hole, the higher the electrical connection reliability between the second hole and the third hole. The projection of the second hole on the power circuit layer coincides with the third hole, which can maximize the contact area between the conductive paste in the second hole and the conductive paste in the third hole, thereby maximizing the electrical connection reliability between the second hole and the third hole and ensuring the correct transmission of electrical signal.

[0070] The layered packaging structure of the power device comprises: a driving circuit layer, a power circuit layer and a chip layer which are sequentially stacked. The driving circuit layer can be electrically connected with the power circuit layer through the first hole, and the driving circuit layer can be electrically connected with the chip layer through the second hole and the third hole, so that the driving circuit layer can drive the chip layer to make the power device work. Compared with the traditional scheme of realizing electrical connection based on bonding wire, the layered packaging structure of the power device is a three-dimensional space layout structure, and there is no conductive line between the layers, which can avoid the concentration of interlayer electric field, and the electrical connection between the layers depends on the first hole, the second hole and the third hole, thereby realizing the direct connection of the driving circuit layer with the power circuit layer, the direct connection of the driving circuit layer with the chip layer and the direct connection of the power circuit layer with the chip layer.

[0071] The layered packaging structure of the power device can make the creepage distance of the power loop layer and the driving loop layer be greater than or equal to 1.5 mm, so as to meet the high-low voltage isolation requirement of the power device in the safety specification. Compared with the traditional scheme of realizing electrical connection based on a bonding wire, the parasitic inductance generated by the electrical connection scheme based on the hole direct connection is lower, the fatigue fracture of the bonding wire in the power cycle is excluded, and the cycle reliability of the power device is improved; and the occupation height of the hole is small, which is conducive to the miniaturization design of the power device.

[0072] In one specific embodiment, as shown in Figure 2 and Figure 3 The driving loop layer includes: a first driving loop layer 1022 and a second driving loop layer 1024 which are sequentially stacked.

[0073] The first driving loop layer is arranged away from the power loop layer compared with the second driving loop layer.

[0074] The first hole includes a first sub-hole 1082 on the first driving loop layer and a second sub-hole 1084 on the second driving loop layer, and the projection of the first sub-hole on the second driving loop layer coincides with the second sub-hole.

[0075] The first driving loop layer is connected with the power loop layer through the first sub-hole and the second sub-hole, and the second driving loop layer is connected with the chip layer through the second hole and the third hole; the first driving loop layer and the second driving loop layer are both used for driving the chip layer.

[0076] The first driving loop layer is a G-pole (Gate, gate) driving loop layer, and the first driving loop layer is used for outputting a first driving signal to the gate of the chip layer to control the rising edge or the falling edge of the gate voltage of the chip layer, so as to realize the fast switching of the chip layer.

[0077] The second driving loop layer is a KS-pole (Kelvin Source, Kelvin source pole) driving loop layer, and the second driving loop layer is used for outputting a second driving signal to the chip layer to control the switching of the chip layer.

[0078] Since the first driving loop layer is at the same potential as the power loop layer, the first driving loop layer needs to establish an electrical connection relationship with the power loop layer, and since the second driving loop layer is arranged between the second driving loop layer and the power loop layer, the first sub-hole on the first driving loop layer needs to establish an electrical connection relationship with the second sub-hole on the second driving loop layer, so as to realize the electrical connection between the first driving loop layer and the power loop layer.

[0079] The greater the contact area between the conductive paste in the first sub-hole and the conductive paste in the second sub-hole, the higher the electrical connection reliability between the first sub-hole and the second sub-hole. The projection of the first sub-hole on the second drive circuit layer coincides with the second sub-hole, which maximizes the contact area between the conductive paste in the first sub-hole and the conductive paste in the second sub-hole, thereby maximizing the electrical connection reliability between the first sub-hole and the second sub-hole and ensuring correct transmission of the first drive signal.

[0080] Further, since the electrical connection has been established between the first drive circuit layer and the power circuit layer, the second hole can be provided only on the second drive circuit layer, so that the second drive circuit layer is connected to the chip layer through the second hole and the third hole, and the first drive circuit layer is electrically connected to the chip layer through the electrical connection relationship of the first drive circuit layer-power circuit layer-chip layer, thereby reducing the process complexity of the layered packaging structure of the power device.

[0081] Based on the electrical connection scheme of hole direct connection, the transmission delay of the layered packaging structure of the power device is ≤1 ns, and the switching drive of the power device can be realized within 100 ns. Moreover, the switching loss of the layered packaging structure of the power device is low, which can support high-frequency operation of 150 kHz.

[0082] In one embodiment, as shown in FIG. 1, the layered packaging structure of the power device includes a chip layer 1060, a first drive circuit layer 1020, a power circuit layer 1040, and a second drive circuit layer 1030. Figure 2 The chip layer includes a copper-clad ceramic carrier board 1062 and a chip 1064.

[0083] The copper-clad ceramic carrier board can be an AMB board (Active Metal Brazed Copper Clad Ceramic Substrate), which is a high-performance electronic packaging material that realizes high-strength combination of a copper layer and a ceramic substrate through an active metal brazing process. The AMB board can withstand more than 3000 thermal cycles (-40°C to 125°C) and has an insulation withstand voltage of more than 10 kV / mm. It can work stably for a long time in a high-temperature environment of more than 175°C and has high reliability. The power device with the AMB board is suitable for harsh outdoor or vehicle-mounted environments.

[0084] In one specific embodiment, as shown in FIG. 1, the first drive circuit layer includes a first ceramic board and a first drive circuit integrated on the first ceramic board. Figure 4 The first drive circuit includes a first drive circuit integrated on the first ceramic board.

[0085] The signal line of the first drive circuit extends to the first sub-hole.

[0086] The signal line of the first driving circuit circuit extends to the first sub-hole, such that the output end of the signal line of the first driving circuit circuit is in contact with the first sub-hole, thereby guiding the driving signal of the first driving circuit circuit into the first sub-hole through the first sub-hole, and transmitting the driving signal of the first driving circuit circuit into the power circuit layer through the first sub-hole and the second sub-hole.

[0087] As shown in Figure 5 , the second driving circuit layer comprises a second ceramic plate and a second driving circuit circuit integrated on the second ceramic plate.

[0088] The signal line of the second driving circuit circuit extends to the second hole.

[0089] The signal line of the second driving circuit circuit extends to the second hole, such that the output end of the signal line of the second driving circuit circuit is in contact with the second hole, thereby guiding the driving signal of the second driving circuit circuit into the second hole through the second hole, and transmitting the driving signal of the second driving circuit circuit into the chip layer through the second hole.

[0090] The wiring structure of the signal line and the ground line of the first driving circuit circuit and the second driving circuit circuit can both be parallel wiring structures. In the case of using a 100 μm thick electrolytic copper foil and a line width of 200 μm, according to the transmission line theory, when the line length ≤ 5 mm, the characteristic impedance can be controlled within the range of 50 ± 5 Ω, so that when the rising edge time of the signal ≤ 5 ns, low distortion signal transmission can still be maintained.

[0091] In a specific embodiment, as shown in Figure 4 and Figure 5 , the first driving circuit circuit comprises a first upper bridge circuit and a first lower bridge circuit arranged independently, and the second driving circuit circuit comprises a second upper bridge circuit and a second lower bridge circuit arranged independently.

[0092] The projection of the circuit region where the first upper bridge circuit is located on the second driving circuit circuit coincides with the circuit region where the second upper bridge circuit is located, and the projection of the circuit region where the first lower bridge circuit is located on the second driving circuit circuit coincides with the circuit region where the second lower bridge circuit is located; wherein the distance between the first upper bridge circuit and the first lower bridge circuit is greater than or equal to the insulation distance under the preset voltage requirement.

[0093] The signal line of the first upper bridge circuit extends to the first upper bridge hole in the first sub-hole, and the signal line of the first lower bridge circuit extends to the first lower bridge hole in the first sub-hole; the signal line of the second upper bridge circuit extends to the second upper bridge hole in the second hole, and the signal line of the second lower bridge circuit extends to the second lower bridge hole in the second hole.

[0094] The preset voltage requirement can be the insulation withstand voltage requirement of the power circuit layer. In one embodiment, the insulation withstand voltage requirement of the power circuit layer is above 2500V, then the preset voltage requirement can be set to above 2500V accordingly.

[0095] The first drive circuit is configured as a first upper bridge circuit and a first lower bridge circuit, and the first upper bridge circuit and the first lower bridge circuit are integrated into a... Figure 6 On the substrate shown, the stray inductance of the first drive circuit can be reduced. Similarly, the second drive circuit is configured as a second upper bridge circuit and a second lower bridge circuit, and the second upper bridge circuit and the second lower bridge circuit are integrated on a substrate as shown. Figure 6 On the substrate shown, the stray inductance of the second drive circuit can be reduced so that the inductance of the drive circuit layer is reduced to less than 6nH.

[0096] In one embodiment, the first ceramic plate can be formed by low-pressure sintering of three green ceramic strips with different dielectric constants, the total thickness of the first ceramic plate is 200μm, and the dielectric strength is ≥8kV / mm.

[0097] In one embodiment, the second ceramic plate can also be formed by low-pressure sintering of three green ceramic strips with different dielectric constants, with a total thickness of 150 μm and a dielectric strength ≥8 kV / mm.

[0098] In a specific embodiment, such as Figure 7 As shown, the power circuit layer includes: a third upper bridge circuit and a third lower bridge circuit that are independently configured, and a third ceramic plate that integrates the third upper bridge circuit and the third lower bridge circuit.

[0099] The signal lines and power lines are routed vertically; the signal lines include the signal lines of the first drive circuit and the signal lines of the second drive circuit, and the power lines include the power lines of the third upper bridge circuit and the power lines of the third lower bridge circuit.

[0100] The signal line of the third upper bridge circuit extends to the third upper bridge hole in the third hole, and the signal line of the third lower bridge circuit extends to the third lower bridge hole in the third hole.

[0101] The vertical wiring structure between the first and second drive loop circuits and the circuits on the power loop layer can reduce crosstalk between the circuits on the power loop layer and the drive loop circuits (i.e., the first and second drive loop circuits).

[0102] Similar to the first upper bridge circuit and the first lower bridge circuit, the third upper bridge circuit and the third lower bridge circuit are set up separately and integrated into a single circuit, such as... Figure 8 On the substrate shown, stray inductance of the power circuit layer can be reduced, voltage spikes can be reduced, and voltage oscillations of power devices during turn-off can be effectively suppressed.

[0103] In one embodiment, the first drive circuit layer, the second drive circuit layer and the power circuit layer can all use 100 μm thick electrolytic copper foil as the conductive medium, such copper foil has purity ≥ 99.9% and conductivity up to 5.9 x 10 7 S / m, the on-resistance of the circuit can be controlled below 1 mΩ, thereby ensuring the current carrying capacity of the first drive circuit layer, the second drive circuit layer and the power circuit layer.

[0104] In one embodiment, the power circuit layer can use 90 μm thick electrolytic copper foil as the conductive medium, and the thinner electrolytic copper foil is more conducive to the miniaturization design of the power device.

[0105] In one embodiment, the first ceramic plate, the second ceramic plate and the third ceramic plate can be prepared based on the LTCC technology (Low - Temperature Co - fired Ceramic), which refers to the ceramic-based multilayer integration technology sintered below 900℃. The first ceramic plate, the second ceramic plate and the third ceramic plate prepared based on the LTCC technology have high insulation, low dielectric loss and good thermal conductivity, thereby improving the reliability of the power device.

[0106] In one embodiment, the pins below the power circuit layer can be connected to the surface of the chip layer through a sintering process to form a sintered silver layer with a thickness of 25 μm. The sintering process has a shear strength ≥ 45 MPa, and the thermal conductivity of the power device obtained based on the sintering process is ≥ 150 W / m·K, which is 3 times the thermal conductivity of the traditional solder.

[0107] The power device uses the double bus laminated structure arranged in the upper bridge circuit and the lower bridge circuit, and also forms a coupling capacitor based on the LTCC multilayer copper foil, which can reduce the layout stray inductance to less than 3 nH.

[0108] In one embodiment, elements can be embedded on the drive circuit layer and / or the power circuit layer to integrate components such as capacitors and resistors that can realize RC circuit (Resistor-Capacitance circuit) on the drive circuit layer and / or the power circuit layer, thereby reducing the peak voltage of the module.

[0109] In one specific embodiment, as shown in FIG. 1, a layered packaging method of a power device includes: Figure 9

[0110] S902, providing a drive circuit layer and a power circuit layer; wherein the drive circuit layer has a first hole and a second hole, the power circuit layer has a third hole, and the first hole, the second hole and the third hole are all filled with conductive paste.​

[0111] S904, the driving circuit layer and the power circuit layer are stacked to obtain a laminated structure; wherein the second hole on the driving circuit layer is projected on the third hole on the power circuit layer.

[0112] The driving circuit layer and the power circuit layer can be stacked by a laminating machine to obtain a laminated structure. Specifically, the driving circuit layer and the power circuit layer are tightly combined to form an integrated laminated structure under the temperature environment of 50-100℃ and the pressure environment of 5-30MPa.

[0113] During the laminating process, the uniformity of the pressure needs to be controlled to avoid the phenomenon of interlayer bubbles or misplacement of the laminated structure, thereby ensuring the structural integrity of the power device after subsequent sintering.

[0114] S906, sintering the laminated structure in an environment with a temperature in the range of 600-900℃ to obtain a low-temperature co-fired ceramic board.

[0115] In an environment with a temperature in the range of 600-900℃, the laminated structure can be heat preserved, and the shortest heat preservation time can be 1 hour and the longest heat preservation time can be 4 hours. Heat preservation can sinter and densify the ceramic powder of the laminated structure, and at the same time, sinter the metal paste on the laminated structure to form conductive lines and vias.

[0116] In the case where the difference between the sintering shrinkage rate of the ceramic of the low-temperature co-fired ceramic board and the sintering shrinkage rate of the metal is ≥1%, stress will be generated, resulting in warping or cracking of the low-temperature co-fired ceramic board. Therefore, during the sintering process, shrinkage control is needed to make the difference between the sintering shrinkage rate of the ceramic of the laminated structure and the sintering shrinkage rate of the metal <1%.

[0117] S908, preparing a chip layer and stacking the low-temperature co-fired ceramic board and the chip layer.

[0118] S910, sintering the low-temperature co-fired ceramic board and the chip layer to obtain a power device.

[0119] The layered packaging method of the power device described above can obtain a power device based on hole direct connection. There is no conductive line between the layers of such a power device, which can avoid interlayer electric field concentration, and the electrical connection between the layers depends on the first hole, the second hole and the third hole, thereby realizing the direct connection of the driving circuit layer and the power circuit layer, the direct connection of the driving circuit layer and the chip layer, and the direct connection of the power circuit layer and the chip layer.

[0120] In one embodiment, the step of sintering the low-temperature co-fired ceramic board and the chip layer to obtain a power device comprises:

[0121] sintering the low-temperature co-fired ceramic plate and the chip layer to obtain a combined module.

[0122] welding the three combined modules to a base plate to obtain a power device.

[0123] In one embodiment, the determining step of the chip layer comprises:

[0124] preparing a chip circuit and an AMB plate.

[0125] sintering the chip circuit and the AMB plate to obtain a chip layer.

[0126] In one specific embodiment, the preparing steps of the driving circuit layer and the power circuit layer comprise:

[0127] preparing and formulating a ceramic slurry based on ceramic powder and slurry.

[0128] The ceramic powder needs to be selected from powder materials capable of satisfying low-temperature sintering characteristics, such as glass ceramics (e.g., borosilicate glass and Al2O3, SiO2 composite materials), cordierite (2MgO·2Al2O3·5SiO2), spinel (MgAl2O4), and other low-melting-point ceramics. Among them, the glass phase can be melted at low temperature to promote ceramic densification. The particle size of the ceramic powder needs to be controlled in the sub-micron level (1-5 μm) to reduce the sintering temperature and ensure the density.

[0129] The ceramic powder is mixed with an organic binder, a plasticizer, and a solvent, and is ball milled to form a uniform ceramic slurry, i.e., a casting slurry. The viscosity of the ceramic slurry needs to be precisely controlled. For example, the viscosity of the ceramic slurry can be controlled in the range of 1000-5000 cP. The organic binder can be polyvinyl alcohol, acrylate.

[0130] Preparation of the first carrier film and the second carrier film. Among them, the first carrier film and the second carrier film can be PET (Polyethylene Terephthalate) film.

[0131] The ceramic slurry is uniformly coated on the first carrier film and the second carrier film by a casting machine to correspondingly obtain a first green ceramic tape and a second green ceramic tape.

[0132] The ceramic slurry is uniformly coated on the first carrier film and the second carrier film by a casting machine, and the solvent is removed by a drying operation to form first and second green ceramic tapes with uniform thickness. The temperature of the drying operation can be in the temperature range of 60-100°C.

[0133] The thickness of the first green ceramic tape and the second green ceramic tape can be adjusted according to requirements. Generally, the thickness of the first green ceramic tape and the second green ceramic tape is any value in the range of 10-200 μm. The thickness of the first green ceramic tape and the second green ceramic tape needs to ensure that the surface is flat, without bubbles or cracks, and the mechanical properties need to meet the subsequent processing requirements. The mechanical properties include flexibility.

[0134] Punching is performed on the first green ceramic tape to form a first hole and a second hole.

[0135] Punching is performed on the second green ceramic tape to form a third hole. The aperture of the first hole, the second hole, and the third hole can be any value in the range of 50-300 μm.

[0136] The conductive paste is filled in the first hole, the second hole, and the third hole, respectively, for interlayer electrical connection.

[0137] The conductive paste can be a metal paste. The metal paste includes silver paste, copper paste, etc. The metal paste needs to match the sintering shrinkage rate of the ceramic powder to avoid cracking of the power device.

[0138] The first hole, the second hole, and the third hole can be filled by screen printing or inkjet printing.

[0139] Drive circuit printing is performed on the first green ceramic tape to form a drive circuit layer.

[0140] Power circuit printing is performed on the second green ceramic tape to form a power circuit layer.

[0141] In one specific embodiment, the punching method is one of mechanical punching, laser punching, or photolithography punching.

[0142] The punch speed of mechanical punching can reach 100-500 times per minute, which is suitable for continuous production and is conducive to realizing low-cost mass production.

[0143] Laser punching has strong material adaptability. CO2 laser has high absorption rate for ceramics and glass, which is suitable for through-hole processing of LTCC green ceramic tape. Laser punching is a non-contact green punching process, without physical tool wear and cutting debris, and has good environmental protection.

[0144] Photolithography punching can realize ultra-precision machining with a hole diameter of 0.1-5 μm and a hole pitch of ±0.1 μm. Through mask replication, photolithography punching can ensure that the size error of each hole of multiple power devices is <±5%, with high process precision.

[0145] In one specific embodiment, the first carrier film includes a first sub-carrier film and a second sub-carrier film, and the first green ceramic tape includes a first sub-green ceramic tape and a second sub-green ceramic tape.

[0146] The steps of drilling holes in the first green porcelain strip to form the first and second holes include:

[0147] Drill holes in the first piece of raw porcelain to form the first hole;

[0148] A hole is drilled in the second sub-green ceramic belt to form a second sub-hole and a second hole; wherein, the first hole includes a connection between the first sub-hole and the second sub-hole, and the projection of the first sub-hole on the second sub-green ceramic belt coincides with the second sub-hole.

[0149] Forming the second sub-hole only in the second sub-green ceramic strip can reduce the manufacturing complexity of power devices.

[0150] Therefore, the low-temperature co-fired ceramic (LTCC) comprises a first driving circuit layer corresponding to the first green ceramic strip, a second driving circuit layer corresponding to the second green ceramic strip, and a power circuit layer corresponding to the second green ceramic strip. Each layer consists of ceramic and wiring circuitry. After the three layers are fabricated, they are laminated to form an LTCC board, which is then sintered onto the chip layer to form a power device. The chip layer includes an AMB board and a chip sintered on the AMB board.

[0151] In one specific embodiment, after the step of stacking the drive circuit layer and the power circuit layer to obtain a laminated structure, and before the step of sintering the laminated structure, the method further includes:

[0152] Place the laminated structure in air or an inert gas.

[0153] When the conductive paste is silver, the laminate can be co-fired in air. When the conductive paste is copper, the laminate can be co-fired in an inert gas such as nitrogen to avoid oxidation of the conductive paste.

[0154] The heating temperature of the laminated structure is increased at a preset rate of change until the temperature of the laminated structure is maintained within the range of 300℃-500℃.

[0155] The preset change rate can be 1-5℃ / min. Placing the laminated structure in a slowly heating environment can drive the organic binder in the laminated structure to be removed, thereby avoiding the rapid decomposition of the organic binder in the high-temperature environment of subsequent sintering, which would lead to cracking of the preform and improve the process reliability of the layered packaging method for power devices.

[0156] In one specific embodiment, the step of sintering a low-temperature co-fired ceramic plate and a chip layer to obtain a power device further includes:

[0157] Sintering low-temperature co-fired ceramic plates and chip layers yields a co-fired structure.

[0158] At least one of the cutting processing, the surface metallization processing and the patch welding processing is performed on the co-fired structure to obtain the power device.

[0159] The surface metallization processing includes gold plating or nickel plating on the surface of the co-fired structure.

[0160] In the description of the specification, the description referring to the terms "some embodiments", "other embodiments" and the like means that the particular feature, structure, material or characteristic being described is included in at least one embodiment or example of the application. The illustrative descriptions are not intended to limit the scope of the application, as the described embodiments are not the only embodiments that can be implemented.

[0161] The technical features of the above-described embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as falling within the scope of the present application.

[0162] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, however, it should not be understood as a limitation on the scope of the present application. It should be pointed out that, for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A layered packaging structure for a power device, characterized in that, include: The driving circuit layer, power circuit layer, and chip layer are stacked in sequence. The drive circuit layer has a first hole and a second hole, and the power circuit layer has a third hole, all of which are filled with conductive paste; the projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the projection of the third hole. The driving circuit layer is connected to the power circuit layer through the first aperture, the driving circuit layer is connected to the chip layer through the second aperture and the third aperture, and the power circuit layer is connected to the chip layer through the third aperture; the driving circuit layer is used to drive the chip layer. The drive circuit layer includes: a first drive circuit layer and a second drive circuit layer stacked sequentially. The first drive circuit layer is located further away from the power circuit layer than the second drive circuit layer. The first hole includes a first sub-hole on the first drive circuit layer and a second sub-hole on the second drive circuit layer, and the projection of the first sub-hole on the second drive circuit layer coincides with the second sub-hole; The first driving circuit layer is connected to the power circuit layer via the first sub-via and the second sub-via, and the second driving circuit layer is connected to the chip layer via the second aperture and the third aperture; both the first driving circuit layer and the second driving circuit layer are used to drive the chip layer. The first driving circuit layer includes: a first ceramic plate and a first driving circuit circuit integrated on the first ceramic plate; The signal line of the first drive circuit extends to the first sub-hole; The second drive circuit layer includes: a second ceramic plate and a second drive circuit circuit integrated on the second ceramic plate; The signal line of the second drive circuit extends to the second hole; The first drive circuit includes an independently configured first upper bridge circuit and a first lower bridge circuit, and the second drive circuit includes an independently configured second upper bridge circuit and a second lower bridge circuit. Wherein, the projection of the circuit region where the first upper bridge circuit is located on the second drive circuit coincides with the circuit region where the second upper bridge circuit is located, and the projection of the circuit region where the first lower bridge circuit is located on the second drive circuit coincides with the circuit region where the second lower bridge circuit is located; wherein, the distance between the first upper bridge circuit and the first lower bridge circuit is greater than or equal to the insulation distance under the preset voltage requirement. The signal line of the first upper bridge circuit extends to the first upper bridge hole in the first sub-hole, and the signal line of the first lower bridge circuit extends to the first lower bridge hole in the first sub-hole; the signal line of the second upper bridge circuit extends to the second upper bridge hole in the second hole, and the signal line of the second lower bridge circuit extends to the second lower bridge hole in the second hole.

2. The layered packaging structure of the power device according to claim 1, characterized in that, The power circuit layer includes: a third upper bridge circuit and a third lower bridge circuit that are independently configured, and a third ceramic plate that integrates the third upper bridge circuit and the third lower bridge circuit; The signal lines and power lines are routed perpendicularly; wherein, the signal lines include the signal lines of the first drive circuit and the signal lines of the second drive circuit, and the power lines include the power lines of the third upper bridge circuit and the power lines of the third lower bridge circuit; The signal line of the third upper bridge circuit extends to the third upper bridge hole in the third hole, and the signal line of the third lower bridge circuit extends to the third lower bridge hole in the third hole.

3. A layered packaging method for power devices, characterized in that, include: A drive circuit layer and a power circuit layer are provided; wherein the drive circuit layer has a first hole and a second hole, the power circuit layer has a third hole, and the first hole, the second hole and the third hole are all filled with conductive paste; The drive circuit layer and the power circuit layer are stacked to obtain a laminated structure; wherein the projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the third hole. The laminated structure is sintered in an environment with a temperature range of 600℃-900℃ to obtain a low-temperature co-fired ceramic plate; Prepare the chip layer and stack the low-temperature co-fired ceramic plate with the chip layer; The power device is obtained by sintering the low-temperature co-fired ceramic plate and the chip layer.

4. The layered packaging method for power devices according to claim 3, characterized in that, The fabrication steps of the drive circuit layer and the power circuit layer include: Prepare and formulate ceramic slurry based on ceramic powder and slurry; Prepare the first and second carrier membranes; The ceramic slurry is uniformly coated onto the first carrier film and the second carrier film using a casting machine to obtain the first green ceramic tape and the second green ceramic tape respectively. Drill holes in the first green ceramic strip to form the first hole and the second hole; Drill a hole in the second green ceramic strip to form the third hole; The first hole, the second hole, and the third hole are respectively filled with conductive paste; A drive circuit layer is formed by printing a drive circuit on the first green ceramic tape. Power circuits are printed on the second green ceramic tape to form a power circuit layer.

5. The layered packaging method for power devices according to claim 4, characterized in that, The drilling method is one of mechanical punching, laser drilling, or photolithography drilling.

6. The layered packaging method for power devices according to claim 4, characterized in that, The first carrier membrane includes a first sub-carrier membrane and a second sub-carrier membrane, and the first green ceramic tape includes a first sub-green ceramic tape and a second green ceramic tape; The step of drilling holes in the first green ceramic strip to form a first hole and a second hole includes: Drill a hole in the first sub-porcelain strip to form the first sub-hole; A hole is drilled in the second green ceramic strip to form a second sub-hole and a second hole; wherein, the first hole includes a connection between the first sub-hole and the second sub-hole, and the projection of the first sub-hole on the second green ceramic strip coincides with the second sub-hole.

7. The layered packaging method for power devices according to claim 3, characterized in that, After the step of stacking the drive circuit layer and the power circuit layer to obtain a laminated structure, and before the step of sintering the laminated structure, the method further includes: Place the laminated structure in air or an inert gas; The heating temperature of the laminated structure is increased at a preset rate of change until the temperature of the laminated structure is maintained within the temperature range of 300℃-500℃.

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