Analog input front-end circuit with constant impedance and high linearity
By introducing a feedforward replication capacitor and a level shifting capacitor into the analog input front-end circuit, the problem of insufficient linearity in high-precision A/D converters is solved, achieving higher linearity and lower power consumption, making it suitable for high-speed, high-precision A/D converters.
Patent Information
- Application Number
- CN202511051939.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-12-19
AI Technical Summary
Existing analog input front-end circuits suffer from nonlinear distortion in high-precision A/D converters, especially under high sampling rates and high resolutions. The linearity of traditional analog input front-end circuits is insufficient, resulting in high power consumption.
By employing a feedforward replication capacitor and a level shifting capacitor design, a feedforward replication capacitor is added between the source and gate of the NMOS follower. Combined with a switched capacitor circuit and a sampling capacitor, the current is kept constant, the voltage variation of the source follower is reduced, the linearity is improved, and the power consumption is reduced.
This invention achieves higher linearity in analog input front-end circuitry with lower bias current, improving linearity by 10dB and reducing power consumption by 70%. It is suitable for high-speed, high-precision A/D converters, especially for applications with sampling rates of hundreds of megahertz to gigahertz.
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Figure CN121173293A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a constant-impedance high-linearity analog input front-end circuit and belongs to the technical field of high-speed high-precision A / D converters. BACKGROUND
[0002] Analog-to-digital converter circuits capable of converting analog signals into digital signals are key components in modern electronic systems. In recent years, with the rapid development of converter circuits, the requirements for sampling rate and resolution are also increasing. High-speed high-precision A / D converter circuits with sampling rates above gigahertz and resolutions above 12 bits are widely used in radar, wireless communication and other fields. The analog input front-end circuit is one of the key modules of the high-speed high-precision A / D converter circuit, and its linearity and bandwidth restrict the improvement of sampling accuracy and speed. The analog input front-end circuit is located at the front end of the input signal path and is directly connected to the signal to be sampled. It can not only realize the isolation of the signal source and the sampling capacitor, but also provide very small output impedance, so that the ADC is easier to be driven. The traditional analog input front-end circuit is a simple source follower, and the non-linear distortion is mainly caused by the non-linearity of the transconductance and the load impedance of the transistor. The input signal is changing all the time, and the change of the source voltage of the NMOS tube will cause the change of the threshold voltage, introducing serious non-linear distortion. As the conversion accuracy exceeds 12 bits and the sampling rate enters the gigahertz range, the linearity requirement of the A / D converter for the analog input front-end circuit is higher and higher, and it is necessary to reduce the non-linearity of the analog input front-end circuit. SUMMARY
[0003] The technical problem solved by the application is to overcome the shortcomings of the prior art and provide a constant-impedance high-linearity analog input front-end circuit using feedforward replica capacitors, which realizes better linearity under smaller bias current.
[0004] The technical solution of the application is as follows:
[0005] The application discloses a constant-impedance high-linearity analog input front-end circuit, comprising an NMOS follower M1, an NMOS follower M2 and a switched capacitor circuit.
[0006] The two input ends of the switched capacitor circuit are connected with input voltages Vb1 and Vb2, the first output end is connected with the gate of the NMOS follower M1, and the second output end is connected with the gate of the NMOS follower M2.
[0007] The drain of the NMOS follower M1 is connected with the source of the NMOS follower M2, and the drain of the NMOS follower M2 is connected with a power supply.
[0008] The input signal V INThe input signal V OUT is inputted from the gate of the NMOS follower M1 and the output signal V OUT is outputted from the source of the NMOS follower M1. IN
[0009] Further, in the above circuit, a switch Φ_btst, a sampling capacitor C S and a switch Φ_1a are further included; wherein the output voltage V OUT is connected with the ground through the switch Φ_btst, the sampling capacitor C S and the switch Φ_1a.
[0010] Further, in the above circuit, an NMOS follower M3 and a feed-forward replica capacitor C1 are further included; wherein the source of the NMOS follower M1 is connected with the drain of the NMOS follower M3; the feed-forward replica capacitor C1 is connected with the source of the NMOS follower M3 and the gate of the NMOS follower M1; the source of the NMOS follower M3 is connected with the drain of the NMOS follower M4, and the source of the NMOS follower M4 is connected with the ground.
[0011] Further, in the above circuit, the gate of the NMOS follower M3 is connected with an input voltage Vb3, and the gate of the NMOS follower M4 is connected with an input voltage Vb4.
[0012] Further, in the above circuit, the switched capacitor circuit includes a switch Φ1, a switch Φ2, a switch Φ3, a switch Φ4 and a capacitor C3; wherein the input end of the switch Φ1 is connected with an input voltage Vb1, the output end of the switch Φ1 is connected with the input end of the switch Φ2 and the input end of the capacitor C3; the input end of the switch Φ3 is connected with an input voltage Vb2, and the output end of the switch Φ3 is connected with the input end of the switch Φ4 and the output end of the capacitor C3.
[0013] Further, in the above circuit, a level shift capacitor C2 is further included; wherein the gate of the NMOS follower M2 is connected with the gate of the NMOS follower M1 through the level shift capacitor C2, and the two ends of the level shift capacitor C2 are respectively connected with the output end of the switch Φ2 and the output end of the switch Φ4 in the switched capacitor circuit.
[0014] Further, in the above circuit, the source of the NMOS follower M1 is connected with the drain of the NMOS follower M3 through an output terminal Vout.
[0015] Further, in the above circuit, the feed-forward replica capacitor C1 has the same value as the sampling capacitor Cs.
[0016] Further, in the above circuit, the drain of the NMOS follower M1 adopts a bootstrapping structure, and the source of the NMOS follower M1 adopts a cascode structure.
[0017] The present application has the following advantages compared with the prior art:
[0018] (1) The present application fixes the current flowing through the source follower M1 as a constant by adding a feed-forward replica capacitor C1 between the source of the NMOS follower M3 of the NMOS source follower and the gate of M1, greatly improves the linearity of the analog input front-end circuit, and isolates the input of the A / D converter from the nonlinear impedance in the later stage. Therefore, the analog input front-end circuit can achieve better linearity under smaller bias current, greatly reducing power consumption.
[0019] (2) The present application solves the problem of the change of the source-drain voltage of the source follower NMOS follower M1 by using the level shift capacitor C2 and the common-gate NMOS follower M2 to raise the drain voltage. This new technology makes the drain voltage follow the input and the source voltage, thus reducing the change of the V ds of the source follower, and reducing the nonlinearity caused by R ds .
[0020] (3) The present application can be applied to high-speed high-precision A / D converters with a sampling rate of hundreds of megahertz to gigahertz, providing technical support for the development of higher-performance high-speed high-precision A / D converters with higher conversion bit number and sampling rate.
[0021] (4) The feed-forward replica capacitor C1 of the present application has the same value as the sampling capacitor Cs, so that the current flowing through the NMOS follower M1 is constant, eliminating the nonlinearity distortion caused by current change, improving the linearity of the input buffer, and making the input impedance of the buffer more stable, reducing the distortion at the input end of the buffer.
[0022] (5) The constant resistance analog input front-end circuit of the present application not only has smaller output impedance, reducing distortion, but also isolates the input of the A / D converter from the nonlinear impedance in the later stage. Therefore, the source follower can achieve better linearity under smaller bias current, greatly reducing power consumption.
[0023] (6) The present application adopts a constant resistance high linearity analog input front-end circuit with feed-forward replica capacitor to solve the problem of nonlinearity distortion of the output signal of the existing analog input front-end circuit, achieving better linearity under smaller bias current, greatly reducing power consumption, effectively suppressing the nonlinearity distortion of the analog input front-end circuit, and meeting the requirements of high-speed high-precision AD converters for front-end input signals. The linearity of the analog input front-end circuit of the present application reaches more than 92dB, which is about 10dB higher than that of the traditional analog input front-end circuit, and the power consumption is reduced by 70%. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1This is a schematic diagram of a constant impedance, high linearity analog input front-end circuit according to the present invention.
[0025] Figure 2 This is a performance simulation diagram of an analog input front-end circuit with constant impedance and high linearity according to the present invention. Detailed Implementation
[0026] The present invention will be described in detail below with reference to the accompanying drawings and specific examples.
[0027] Example
[0028] like Figure 1 As shown, this invention discloses a constant impedance, high linearity analog input front-end circuit, including an NMOS follower M1, an NMOS follower M2, and a switched capacitor circuit; wherein,
[0029] The two input terminals of the switched capacitor circuit are connected to the input voltages Vb1 and Vb2, the first output terminal is connected to the gate of NMOS follower M1, and the second output terminal is connected to the gate of NMOS follower M2.
[0030] The drain of NMOS follower M1 is connected to the source of NMOS follower M2, and the drain of NMOS follower M2 is connected to the power supply.
[0031] Input signal V IN The source-to-output signal V is obtained from the gate input of the NMOS follower M1. OUT Output signal V OUT Follow the input signal V IN ;
[0032] Preferably, it also includes a switch Φ_btst and a sampling capacitor C. S and switch Φ_1a; where the output voltage V OUT Through switch Φ_btst, sampling capacitor C S Connect the switch Φ_1a to ground.
[0033] Preferably, it further includes an NMOS follower M3 and a feedforward replication capacitor C1; wherein, the source of the NMOS follower M1 is connected to the drain of the NMOS follower M3; the feedforward replication capacitor C1 is connected to the source of the NMOS follower M3 and the gate of the NMOS follower M1; the source of the NMOS follower M3 is connected to the drain of the NMOS follower M4, and the source of the NMOS follower M4 is grounded.
[0034] Preferably, the gate of NMOS follower M3 is connected to the input voltage Vb3, and the gate of NMOS follower M4 is connected to the input voltage Vb4.
[0035] Preferably, the switched capacitor circuit comprises switches Φ1, Φ2, Φ3, Φ4, and a capacitor C3; wherein the input terminal of the switch Φ1 is connected to the input voltage Vb1, and the output terminal of the switch Φ1 is connected to the input terminal of the switch Φ2 and the input terminal of the capacitor C3; the input terminal of the switch Φ3 is connected to the input voltage Vb2, and the output terminal of the switch Φ3 is connected to the input terminal of the switch Φ4 and the output terminal of the capacitor C3.
[0036] Preferably, the circuit further comprises a level shift capacitor C2, wherein the level shift capacitor C2 is connected between the gate of the NMOS follower M2 and the gate of the NMOS follower M1, and the two terminals of the level shift capacitor C2 are respectively connected to the output terminal of the switch Φ2 and the output terminal of the switch Φ4 in the switched capacitor circuit.
[0037] Preferably, the source of the NMOS follower M1 is connected to the drain of the NMOS follower M3.
[0038] Preferably, the feed-forward replica capacitor C1 has the same value as the sampling capacitor Cs.
[0039] Preferably, the drain of the NMOS follower M1 adopts a bootstrapping structure, and the source of the NMOS follower M1 adopts a cascode structure.
[0040] Embodiment
[0041] The embodiment discloses an analog input front-end circuit with constant impedance and high linearity by using a feed-forward replica capacitor, comprising an NMOS source follower, a feed-forward replica capacitor, a level shift capacitor, a switched capacitor circuit, and a sampling capacitor.
[0042] The drain of the NMOS source follower M1 adopts a bootstrapping structure, and comprises an NMOS follower M2, a level shift capacitor C2, and a switched capacitor circuit, wherein the level shift capacitor C2 is charged by the switched capacitor circuit. The level shift capacitor C2 and the NMOS follower M2 raise the drain voltage, so that the drain voltage follows the input and the source voltage, thereby solving the problem of the change of the source-drain voltage of the NMOS device in the analog input front-end circuit, keeping the V DS unchanged, that is, r ds remains constant, thereby reducing the nonlinearity caused by R ds , reducing the channel modulation effect, and improving the linearity; the source adopts a cascode structure, increasing the impedance, and further improving the linearity.
[0043] The embodiment adds a feed-forward replica capacitor C1 between the source level of NMOS follower M3 and the gate of M1, and the feed-forward replica capacitor C1 has the same value as the sampling capacitor Cs. Since the transconductance of the common-gate tube M3 is very high, the source end of M3 is equivalent to "virtual", thus the current flowing through the capacitor C1 following the change of the analog input signal is almost the same as the current flowing through the sampling capacitor Cs, and the high output impedance of M4 makes most of the current of the capacitor C1 flow through the transistor M2 to the output end Vout of the source level follower, so that the current flowing through the source follower M1 is constant, and the linearity of the input buffer is improved. It can be seen that the high linearity input buffer can eliminate the nonlinear distortion caused by current change, and also makes the input impedance of the buffer more stable, reducing the distortion of the input end of the buffer. The constant impedance buffer not only has smaller output impedance, reduces distortion, but also isolates the input of the A / D converter from the nonlinear impedance in the later stage. Therefore, the source follower can achieve better linearity under smaller bias current, greatly reducing power consumption.
[0044] The output resistance of the NMOS source level follower is low, and the linearity is poor, which reduces the DC and high frequency nonlinearities. If the change of the source-drain voltage of M1 of the source level follower is reduced, the nonlinearities can be greatly improved. The present application solves this problem by raising the drain voltage through the level shift capacitor C2 and the common-gate NMOS follower M2. This new technology makes the drain voltage follow the input and the source voltage, thus reducing the change of V ds of the source level follower, and reducing the nonlinearities caused by R ds The level shift capacitor C2 is charged by a switched capacitor circuit.
[0045] The embodiment proposes a high linearity wide bandwidth low noise analog input front-end circuit for high speed high precision A / D converters with resolution of 10-14 bits and sampling rate of hundreds of megahertz to gigahertz, which can make the linearity of the analog input front-end circuit reach more than 92dB, about 10dB higher than the traditional analog input front-end circuit, and reduce the power consumption by 70%.
[0046] The embodiment uses cascode structure for the drain and source of the analog input front-end circuit M1, and adds a feed-forward replica capacitor C1 between the source level of NMOS follower M3 and the gate of M1, so that the current flowing through the analog input front-end circuit M1 is constant, ensuring that I BThe constant impedance improves the linearity, and the input impedance of the analog input front-end circuit is more stable, and the distortion of the buffer input end is reduced. The analog input front-end circuit with constant impedance and high linearity has smaller output impedance and distortion, and separates the input of the A / D converter from the non-linear impedance in the later stage. Therefore, the analog input front-end circuit can achieve better linearity under smaller bias current, and greatly reduces the power consumption.
[0047] The analog input front-end circuit in the embodiment is located at the front end of the input signal path and directly connected with the signal to be sampled, and can realize the isolation of the signal source and the sampling capacitor and provide very small output impedance, so that the ADC is easier to be driven, and is a key module of high-speed and high-precision A / D converter. The analog input front-end circuit can be applied to high-speed and high-precision A / D converter with a sampling rate of hundreds of megahertz to gigahertz and a resolution of 12 bits or more, and the dynamic performance of the analog input front-end circuit is shown in the table. Figure 2 As shown in the table, the linearity reaches more than 92 dB, and the linearity is improved by about 10 dB and the power consumption is reduced by 70% compared with the traditional analog input front-end circuit.
[0048] Although the content of the present application has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present application. After reading the above content, various modifications and alternatives of the present application will be obvious to those skilled in the art. Therefore, the protection scope of the present application should be defined by the appended claims.
[0049] The content not described in detail in the specification of the present application belongs to the known technology of the skilled in the art.
Claims
1. A constant impedance high linearity analog input front end circuit, characterized by: The circuit comprises an NMOS follower M1, an NMOS follower M2 and a switched capacitor circuit; wherein, The two input terminals of the switched capacitor circuit are connected with input voltages Vb1 and Vb2, the first output terminal is connected with the gate of the NMOS follower M1, and the second output terminal is connected with the gate of the NMOS follower M2. The drain of the NMOS follower M1 is connected with the source of the NMOS follower M2, and the drain of the NMOS follower M2 is connected with a power supply. Input signal V IN Output signal V is input from the gate of NMOS follower Ml, source- level output OUT , Output signal V OUT Follows input signal V IN。 2. The constant impedance high linearity analog input front-end circuit of claim 1, wherein, Also included are switches Φ_btst, sampling capacitor C S and switch Φ_1a; wherein the output voltage V OUT through switch Φ_btst, sampling capacitor C S and switch Φ_1a is connected to ground.
3. The constant impedance high linearity analog input front end circuit of claim 2, wherein, The circuit further comprises an NMOS follower M3 and a feed-forward replica capacitor C1; wherein, the source of the NMOS follower M1 is connected with the drain of the NMOS follower M3, the feed-forward replica capacitor C1 is connected with the source of the NMOS follower M3 and the gate of the NMOS follower M1, the source of the NMOS follower M3 is connected with the drain of the NMOS follower M4, and the source of the NMOS follower M4 is connected with a ground.
4. The analog input front-end circuit of claim 3, wherein, The gate of the NMOS follower M3 is connected with an input voltage Vb3, and the gate of the NMOS follower M4 is connected with an input voltage Vb4.
5. The constant impedance high linearity analog input front end circuit of claim 1, wherein, The switched capacitor circuit comprises a switch Φ1, a switch Φ2, a switch Φ3, a switch Φ4 and a capacitor C3; wherein, the input terminal of the switch Φ1 is connected with an input voltage Vb1, the output terminal of the switch Φ1 is connected with the input terminal of the switch Φ2 and the input terminal of the capacitor C3, the input terminal of the switch Φ3 is connected with an input voltage Vb2, and the output terminal of the switch Φ3 is connected with the input terminal of the switch Φ4 and the output terminal of the capacitor C3.
6. The constant impedance high linearity analog input front end circuit of claim 5, wherein, The circuit further comprises a level shift capacitor C2, wherein, the gate of the NMOS follower M2 is connected with the gate of the NMOS follower M1 via the level shift capacitor C2, and the two terminals of the level shift capacitor C2 are respectively connected with the output terminal of the switch Φ2 and the output terminal of the switch Φ4 in the switched capacitor circuit.
7. The constant impedance high linearity analog input front-end circuit of claim 1, wherein: The source of the NMOS follower M1 is connected with the drain of the NMOS follower M3 via an output terminal Vout.
8. The constant impedance high linearity analog input front end circuit of claim 3, wherein: The feed-forward replica capacitor C1 has the same value as a sampling capacitor Cs.
9. The constant impedance high linearity analog input front end circuit of claim 3, wherein: The drain of the NMOS follower M1 adopts a bootstrapping structure, and the source of the NMOS follower M1 adopts a cascode structure.