Memory device including isolation transistor

Abstract

The invention provides a memory device, which may include: an active region disposed on a substrate; a first unit cell and a second unit cell disposed in the active region; and an isolation transistor disposed in the active region between the first unit cell and the second unit cell, the isolation transistor maintaining an off state.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0079323, filed with the Korean Intellectual Property Office on June 19, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a memory device including an isolation transistor. Background Technology

[0004] Unlike typical random access memory (RAM) devices, non-volatile memory devices retain stored data even when power is off. Read-only memory (ROM) devices, as an example of non-volatile memory capable of retaining data, can be used in various electronic devices. ROM devices can have the characteristics of non-volatile memory, so the stored information is not deleted even when power is off.

[0005] ROM devices can be categorized based on whether users can input data. Depending on the application, programmable ROM devices can be sold in their initial state, without data programmed during manufacturing, allowing users to program the necessary information directly on-site. Mask ROM devices can be sold with data pre-programmed according to user orders during manufacturing. Depending on the input method, one-time programmable ROMs (OTPROMs), multiple-time programmable ROMs (MTPROMs), and PROM devices can be used. There are attempts to implement PROM devices as devices that store data as charge, such as electrically programmable ROMs (EPROMs) or electrically erasable PROMs (EEPROMs). Summary of the Invention

[0006] Embodiments of this disclosure can provide a memory device capable of preventing degradation of device characteristics due to process defects.

[0007] Embodiments of this disclosure may provide a memory device comprising: an active region disposed on a substrate; a first cell unit and a second cell unit disposed in the active region; and an isolation transistor, kept in an off state and disposed in the active region between the first cell unit and the second cell unit.

[0008] Embodiments of this disclosure may provide a memory device comprising: a first unit cell including a first transistor and a second transistor adjacent to the first transistor; a second unit cell including a third transistor and a fourth transistor adjacent to the third transistor; and an isolation transistor disposed between the first unit cell and the second unit cell, connected to the first unit cell and the second unit cell, and kept in an off state.

[0009] Embodiments of this disclosure may provide a memory device comprising: a memory cell structure including a memory cell array; and a peripheral structure disposed below the memory cell structure, including peripheral circuitry and a ROM device. The peripheral circuitry is used to transmit voltages and signals required for the operation of the memory cell array, and the ROM device is used to store code data. The ROM device includes: an active region disposed on a substrate; a first unit cell and a second unit cell disposed in the active region; and an isolation transistor disposed between the first unit cell and the second unit cell in the active region and kept in an off state.

[0010] According to embodiments of this disclosure, device characteristic degradation of memory devices due to process defects can be prevented. Attached Figure Description

[0011] Figure 1 This is a block diagram of a ROM device included in a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 Show Figure 1 A schematic diagram including the unit cell.

[0013] Figure 3 Show Figure 1 A planar structure that includes unit cells.

[0014] Figure 4 Show along Figure 3 The cross section intercepted by line I-I'.

[0015] Figure 5 An example of a memory device according to an embodiment of the present disclosure is shown.

[0016] Figure 6 The planar structure of the comparison memory device is shown.

[0017] Figure 7 Show along Figure 6 The cross section intercepted by line II-II'.

[0018] Figure 8 This is a block diagram of a memory system including a memory device according to embodiments of the present disclosure. Detailed Implementation

[0019] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] In the accompanying drawings, two directions parallel to the upper surface of the substrate can be defined as the first direction (FD) and the second direction (SD), respectively, and a direction projecting perpendicularly from the upper surface of the substrate can be defined as the third direction (VD). The first direction (FD) and the second direction (SD) can be substantially perpendicular to each other. The third direction (VD) can be perpendicular to the first direction (FD) and the second direction (SD). In the following description, "perpendicular" or "perpendicular direction" will be used with substantially the same meaning as the third direction (VD). In the figures, the direction indicated by the arrow and its opposite direction can represent the same direction.

[0021] Figure 1 This is a block diagram of a ROM device included in a memory device according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The ROM device 100 may include control logic 110, word line selection circuit 120, bit line selection circuit 130, and multiple unit cells CU.

[0023] Control logic 110 can provide a row address to word line selection circuit 120 and a column address to bit line selection circuit 130. Word line selection circuit 120 can select one or more word lines WL based on the row address transmitted from control logic 110. Bit line selection circuit 130 can select one or more bit lines BL based on the column address transmitted from control logic 110. A unit cell CU can be selected using the selected word line WL and bit line BL.

[0024] Each of the multiple unit cells (CUs) can be located in a region comprising the intersection of a pair of word lines (WL) and a bit line (BL). Here, a unit cell (CU) can refer to a pair of cells, i.e., two cells. Each cell can include a transistor, and logic values ​​programmed during the manufacture of the ROM device 100 can be stored in each cell. A cell can store 1 bit of information (0 or 1), or it can store 2 or more bits of information. When a cell stores 1 bit of information, a unit cell (CU) can store 2 bits of information.

[0025] Although not shown, the ROM device 100 may further include read circuitry for reading logic values ​​stored in each unit cell CU. The read circuitry can read the logic value of a selected unit cell CU based on the current flowing in the bit line BL associated with that selected unit cell CU.

[0026] Figure 2 Show Figure 1 A schematic diagram including the unit cell.

[0027] Figure 2 Show Figure 1Part 10, in which the unit unit CU includes a first unit unit CU1 and a second unit unit CU2. The first unit unit CU1 may be located in the region where the first word line WL1 and the second word line WL2 intersect with the first word line BL1. The second unit unit CU2 may be located in the region where the third word line WL3 and the fourth word line WL4 intersect with the first word line BL1.

[0028] The ROM device 100 may include a first ground line GND1 and a second ground line GND2 disposed parallel to the word line WL.

[0029] The first ground line GND1 can be configured to overlap with the area where the first unit cell CU1 is located. In an embodiment, a first ground line GND1 can be located between the first word line WL1 and the second word line WL2.

[0030] The second ground wire GND2 can be arranged to overlap with the area where the second unit CU2 is located. In an embodiment, a second ground wire GND2 can be located between the third word line WL3 and the fourth word line WL4.

[0031] The number and arrangement of the first ground wire GND1 and the second ground wire GND2 are not limited to... Figure 2 As shown in the diagram, the first ground wire GND1 can be located in a region that does not overlap with the first unit cell CU1, and the second ground wire GND2 can be located in a region that does not overlap with the second unit cell CU2. Additionally, a pair of first ground wires GND1 and a pair of second ground wires GND2 can be provided, corresponding to the first unit cell CU1 and the second unit cell CU2 respectively. Each of the first ground wires GND1 and the second ground wires GND2 provides a fixed ground voltage.

[0032] The first unit CU1 may include a first transistor TR1 and a second transistor TR2. In an embodiment, the first transistor TR1 and the second transistor TR2 may be NMOS transistors. The first transistor TR1 may include a first word line WL1, and the second transistor TR2 may include a second word line WL2.

[0033] The second unit CU2 may include a third transistor TR3 and a fourth transistor TR4. In an embodiment, the third transistor TR3 and the fourth transistor TR4 may be NMOS transistors. The third transistor TR3 may include a third word line WL3, and the fourth transistor TR4 may include a fourth word line WL4.

[0034] The first line BL1 can be connected to the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4. The first transistor TR1 and the second transistor TR2 can share a drain (as described later) and can be connected to the first line BL1 through this shared drain. The third transistor TR3 and the fourth transistor TR4 can share a drain (as described later) and can be connected to the first line BL1 through this shared drain. That is, both the first unit cell CU1 and the second unit cell CU2 can be connected to the first line BL1.

[0035] The source of the first transistor TR1 and the source of the second transistor TR2 can be connected to the first ground line GND1, or they can be floating and not connected to the first ground line GND1. Similarly, the source of the third transistor TR3 and the source of the fourth transistor TR4 can be connected to the second ground line GND2, or they can be floating and not connected to the second ground line GND2.

[0036] The logic value stored in the first unit cell CU1 can vary depending on whether the sources of the first transistor TR1 and the second transistor TR2 are connected to the first ground line GND1. Similarly, the logic value stored in the second unit cell CU2 can vary depending on whether the sources of the third transistor TR3 and the fourth transistor TR4 are connected to the second ground line GND2. For ease of explanation, in the following description, it will be assumed that one cell stores one bit of information and one unit cell CU stores two bits of information.

[0037] In this embodiment, the source of the first transistor TR1 can be connected to the first ground line GND1, and the source of the second transistor TR2 can be unconnected to the first ground line GND1. When the source of the first transistor TR1 is connected to the first ground line GND1, a read operation performed on the first transistor TR1 can read the logic value "1". Conversely, if the source of the second transistor TR2 is not connected to the first ground line GND1 and the source of the second transistor TR2 is in a floating state, a read operation performed on the second transistor TR2 can read the logic value "0". That is, in this case, the information "10" can be stored in the first unit cell CU1.

[0038] Similarly, in this embodiment, the source of the third transistor TR3 can be connected to the second ground GND2, and the source of the fourth transistor TR4 can also be connected to the second ground GND2. If the source of the third transistor TR3 is connected to the second ground GND2, then when a read operation is performed on the third transistor TR3, the logic value "1" can be read. Furthermore, if the source of the fourth transistor TR4 is connected to the second ground GND2, then when a read operation is performed on the fourth transistor TR4, the logic value "1" can be read. That is, in this case, the information "11" can be stored in the second unit CU2.

[0039] exist Figure 2 In this embodiment, the first unit CU1 can store the information of "10" and the second unit CU2 can store the information of "11". However, the embodiment is not necessarily limited to this, and each of the first unit CU1 and the second unit CU2 can store the information of "00", "10", "01" or "11".

[0040] For example, the sources of the first transistor TR1 and the second transistor TR2 may not be connected to the first ground line GND1. If the source of the first transistor TR1 is not connected to the first ground line GND1, the source of the first transistor TR1 can be in a floating state, so when a read operation is performed on the first transistor TR1, the logic value "0" can be read. Similarly, if the source of the second transistor TR2 is not connected to the first ground line GND1, the source of the second transistor TR2 can be in a floating state, so when a read operation is performed on the second transistor TR2, the logic value "0" can be read. That is, in this case, the information "00" can be stored in the first unit cell CU1.

[0041] Optionally, the source of the first transistor TR1 may not be connected to the first ground line GND1, and the source of the second transistor TR2 may be connected to the first ground line GND1. If the source of the first transistor TR1 is not connected to the first ground line GND1 and the source of the first transistor TR1 is in a floating state, then when performing a read operation on the first transistor TR1, the logic value "0" can be read. Conversely, if the source of the second transistor TR2 is connected to the first ground line GND1, then when performing a read operation on the second transistor TR2, the logic value "1" can be read. That is, in this case, the information of "01" can be stored in the first unit cell CU1.

[0042] Reference Figure 2 The ROM device 100 may further include a gate line Vcc and an isolation transistor TR_ISO. The isolation transistor TR_ISO may include the gate line Vcc.

[0043] The gate line Vcc can be arranged parallel to the word line WL. In an embodiment, the gate line Vcc can be located between the first unit cell CU1 and the second unit cell CU2. For example, as... Figure 2 As shown, the gate line Vcc can be located between the second word line WL2 and the third word line WL3. Alternatively, although not shown, the gate line Vcc can also be located between the second unit cell CU2 and another unit cell, which, viewed from the perspective of the second unit cell CU2, is adjacent to the second unit cell CU2 in a different direction relative to the first unit cell CU1.

[0044] An isolation transistor TR_ISO can be located between the second transistor TR2 of the first unit cell CU1 and the third transistor TR3 of the second unit cell CU2. In an embodiment, the source of the isolation transistor TR_ISO can be connected to the second transistor TR2, and the source of the isolation transistor TR_ISO and the source of the second transistor TR2 can be shared. The drain of the isolation transistor TR_ISO can be connected to the third transistor TR3, and the drain of the isolation transistor TR_ISO and the source of the third transistor TR3 can be shared.

[0045] Optionally, the drain of the isolation transistor TR_ISO and the source of the second transistor TR2 can be shared, and the source of the isolation transistor TR_ISO and the source of the third transistor TR3 can be shared.

[0046] Regardless of the operation of the second transistor TR2 and the third transistor TR3, the isolation transistor TR_ISO remains off. That is, a voltage can be supplied to the gate line Vcc to turn off the isolation transistor TR_ISO. In this embodiment, the isolation transistor TR_ISO can be an NMOS transistor. If the isolation transistor TR_ISO is an NMOS transistor, a ground voltage can be supplied to the gate line Vcc.

[0047] Since the isolation transistor TR_ISO remains off regardless of the operation of the second transistor TR2 and the third transistor TR3, no current flows through the channel of the isolation transistor TR_ISO. Therefore, the second transistor TR2 and the third transistor TR3 can be electrically disconnected from each other.

[0048] Since the isolation transistor TR_ISO remains off, the source of the second transistor TR2 can be in a floating state if its source is not connected to the first ground line GND1. Similarly, the source of the third transistor TR3 can be in a floating state if its source is not connected to the second ground line GND2.

[0049] Furthermore, since the isolation transistor TR_ISO remains off, the source of the second transistor TR2 can be grounded even if its source is connected to the first ground line GND1. Similarly, the source of the third transistor TR3 can be grounded even if its source is connected to the second ground line GND2.

[0050] Figure 3 Show Figure 1 A planar structure that includes unit cells. Figure 4 Show along Figure 3 The cross section intercepted by line I-I'.

[0051] Reference Figure 3 and Figure 4 The ROM device 100 may include a substrate 400, an active region 300, a first unit cell CU1, a second unit cell CU2, and an isolation transistor TR_ISO.

[0052] Substrate 400 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 400 may include a group III-V semiconductor substrate, such as a compound semiconductor substrate like GaAs. Substrate 400 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof. In an embodiment, substrate 400 may be silicon doped with a group III element.

[0053] An active region 300 may be disposed in a substrate 400. A first unit cell CU1, a second unit cell CU2, and an isolation transistor TR_ISO may be disposed in the active region 300 of the substrate 400. The active region 300 may include: a first portion 301, in which the first unit cell CU1 is disposed; a second portion 302, in which the second unit cell CU2 is disposed; and a third portion 303, in which the isolation transistor TR_ISO is disposed. In an embodiment, the upper surface of the third portion 303 of the active region 300 may form the same plane as the upper surfaces of the first portion 301 and the second portion 302 of the active region 300.

[0054] Multiple source and drain regions 411, 412, 413, 414, 415, and 416 may be disposed in the active region 300. In an embodiment, the multiple source and drain regions 411, 412, 413, 414, 415, and 416 may comprise single-crystal silicon with N-type impurities. N-type impurities may comprise P, As, or combinations thereof.

[0055] The channel regions of the first transistor TR1, the second transistor TR2, the isolation transistor TR_ISO, the third transistor TR3, and the fourth transistor TR4 can be formed between multiple source and drain regions 411, 412, 413, 414, 415, and 416, respectively. For example, the channel region of the first transistor TR1 can be formed between the first source region 411 and the first drain region 412.

[0056] The gate insulating layer 420 may be disposed in a region that vertically (VD) overlaps with the channel regions of the first transistor TR1, the second transistor TR2, the isolation transistor TR_ISO, the third transistor TR3, and the fourth transistor TR4 in the active region 300 of the substrate 400. The gate insulating layer 420 may comprise silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof.

[0057] The first word line WL1, the second word line WL2, the gate line Vcc, the third word line WL3, and the fourth word line WL4 can be disposed on the gate insulating layer 420. In an embodiment, the gate line Vcc can be disposed in the same layer as the first word line WL1, the second word line WL2, the third word line WL3, and the fourth word line WL4. Each of the multiple word lines WL1, WL2, WL3, and WL4 can include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. In an embodiment, the gate line Vcc can include the same material as the material forming the multiple word lines WL1, WL2, WL3, and WL4.

[0058] like Figure 3 As shown, the first word line WL1, the second word line WL2, the gate line Vcc, the third word line WL3, and the fourth word line WL4 can extend across the active region 300 along the second direction (SD). Each of the first word line WL1, the second word line WL2, the gate line Vcc, the third word line WL3, and the fourth word line WL4 can not only vertically overlap with the first unit cell CU1 and the second unit cell CU2 in the vertical direction (VD), but also vertically overlap with other unit cells disposed in the region extending along the second direction (SD).

[0059] The transistors included in the first unit cell CU1 can share a drain with each other through the first drain region 412. That is, the first drain region 412 can correspond to the drain regions of the first transistor TR1 and the second transistor TR2.

[0060] The transistors included in the second unit CU2 share a common drain through the second drain region 415. That is, the second drain region 415 can correspond to the drain regions of the third transistor TR3 and the fourth transistor TR4.

[0061] The isolation transistor TR_ISO can share a source or drain with the second transistor TR2 through the second source region 413, and can also share a source or drain with the third transistor TR3 through the third source region 414. That is, the second source region 413 can correspond to the source region of the second transistor TR2, and can also correspond to the source or drain region of the isolation transistor TR_ISO. Similarly, the third source region 414 can correspond to the source region of the third transistor TR3, and can also correspond to the source or drain region of the isolation transistor TR_ISO.

[0062] Although not shown, the first ground line GND1 and the second ground line GND2 may be further provided on the first word line WL1, the second word line WL2, the gate line Vcc, the third word line WL3 and the fourth word line WL4.

[0063] Similar to the first word line WL1, the second word line WL2, the gate line Vcc, the third word line WL3, and the fourth word line WL4, the first ground line GND1 and the second ground line GND2 can extend across the active region 300 along the second direction (SD). Each of the first ground line GND1 and the second ground line GND2 can overlap not only with the first unit cell CU1 and the second unit cell CU2 in the vertical direction (VD), but also with other unit cells arranged in the region extending along the second direction (SD).

[0064] The first ground line GND1 and the second ground line GND2 can be electrically connected to the first transistor TR1, the second transistor TR2, the third transistor TR3, or the fourth transistor TR4 through the first source region 411, the second source region 413, the third source region 414, or the fourth source region 416.

[0065] Although not shown, the ROM device 100 may further include conductive contacts for connecting a first ground line GND1 and a second ground line GND2 to at least one of a plurality of source regions 411, 413, 414 and 416.

[0066] Conductive contacts can be set at various positions within a unit cell based on the logic values ​​stored in the unit cell.

[0067] For example, if the first unit cell CU1 stores the information "10", then the source of the first transistor TR1 is required to be connected to the first ground line GND1, and the source of the second transistor TR2 is required not to be connected to the first ground line GND1. Therefore, the conductive contact can be connected to the first source region 411, and can be connected between the first source region 411 and the first ground line GND1. Alternatively, the conductive contact may not be provided between the second source region 413 and the first ground line GND1.

[0068] Figure 5An example of a memory device according to an embodiment of the present disclosure is shown.

[0069] Reference Figure 5 The memory 500 may include a peripheral structure or outer perimeter structure (P) and a memory cell structure (C).

[0070] The memory cell structure (C) may include a memory cell array 520 in which multiple memory cells are arranged. In the memory cell array 520, the memory cells may be arranged along a first direction (FD) or a second direction (SD), i.e., in a two-dimensional manner. Alternatively, in another embodiment, the memory cells may be arranged along a vertical direction (VD), i.e., in a three-dimensional manner.

[0071] In one embodiment, the peripheral structure (P) may include peripheral circuitry 510 and ROM device 100. Alternatively, in another embodiment, ROM device 100 may exist outside the memory 500. Peripheral circuitry 510 may transmit various signals and voltages for the operation of the memory cells to the memory cell array 520. ROM device 100 may store code data used by the program code required for the operation of the controller. Code data may refer to one or more bits of information stored in the aforementioned unit cells.

[0072] If the memory cells are arranged in a vertical direction (VD), the memory cell structure (C) and the peripheral structure (P) can be vertically built on a single wafer. The memory cell structure (C) may include a substrate, various semiconductor devices formed on the substrate, and wiring connected to the semiconductor devices. The peripheral structure (P) may include multiple transistors, block select circuits, page buffer circuits, multiple voltage switching circuits, and circuits corresponding to the peripheral circuit 510. After forming various circuits on the peripheral structure (P), a memory cell array 520 can be formed on the peripheral structure (P), and wiring for electrically connecting the memory cell array 520 and the circuits formed on the peripheral structure (P) can be formed. In this case, the memory 500 can be defined as having a peri-under-cell (PUC) structure.

[0073] Alternatively, the peripheral structure (P) and the memory cell structure (C) can be fabricated on different wafers and then bonded together to form a single unit via a wafer bonding process. In this case, the memory 500 can be defined as having a peri-over-cell (POC) structure.

[0074] If the peripheral structure (P) includes the ROM device 100, then the ROM device 100 can be disposed within the peripheral structure (P). The unit cells of the ROM device 100 can be disposed on a substrate, and the various circuits included in the peripheral structure (P) are arranged on the substrate. That is, as described above... Figure 4 The substrate 400 described can correspond to a substrate in which various circuits are included in the peripheral structure (P).

[0075] Figure 6 The planar structure of the comparison memory device is shown. Figure 7 Show along Figure 6 The cross section intercepted by line II-II'.

[0076] Reference Figure 6 and Figure 7 A device isolation layer 700 can be disposed between unit cells on the substrate 400. Specifically, the device isolation layer 700 can be disposed between the first unit cell CU1 and the second unit cell CU2. The device isolation layer 700 can be formed using trench device isolation technology such as shallow trench isolation (STI). The device isolation layer 700 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. Because the device isolation layer 700 is disposed between the first unit cell CU1 and the second unit cell CU2, the active region 600 can be electrically disconnected between the first unit cell CU1 and the second unit cell CU2.

[0077] The device isolation layer 700 can be used to isolate the first unit cell CU1 and the second unit cell CU2. That is, the device isolation layer 700 can isolate the transistors included in different units, so that operating the transistors included in the first unit cell CU1 will not affect the operation of the transistors included in the second unit cell CU2. Although not shown, the device isolation layer 700 may also be disposed between a unit cell and the second unit cell CU2 that are adjacent to each other in a different direction from the first unit cell CU1.

[0078] However, if the ROM device 100 includes the device isolation layer 700 as described above, the active region 600 may be physically isolated. Since the device isolation layers 700 are arranged between unit cells, as the ROM device 100 becomes more highly integrated, it may be necessary to increase the number of device isolation layers 700 to ensure more unit cells. As the number of device isolation layers 700 increases, the size of the active region 600 present on the substrate 400 may decrease, and therefore the active region 600 may be susceptible to stress caused by stress generated during the manufacturing process of the ROM device 100. Since stress may cause cracks or dislocations around the active region 600 and the device isolation layer 700, this may lead to defects or degraded characteristics of the ROM device.

[0079] Refer to Figure 3 and Figure 4In embodiments of this disclosure, the ROM device 100 may include an isolation transistor TR_ISO disposed between a first unit cell CU1 and a second unit cell CU2. The source or drain of the isolation transistor TR_ISO may be connected to the source of a second transistor TR2 included in the first unit cell CU1 and the source of a third transistor TR3 included in the second unit cell CU2. Additionally, the isolation transistor TR_ISO may include at least a portion of a gate line Vcc, and a ground voltage may be applied to the gate line Vcc.

[0080] Additionally, in embodiments of this disclosure, the active region 300 may extend from the region overlapping with the first unit cell CU1 to the region overlapping with the second unit cell CU2, and the isolation transistor TR_ISO may be disposed in the active region 300 between the first unit cell CU1 and the second unit cell CU2.

[0081] According to embodiments of this disclosure, the ROM device 100 may include an isolation transistor TR_ISO disposed between a first unit cell CU1 and a second unit cell CU2, and the isolation transistor TR_ISO may include a gate line Vcc, to which a ground voltage is applied. Therefore, even if no device isolation layer is provided between the first unit cell CU1 and the second unit cell CU2, that is, even if the active region 300 is not separated or disconnected, a memory device insulated from each other by the first unit cell CU1 and the second unit cell CU2 can be provided.

[0082] That is, in the embodiments of this disclosure, the active region 300 can extend from the region overlapping with the first unit cell CU1 to the region overlapping with the second unit cell CU2, and the off isolation transistor TR_ISO can be disposed in the active region 300 between the first unit cell CU1 and the second unit cell CU2, thereby providing a memory device that physically connects the active region 300 while the first unit cell CU1 and the second unit cell CU2 are electrically insulated from each other.

[0083] Therefore, the memory device according to the embodiments of the present disclosure can prevent the occurrence of cracks or dislocations that may occur during the manufacturing process, thereby preventing defects or degradation of the memory device.

[0084] Figure 8 This is a block diagram of a memory system including a memory device according to embodiments of the present disclosure.

[0085] Reference Figure 8 The memory system 800 may include a memory 500 for storing data and a controller 810 for controlling the memory 500.

[0086] The memory 500 can operate in response to the control of the controller 810. Here, the operation of the memory 500 can include, for example, read operations, programming operations (also known as "write operations"), and erase operations.

[0087] The memory 500 can be implemented in various types such as NAND flash memory, 3D NAND flash memory, NOR flash memory, etc.

[0088] The memory 500 can receive commands and addresses from the controller 810 and can access the address-selected region in the memory cell array 520. That is, the memory 500 can perform operations instructed by commands on the address-selected region.

[0089] For example, the memory 500 can perform programming operations, reading operations, erasing operations, etc. In this regard, when performing a programming operation, the memory 500 can program or write data to an area selected by an address. When performing a reading operation, the memory 500 can read data from an area selected by an address. When performing an erasing operation, the memory 500 can erase or delete the data stored in the area selected by an address.

[0090] The controller 810 can control write (i.e., programming), read, erase, and background operations on the memory 500. Here, background operations may include one or more of, for example, garbage collection (GC) operations, wear leveling (WL) operations, read reclamation (RR) operations, or bad block management (BBM) operations.

[0091] The controller 810 can control the operation of the memory 500 based on requests from a device located outside the memory system 800 (e.g., a host). Alternatively, the controller 810 can also control the operation of the memory 500 independently of requests from the host.

[0092] The host device can be a computer, ultra-mobile PC (UMPC), workstation, personal digital assistant (PDA), tablet computer, mobile phone, smartphone, e-book reader or portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, digital multimedia broadcast (DBM) player, smart TV, digital recorder, digital voice player, digital image recorder, digital image player, digital video recorder, digital video player, data center storage device, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a telematics network, radio frequency identification (RFID) device, mobile device that moves under human control or is capable of autonomous movement (e.g., vehicle, robot, drone), etc.

[0093] A host (HOST) may include at least one operating system. The operating system typically manages and controls the host's functions and operations, and controls the interoperability between the host and the storage system 800. Operating systems can be categorized into general-purpose operating systems and mobile operating systems based on the host's mobility.

[0094] On the other hand, the host and controller 810 can be separate devices. In some cases, the controller 810 can be integrated with the host and implemented as a single device. In the following examples, for ease of illustration, it is assumed that the controller 810 and the host are separate devices.

[0095] Reference Figure 8 The controller 810 may include a memory interface 812 and a control circuit 813, and may further include a host interface 811.

[0096] The host interface 811 can provide an interface for communication with a host. For example, the host interface 811 can provide an interface utilizing at least one of the following interface protocols: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, or a proprietary protocol.

[0097] The control circuit 813 can receive commands through the host interface 811 and perform operations to process the received commands in response to receiving commands from the host.

[0098] The memory interface 812 can be connected to the memory 500 and can provide an interface for communication with the memory 500. That is, the memory interface 812 can be configured to provide an interface between the memory 500 and the controller 810 in response to the control of the control circuit 813.

[0099] The control circuit 813 can perform the overall control operations of the controller 810 to control the operation of the memory 500. For this purpose, as an example, the control circuit 813 may include one or more of a processor 814 and a working memory 815, and may also optionally include error detection and correction circuitry, etc.

[0100] The processor 814 can control all operations of the controller 810 and perform logical operations. The processor 814 can communicate with the host (HOST) through the host interface 811 and with the memory 500 through the memory interface 812.

[0101] Processor 814 can perform the functions of a Flash Translation Layer (FTL). Processor 814 can use the Flash Translation Layer (FTL) to translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs). The Flash Translation Layer (FTL) can receive logical block addresses (LBAs) and use a mapping table to translate logical block addresses (LBAs) into physical block addresses (PBAs).

[0102] Depending on the mapping unit, the flash translation layer can use various address mapping methods. Address mapping methods can include page mapping methods, block mapping methods, and hybrid mapping methods.

[0103] The processor 814 can randomize data received from the host. For example, the processor 814 can randomize data received from the host using a preset randomization seed. The randomized data can be provided to the memory 500 and can be programmed into the memory cell array of the memory 500.

[0104] Processor 814 can derandomize data received from memory 500 during a read operation. For example, processor 814 can derandomize data received from memory 500 using a derandomization seed. The derandomized data can then be output to the host.

[0105] The processor 814 can control the operation of the controller 810 by executing firmware. That is, the processor 814 can execute or drive the firmware loaded into the working memory 815 at startup to control the overall operation of the controller 810 and perform logical operations.

[0106] Firmware can be a program that executes within memory system 800 to drive memory system 800, and can include various functional layers. For example, firmware can include binary data in which code is defined for executing each of the functional layers.

[0107] For example, the firmware may include one or more of the following: a flash translation layer (FTL) that performs a translation function between the logical address requested by the host from the memory system 800 and the physical address of the memory 500; a host interface layer (HIL) that interprets the commands requested by the host from the memory system 800, which is a storage device, and transmits the interpreted commands to the flash translation layer (FTL); and a flash interface layer (FIL) that transmits the commands indicated by the flash translation layer (FTL) to the memory 500.

[0108] Firmware can be loaded into working memory 815 from, for example, memory 500 or a separate non-volatile memory (e.g., ROM, NOR flash memory) located outside memory 500. When a boot operation is performed after power-on, processor 814 may first load all or part of the firmware into working memory 815.

[0109] Processor 814 can execute logical operations defined in firmware loaded into working memory 815 to control the overall operation of controller 810. Processor 814 can store the results of executing the logical operations defined in firmware into working memory 815. Processor 814 can control controller 810 to generate commands or signals based on the results of executing the logical operations defined in firmware. If a portion of the firmware defining the logical operation to be executed is not loaded into working memory 815, processor 814 can generate an event (e.g., an interrupt) to load the corresponding portion of the firmware into working memory 815.

[0110] The processor 814 can load metadata required to run the firmware from the memory 500. The metadata can be data used to manage the memory 500 and may include management information about user data stored in the memory 500.

[0111] Firmware can be updated during the manufacture of memory system 800 or during operation of memory system 800. Controller 810 can download new firmware from outside memory system 800 and use the new firmware to update existing firmware.

[0112] The working memory 815 can store firmware, program code, commands, or data required by the drive controller 810. The working memory 815 may include one or more of static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM) as volatile memory.

[0113] Bus 816 can be configured to provide a channel between components 811, 812, 814, and 815 of controller 810. Bus 816 may include, for example, a control bus for transmitting various control signals and commands, and a data bus for transmitting various data.

[0114] Some of the components 811, 812, 814, and 815 of the controller 810 described above may be omitted, or some of the components 811, 812, 814, and 815 of the controller 810 may be integrated into a single device. In some cases, one or more other components may be added in addition to the components of the controller 810 described above.

[0115] The above description is merely an illustrative description of the technical concept of this disclosure. Those skilled in the art can make various modifications and variations without departing from the basic characteristics of this disclosure. Furthermore, the embodiments disclosed in this disclosure are not intended to limit the technical concept of this disclosure, but rather to illustrate it. Therefore, the scope of the technical concept of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and all technical concepts within the equivalent scope of the claims should be interpreted as included within the scope of the rights of this disclosure.

Claims

1. A memory device, comprising: The active region is located on the substrate. The first unit cell and the second unit cell are disposed in the active region; as well as An isolation transistor is kept off and is disposed in the active region between the first unit cell and the second unit cell.

2. The memory device according to claim 1, wherein, The first unit cell and the second unit cell are arranged adjacent to each other in the first direction. The isolation transistor includes a gate line, and the gate line is configured to cross the active region in a second direction perpendicular to the first direction.

3. The memory device according to claim 2, wherein, Each of the first unit cell and the second unit cell includes a pair of word lines arranged parallel to each other on the active region. The gate line of the isolation transistor is disposed in the same layer as the word line of the first unit cell and the word line of the second unit cell.

4. The memory device according to claim 1, wherein, The isolation transistor is an NMOS transistor and receives a ground voltage independently of the operation of the first unit cell and the operation of the second unit cell.

5. The memory device according to claim 1, wherein, The active region includes: The first part, wherein the first unit unit is disposed in the first part; The second part, wherein the second unit cell is disposed in the second part; and The third part, wherein the isolation transistor is disposed in the third part. The upper surface of the third part is disposed on the same plane as the upper surfaces of the first part and the second part.

6. The memory device according to claim 1, wherein, Each of the first unit and the second unit stores two bits of information.

7. The memory device according to claim 1, wherein, The first unit cell and the second unit cell are connected to a single bit line.

8. The memory device according to claim 1, wherein, The isolation transistor shares a source with a transistor included in one of the first unit cell and the second unit cell, and shares a drain with a transistor included in the other of the first unit cell and the second unit cell.

9. The memory device according to claim 1, wherein, The first unit and the second unit are electrically disconnected from each other.

10. A memory device, comprising: The first unit cell includes a first transistor and a second transistor adjacent to the first transistor; The second unit cell includes a third transistor and a fourth transistor adjacent to the third transistor; as well as An isolation transistor is disposed between the first unit cell and the second unit cell, connected to the first unit cell and the second unit cell, and kept in an off state.

11. The memory device according to claim 10, wherein, The isolation transistor includes a gate line. Each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a word line. The gate line and the word line are disposed on the same layer.

12. The memory device according to claim 10, wherein, The isolation transistor is disposed between the second transistor and the third transistor, and shares a source or drain with the second transistor and the third transistor, respectively.

13. The memory device according to claim 10, wherein, The first transistor and the second transistor share a common drain, and the third transistor and the fourth transistor also share a common drain.

14. The memory device according to claim 13, wherein, The first unit cell is connected to a single bit line via a drain shared by the first transistor and the second transistor, and the second unit cell is connected to a single bit line via a drain shared by the third transistor and the fourth transistor.

15. The memory device according to claim 10, wherein, The second transistor and the third transistor are electrically disconnected from each other.

16. The memory device according to claim 10, wherein, Each of the first unit and the second unit stores two bits of information.

17. A memory device, comprising: Memory cell structure, including memory cell array; as well as The peripheral structure, located below the memory cell structure, includes peripheral circuitry and a ROM device. The peripheral circuitry transmits the voltages and signals required for the operation of the memory cell array, and the ROM device stores code data. The ROM device includes: The active region is located on the substrate. The first unit cell and the second unit cell are disposed in the active region; and An isolation transistor is disposed in the active region between the first unit cell and the second unit cell and remains in the off state.

18. The memory device according to claim 17, wherein, Each of the first unit and the second unit stores two bits of information.

19. The memory device according to claim 17, wherein, The isolation transistor includes a gate line. Each of the first unit cell and the second unit cell includes a pair of word lines arranged parallel to each other on the active region. The gate line and the word line are disposed on the same layer.

20. The memory device according to claim 17, wherein, The active region includes: The first part, wherein the first unit unit is disposed in the first part; The second part, wherein the second unit cell is disposed in the second part; and The third part, wherein the isolation transistor is disposed in the third part. The upper surfaces of the third part, the first part, and the second part are disposed on the same plane.

Images