Integrated circuit lamination packaging method

Abstract

The invention provides a laminated packaging method for an integrated circuit. The laminated packaging method comprises the following steps: step 1, laminating; step 2, cutting a single particle; step 3, electroplating; 4, etching is carried out; step 5, ball grid array (BGA) ball mounting; according to the integrated circuit stack packaging method, a plurality of integrated circuits of the same model are packaged in a stack mode, when the plurality of same integrated circuits are used in parallel, only one-time welding is needed, welding spots are reduced, and therefore the service life and reliability risks caused by welding quality are greatly reduced. Meanwhile, due to lamination packaging and stacking of a plurality of integrated circuits, the requirement for the area of the PCB is reduced, the whole PCBA can be miniaturized, the overall size and weight are reduced, the use field of the PCBA can be expanded, and space is provided for function expansion or miniaturization of the whole equipment.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit packaging, and particularly relates to an integrated circuit stacked packaging method. BACKGROUND

[0002] Miniaturization of integrated circuits is the demand and driving force for industry development. Realizing miniaturization of integrated circuits can expand the use field, reduce the cost of various materials, and at the same time, often improve reliability and bring unexpected good results.

[0003] There are many ways to miniaturize integrated circuits at present, and the more common ones are wafer-level optimization. Common methods include the following methods:

[0004] 1. Using smaller line width technology (currently in the mobile phone field, it has reached 3nm) to reduce the size of the chip;

[0005] 2. Using flip-chip technology to reduce the size of the package;

[0006] 3. Using direct ball planting technology on the surface of the chip to omit the package shell and reduce the size;

[0007] 4. Using chip punching technology to stack and connect the chip to reduce the size.

[0008] These technical methods are all processed at the wafer level to achieve the purpose of reducing the size and weight of the package structure. At present, there are a large number of traditional packaging forms in the industry, which have the following characteristics: 1. The product types are various, covering almost all customer needs; 2. The customer usage is large, and often multiple same type devices are needed in a PCB. 3. The cost of packaging form transformation is high, and often the entire production line needs to be purchased again, which will cause a lot of resource waste. The main shortcomings are as follows:

[0009] 1. High construction cost, need to rebuild the production line, and these production line equipment are often imported restricted equipment, expensive, and technical workers also need higher treatment requirements;

[0010] 2. Long production cycle, because the production line needs to be rebuilt, it often takes 2-3 years to achieve mass production;

[0011] 3. High construction difficulty, technology is foreign introduced technology, equipment is foreign equipment, and domestic technical personnel are very few;

[0012] 4. Resource waste, causing the waste of existing industrial resources, and wasting a lot of existing industrial resources;

[0013] 5. High product price, based on the above four reasons, the product price is high. SUMMARY

[0014] When multiple same type integrated circuits are used in parallel, multiple same devices are welded on a PCB, which increases the area of PCBA, the number of welding points and the weight, and the welding quality and reliability of the welding points directly affect the function and reliability of the entire PCBA, which reduces the overall service life and reliability of the PCBA and affects the service life and reliability of the entire equipment.

[0015] Therefore, the application provides an integrated circuit laminated packaging method, which comprises the following steps:

[0016] Step 1: Lamination

[0017] After the chip bonding and wire bonding are completed, the entire chip (containing multiple individual circuits) which has not been injection molded is arranged in an up-down lamination, and the circuits of the upper and lower layers should be aligned during lamination, and the entire chip is injection molded after the stacking is completed;

[0018] Step 2: Cutting of single piece

[0019] The laminated circuit of the entire chip after injection molding is cut to ensure that the lead-out ends of the internal individual circuits are exposed, and a single plastic encapsulation body is obtained;

[0020] Step 3: Electroplating

[0021] The single plastic encapsulation body after cutting is electroplated, and in order to ensure good adhesion and conductivity of the plating layer, nickel plating is first performed, and then gold plating is performed after the nickel plating is completed;

[0022] Step 4: Etching

[0023] The product after electroplating needs to be etched to connect the same legs exposed on the side of the single plastic encapsulation body and insulate the different legs from each other; meanwhile, the position of the bottom pad can be laid out through etching according to the distribution requirement of the subsequent welding points;

[0024] Step 5: BGA ball planting

[0025] The product after etching is bottom ball planted according to the layout after etching.

[0026] The application has the following advantages: the application provides the integrated circuit laminated packaging method, which stacks multiple same type integrated circuits, and only needs to be welded once when multiple same integrated circuits are used in parallel, thereby reducing the welding points and greatly reducing the service life and reliability risks caused by the welding quality. At the same time, because of the laminated packaging, multiple integrated circuits are stacked together, which reduces the requirement for the area of the PCB, miniaturizes the entire PCBA, reduces the overall volume and weight, and expands the use field of the PCBA, thereby providing space for the function expansion or miniaturization of the entire equipment.

[0027] The application will be described in detail below with reference to the drawings and embodiments. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the stacked arrangement of a whole chip that has been bonded and wire-bonded but has not yet been injection molded.

[0029] Figure 2 This is a schematic diagram of the stacked frame.

[0030] Figure 3 Schematic diagram of the injection-molded device Figure 1 .

[0031] Figure 4 Schematic diagram of the injection-molded device Figure 2 .

[0032] Figure 5 This is a schematic diagram of a device with a single cut surface exposing the lead-out end.

[0033] Figure 6 This is a schematic diagram of the product after electroplating.

[0034] Figure 7 This is a side view of the product after etching.

[0035] Figure 8 This is a schematic diagram of the bottom surface of the product after etching.

[0036] Figure 9 This is a front view of the product after the bulbs have been implanted.

[0037] Figure 10 This is a schematic diagram of the bottom surface of the product after the balls are planted.

[0038] Figure 11 This is a schematic diagram of a chip before it is packaged without stacking layers in a real-world example.

[0039] Figure 12 This is a schematic diagram of a chip after the stacked packaging is completed in a real-world case.

[0040] Figure 13 This is a 3D schematic diagram of chip X-ray inspection after the completion of stacked packaging in a real-world case. Detailed Implementation

[0041] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the specific implementation methods, structural features and effects of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0042] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present application.

[0043] All features disclosed in the specification, or all steps of the methods or processes disclosed in the specification, can be combined in any manner, except where features and / or steps are mutually exclusive.

[0044] Any feature disclosed in the specification, including any accompanying claims, abstract, and drawings, can be replaced by an alternative feature that is equivalent or has a similar purpose, unless specifically stated otherwise. That is, each feature is only an example of one of a range of equivalent or similar features, unless specifically stated.

[0045] Embodiment 1

[0046] When integrated circuits need to run in multiple parallel ways, multiple same devices need to be soldered on a PCB, which causes the area of the PCBA to increase, the number of solder joints to increase, and the weight and volume to increase, which limits the use of the integrated circuits in many fields and is not conducive to the realization of the functions of the entire equipment. At the same time, because many same integrated circuits need to be used on the PCB, each additional integrated circuit will increase more than 10 solder joints on average, resulting in a large increase in the number of solder joints of the entire PCBA, and the soldering quality and reliability of the solder joints directly affect the functions and reliability of the entire PCBA. This leads to a decrease in the overall service life and reliability of the PCBA, and affects the service life and reliability of the entire equipment.

[0047] Therefore, the present application provides an integrated circuit laminated packaging method, which uses a traditional production line and can perform secondary optimization lamination on the traditional packaging after only adding an etching process, better utilizes the existing production line scale technology, and solves the customer's miniaturization demand.

[0048] The integrated circuit laminated packaging method comprises the following steps:

[0049] Step 1: Lamination

[0050] As shown in Figure 1 , the whole frame (containing multiple individual circuits) produced by the existing production line and completed with chip bonding and wire bonding is arranged in an up-down lamination, and the circuits of the upper and lower layers should be aligned during lamination. The stacked frame is as shown in Figure 2 , and the frame is injected after stacking, and the typical epoxy molding compound injection temperature is controlled at 180℃±5℃ to ensure fluidity and reduce internal bubbles. The device after injection is as shown in Figure 3 ,Figure 4 as shown;

[0051] Step 2: Cutting of single piece

[0052] The completed whole piece of injection-molded stacked circuit is cut, and the cutting process should use a cutting method that produces less vibration (such as diamond precision cutting), while ensuring that the lead-out ends of the internal single circuits are exposed, obtaining a single piece of plastic package, and the cutting surface of the exposed lead-out end is as shown in Figure 5 as shown;

[0053] Step 3: Electroplating

[0054] The single piece of plastic package after cutting is electroplated, and the purpose of electroplating is to electrically connect the lead legs of the same function on the first frame, the second frame, and the third frame of the cut product, and also has the effects of shielding electromagnetic interference, preventing oxidation and corrosion, and improving use reliability. In order to ensure good adhesion and conductivity of the plating layer, the whole is first plated with nickel, the thickness of the nickel layer is controlled at 1.2 μm ± 0.3 μm, and after the nickel plating is completed, gold plating protection is carried out, the thickness of the gold layer is ≥ 5 μm, and the product after electroplating is as shown in Figure 6 as shown;

[0055] Step 4: Etching

[0056] The product after electroplating needs to be etched; the purpose of etching is to electrically connect the lead legs of the same function on the first frame, the second frame, and the third frame of the cut product, while removing the plating layer of the short-circuit part, and forming good insulation between the lead legs of different functions. In addition, according to the future demand for PCB, the bottom can be etched to allocate the pad position as needed.

[0057] Etching method: using laser and the like to remove the unnecessary plating layer part, so that the lead legs of the same function are electrically connected, and the etched product is obtained Figure 7 , Figure 8 . At the same time, X-ray etching, electron beam etching or ion beam etching can be used; (the original PCBA wiring can also be used for bottom pad redistribution etching, which can maximize the adaptability of the product).

[0058] Step 5: BGA ball planting

[0059] According to the distribution of the etched bottom pad, the product after etching is planted with balls. The purpose of ball planting is to facilitate the later board installation and improve heat dissipation. Lead solder balls or lead-free solder balls can be selectively used. The product after ball planting is as shown in Figure 9 , Figure 10 . After the ball planting is completed, it can be tested and used.

[0060] In summary, this embodiment provides an integrated circuit stacked packaging method that stacks multiple identical integrated circuits. When using multiple identical integrated circuits in parallel, only one soldering step is required, reducing solder joints and significantly lowering the lifespan and reliability risks caused by soldering quality. Furthermore, because of the stacked packaging, multiple integrated circuits are placed together, reducing the required PCB area, allowing for miniaturization of the entire PCBA. This reduces the overall size and weight, expands the application areas of the PCBA, and provides space for functional expansion or miniaturization of the entire equipment.

[0061] Example 2

[0062] Using the integrated circuit stacked packaging method shown in Example 1, for Figure 11 The 4GB SOP packaged memory shown is subjected to stacked packaging. The finished product after stacked packaging is as follows: Figure 12 As shown. Its internal three-dimensional structure is scanned and imaged using X-rays, as... Figure 13 As shown. With 8-layer devices stacked, the capacity increases from 2GB to 32GB in the same area, which is 4 times the original capacity. When mounted on the PCB, the total number of solder joints is reduced from 48*8 to 48 after packaging, which is 48*7. At the same time, the total weight of the PCBA will also be reduced by 48*7 solder joints.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for stacked packaging of integrated circuits, characterized in that, Includes the following steps: Step 1: Layering; Stack the entire chip (containing multiple individual circuits) that has been bonded and wire-bonded but not yet injection molded into layers. Ensure that the circuits in the upper and lower layers are aligned during stacking. After stacking, perform injection molding on the entire chip. Step 2: Cut each piece individually; The entire stacked circuit after injection molding is cut to ensure that the leads of each individual circuit inside are exposed, resulting in a single encapsulated unit. Step 3: Electroplating; Electroplating is performed on the cut individual plastic seals. To ensure good adhesion and conductivity of the plating, nickel plating is performed on the whole body first, and then gold plating is performed after nickel plating is completed. Step 4: Etching; After electroplating, the product needs to be etched to connect the same legs exposed on the side of the individual molded body, and to insulate different legs from each other; at the same time, the bottom pad positions can be laid out by etching according to the subsequent solder joint distribution requirements. Step 5: BGA ball placement; Based on the etched wiring, the bottom of the etched product is then ball-planted.

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