A circuit board and its manufacturing method, and an electronic device.

Abstract

This invention discloses a circuit board and its manufacturing method, as well as an electronic device, relating to the field of circuit board technology. The circuit board includes: a bottom layer, and stacked layers of a chip embedding layer, a drive aggregation layer, a first power layer, a second power layer, a shielding layer, a drive circuit layer, and a top layer. The chip embedding layer contains a power chip; the drive aggregation layer aggregates and transmits drive signals to the power chip; the first and second power layers respectively transmit the positive and negative potentials of the bus and the midpoint potential current; the shielding layer separates the power and drive circuits to shield against corresponding electromagnetic interference; the drive circuit layer contains drive signal lines; and the top layer carries drive components. This layered, three-dimensional collaborative layout of the drive and power circuits, along with the integrated shielding layer, suppresses electromagnetic interference and enhances anti-interference capabilities. The power chip embedding combined with the integrated design of the drive circuit significantly reduces the drive circuit area and stray inductance, lowers the volume, improves power density and dynamic response performance, and achieves a high degree of compatibility between the drive circuit and the power chip.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a circuit board and its manufacturing method, as well as electronic devices. Background Technology

[0002] Current power electronic systems pursue higher efficiency, power density and switching frequency, but traditional drive integration solutions have bottlenecks. Their drive paths are long and parasitic inductance is large, resulting in high switching losses, voltage overshoot and electromagnetic interference problems, which occupy circuit board space and limit design flexibility.

[0003] In high-frequency switching, low parasitic inductance and synergistic optimization of power circuit and drive circuit are key, but traditional layouts do not fully utilize the mutual inductance cancellation effect, and the three-dimensional interconnection characteristics are not effectively utilized when power chips are embedded, resulting in suboptimal electrical performance. Summary of the Invention

[0004] The purpose of this invention is to provide a circuit board and its manufacturing method, as well as an electronic device, which can effectively suppress electromagnetic interference, improve the system's anti-interference capability, reduce the loop area and stray inductance, improve power density and dynamic response performance, and achieve a high degree of compatibility between the drive circuit and the power chip.

[0005] To solve the above-mentioned technical problems, the present invention provides a circuit board, comprising: a bottom layer, a chip embedding layer, a driver aggregation layer, a first power layer, a second power layer, a shielding layer, a driver circuit layer, and a top layer stacked on the bottom layer;

[0006] The chip embedding layer includes a power chip in a power circuit;

[0007] The drive aggregation layer is used to aggregate the drive signals transmitted from the top layer and the drive circuit layer, and to transmit the aggregated drive signals to the power chip built into the chip embedding layer.

[0008] The first power layer is used to transmit the current at the positive potential of the bus in the power circuit;

[0009] The second power layer is used to transmit the current between the bus negative potential and the midpoint potential in the power circuit;

[0010] The shielding layer is used to physically separate the power circuit from the drive circuit and shield the corresponding electromagnetic interference;

[0011] The drive circuit layer is used to arrange the drive signal lines of the drive circuit;

[0012] The top layer is used to support various components of the drive circuit.

[0013] To address the aforementioned technical problems, the present invention also provides a method for manufacturing a circuit board, comprising:

[0014] A chip embedding layer is formed, and a power chip is integrated within the chip embedding layer;

[0015] These layers are respectively formed as a bottom layer, a drive aggregation layer, a first power layer, a second power layer, a shielding layer, a drive circuit layer, and a top layer;

[0016] The bottom layer, the chip embedding layer, the driver aggregation layer, the first power layer, the second power layer, the shielding layer, the driver circuit layer, and the top layer are stacked in a predetermined order;

[0017] A circuit board is obtained by laminating the bottom layer, the chip embedding layer, the driver aggregation layer, the first power layer, the second power layer, the shielding layer, the driver circuit layer, and the top layer using a lamination process.

[0018] To address the aforementioned technical problems, the present invention also provides an electronic device, including the circuit board described above.

[0019] As can be seen from the above technical solution, the circuit board provided by the present invention includes: a bottom layer, a chip embedding layer, a drive aggregation layer, a first power layer, a second power layer, a shielding layer, a drive circuit layer, and a top layer stacked on the bottom layer; wherein, the chip embedding layer includes a power chip in the power circuit; the drive aggregation layer is used to aggregate the drive signals transmitted from the top layer and the drive circuit layer, and to transmit the aggregated drive signals to the power chip built into the chip embedding layer; the first power layer is used to transmit the current at the positive potential of the bus in the power circuit; the second power layer is used to transmit the current at the negative potential of the bus and the midpoint potential in the power circuit; the shielding layer is used to physically separate the power circuit from the drive circuit and block the power ripple generated by the power circuit; the drive circuit layer is used to arrange the drive signal lines of the drive circuit; and the top layer is used to carry various components of the drive circuit.

[0020] The beneficial effects of the present invention are as follows: the circuit board provided by the present invention, through the layered three-dimensional collaborative layout of the drive circuit and the power circuit, combined with the integrated shielding layer to achieve physical separation between the power circuit and the drive circuit, effectively shields high-power electromagnetic interference and enhances the system's anti-interference capability; furthermore, by embedding the power chip inside the circuit board, combined with the integrated design of the drive circuit layer and the top layer drive circuit, the area of ​​the drive circuit and stray inductance are greatly reduced, while the overall size of the system is reduced, the power density and dynamic response performance are improved, and the drive circuit and power chip are highly compatible. It is especially suitable for power electronics fields such as new energy, data center server power supplies, industrial frequency converters and servo drives, and aerospace systems, which have stringent requirements for power density, conversion efficiency, switching performance and reliability.

[0021] In addition, the present invention also provides a corresponding manufacturing method and electronic equipment for circuit boards, which have the same or corresponding technical features as the circuit boards mentioned above, and have the same effects. Attached Figure Description

[0022] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A cross-sectional schematic diagram of a circuit board provided in an embodiment of the present invention;

[0024] Figure 2 A front view of a circuit board provided in an embodiment of the present invention;

[0025] Figure 3 A flowchart illustrating a circuit board manufacturing method provided in an embodiment of the present invention.

[0026] Among them, 1 is the bottom layer, 2 is the chip embedding layer, 3 is the driver aggregation layer, 4 is the first power layer, 5 is the second power layer, 6 is the shielding layer, 7 is the driver circuit layer, 8 is the top layer, 9 is the staggered buried via, 10 is the independent copper pour structure, and 11 is the smallest power unit. Detailed Implementation

[0027] Current power electronic systems strive for higher efficiency, power density, and switching frequency, but traditional driver integration methods face significant bottlenecks. Traditional solutions primarily rely on discrete mounting of driver chips and power devices on the surface of a circuit board (PCB) or interconnection within modules, or even integrated circuit (IC) solutions. These solutions generally suffer from excessively long drive paths, high parasitic inductance leading to high switching losses, voltage overshoot, and electromagnetic interference (EMI) issues. Furthermore, they occupy PCB surface space, limiting power density increases, and restricting heat dissipation paths and design flexibility, making it difficult to meet the demands of advanced applications. Moreover, in high-frequency switching, extremely low parasitic inductance and synergistic optimization of the power and drive circuits are crucial. However, traditional layouts typically physically separate the two, resulting in lengthy paths that fail to effectively utilize the mutual inductance cancellation effect between circuits. Especially when the power chip is embedded within the circuit board, its three-dimensional interconnect characteristics are not fully utilized to achieve extreme shortening of the drive circuit (particularly the critical gate path) and optimal spatial overlap and coupling with the embedded power circuit, resulting in overall electrical performance falling short of theoretical optimality. Embedding power chips into circuit boards and building high-density interconnects faces core technological challenges, particularly the aspect ratio limitation in the via copper plating process. When the aspect ratio (the ratio of hole depth to hole diameter) is too large, it becomes difficult to ensure the continuity and uniformity of copper plating thickness on the hole bottom and walls, easily leading to problems such as copper cracking, voids, or excessively high resistance. This not only directly affects the electrical performance and long-term reliability of the interconnects but also severely limits the ability to achieve the high-density, fine-width / spacing, and low-inductance via interconnects required for the drive circuit above and around the embedded chip. This makes it difficult to reliably implement the theoretically optimal ultra-short gate drive path layout in terms of process technology, becoming a key bottleneck restricting system performance breakthroughs. To solve the above technical problems, this invention provides a circuit board.

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0029] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0030] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] An embodiment of the present invention provides a circuit board. Figure 1 This is a schematic diagram of the circuit board structure provided in an embodiment of the present invention, such as... Figure 1 As shown, the circuit board includes: a bottom layer 1, a chip embedding layer 2, a drive aggregation layer 3, a first power layer 4, a second power layer 5, a shielding layer 6, a drive circuit layer 7, and a top layer 8 stacked on the bottom layer 1.

[0032] Among them, chip embedding layer 2 includes power chips in power circuits;

[0033] The driver aggregation layer 3 is used to aggregate the drive signals transmitted from the top layer 8 and the drive line layer 7, and then transmit the aggregated drive signals to the power chip built into the chip embedding layer 2.

[0034] The first power layer 4 is used to transmit the current at the positive potential of the bus in the power loop;

[0035] The second power layer 5 is used to transmit the current between the bus negative potential and the midpoint potential in the power loop;

[0036] Shielding layer 6 is used to physically separate the power circuit from the drive circuit and block the power ripple generated by the power circuit;

[0037] Drive circuit layer 7 is used to arrange the drive signal lines of the drive circuit;

[0038] Top layer 8, used to carry various components of the drive circuit.

[0039] In the circuit board provided in this embodiment of the invention, the power circuit and the drive circuit are arranged in a layered three-dimensional collaborative layout. The integrated shielding layer 6 achieves physical separation between the power circuit and the drive circuit, effectively shielding high-power electromagnetic interference and enhancing the system's anti-interference capability. Furthermore, by embedding the power chip inside the circuit board and combining the integrated design of the drive circuit in the drive circuit layer 7 and the top layer 8, the area of ​​the drive circuit and stray inductance are significantly reduced, while the overall system size is reduced, power density and dynamic response performance are improved, and a high degree of compatibility between the drive circuit and the power chip is achieved. This is especially suitable for power electronics fields such as new energy, data center server power supplies, industrial frequency converters and servo drives, and aerospace systems, where power density, conversion efficiency, switching performance, and reliability requirements are stringent.

[0040] It should be noted that traditional embedded circuit boards use external driver cores, resulting in large drive circuits and limited power density. The integrated low-inductance circuit design of the drive circuit and embedded circuit board in this invention reduces the drive circuit area and clutter, lowers the overall size, and provides better compatibility with power chips. Traditional methods of embedding power chips can cause electromagnetic coupling interference such as drive / power circuit crosstalk. However, the three-dimensional collaborative layout and electromagnetic shielding architecture of the drive-power circuits in this invention, with layered layouts of the drive and power circuits and an integrated shielding layer to block electromagnetic noise propagation, significantly enhances the system's anti-interference capability.

[0041] In practical applications, the power device of this invention can be any type of power device, such as a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET). The circuit board of this invention is a three-dimensional collaborative layout integrated structure, which, arranged from top to bottom, may include a top layer, a drive line layer, a shielding layer, a second power layer, a first power layer, a drive convergence layer, a chip embedding layer, and a heat dissipation bottom layer. Each layer may be filled with resin material (such as FR4, high TG resin) or other insulating material.

[0042] Furthermore, in specific implementations, in the circuit board provided in the embodiments of the present invention, as follows: Figure 1 As shown, the driving circuit layer 7 can be connected to the driving aggregation layer 3 through the first buried via; the driving aggregation layer 3 can be connected to the corresponding pin of the power chip built into the chip embedding layer 2 through the second buried via. The first buried via of the driving circuit layer 7, the second buried via of the driving aggregation layer 3, the third buried via of the first power layer 4, and the fourth buried via of the second power layer 5 can all be non-overlapping in the vertical direction and staggered from each other in the horizontal position.

[0043] In implementation, such as Figure 1As shown, the drive circuit layer 7 is connected to the drive aggregation layer 3 via a first buried via. The drive aggregation layer 3 then connects to the power chip pins of the chip embedding layer 2 via a second buried via, thus constructing a precise drive signal transmission path. The first and second buried vias are offset in the vertical direction (not perfectly aligned lines). This design avoids electromagnetic coupling and thermal stress concentration, ensuring the integrity of the drive signal transmission. Simultaneously, the first via of the drive circuit layer 7, the second via of the drive aggregation layer 3, the third via of the first power layer 4, and the fourth via of the second power layer 5 are actually buried via structures belonging to different layers. The buried vias do not overlap vertically and are horizontally offset, forming a staggered buried via layout (also known as a microvia misalignment design). This achieves highly reliable microvia interconnection between the drive and power circuits, providing support for the construction of an extremely short gate drive path; effectively overcoming the microvia copper plating challenge caused by aspect ratio limitations, ensuring interconnection stability and the realization of an extremely short drive path; and simultaneously enhancing circuit current carrying capacity and heat dissipation performance, adapting to high-power, high-junction-temperature power device applications.

[0044] It should be noted that the aspect ratio limitation in traditional structures leads to incomplete copper plating of microvias, which easily results in voids in the via walls and high-resistance connections. However, the staggered stacking and independent copper plating design of the microvias in this invention can achieve highly reliable microvia interconnection of the drive and power circuits, support the construction of extremely short gate drive paths, and thus solve the problems of drive circuit performance and power circuit layout interconnection.

[0045] Furthermore, in specific implementations, in the circuit board provided in the embodiments of the present invention, as follows: Figure 1 As shown, the first power layer 4 can be connected to the second power layer 5 and the power chip built into the chip embedding layer 2 through the third buried via; the second power layer 5 can be connected to the first power layer 4 and the power chip built into the chip embedding layer 2 through the fourth buried via.

[0046] In implementation, both the first power layer 4 and the second power layer 5 are used for main power current routing. The first power layer 4 and the second power layer 5 are interconnected via the third and fourth buried vias. Simultaneously, both are connected to the power chip within the chip embedding layer 2 via corresponding buried vias, constructing a complete and compact power loop conduction path. This connection method ensures efficient transmission of power loop current between each power layer and the power chip, shortens the current conduction path, significantly reduces stray inductance and conduction losses in the power loop, and improves system power conversion efficiency. The tight interlayer interconnection and direct chip connection design reduce signal attenuation and interference during power transmission, enhancing the operational stability of the power loop.

[0047] Furthermore, in specific implementations, in the circuit board provided in the embodiments of the present invention, as follows: Figure 1As shown, an independent copper plating structure 10 can be provided inside the first buried via of the drive circuit layer 7; the independent copper plating structure 10 can be used to separate the drive section from the power section.

[0048] In implementation, the first buried via of the drive circuit layer 7 can be used to separate the drive section from the power section through independent copper pouring, providing a channel for drive signal transmission. This independent copper pouring design ensures the stability and reliability of the connection between the drive circuit layer 7 and the drive aggregation layer 3, reduces contact resistance and loss during signal transmission, ensures efficient transmission of drive signals, and avoids crosstalk between signals from different circuits through the buried via, further improving the integrity of the drive circuit signal.

[0049] Furthermore, in specific implementations, in the circuit board provided in the embodiments of the present invention, as follows: Figure 1 As shown, when the chip embedding layer 2 may include a first power chip and a second power chip, the first power chip and the second power chip form a bridge arm; the first power layer 4 is connected to the positive potential of the bridge arm bus; a part of the second power layer 5 is connected to the negative potential of the bridge arm bus, and the other part is connected to the midpoint potential of the bridge arm.

[0050] In implementation, when the chip embedding layer 2 includes the first and second power chips, they form a circuit bridge arm, constituting the core unit for power conversion. The first power layer 4 connects to the positive potential of the bridge arm bus, and the second power layer 5 can be divided into two parts: one part handles the connection function of the negative potential of the bridge arm bus, and the other part handles the connection function of the potential of the bridge arm midpoint, realizing precise allocation and isolation of power loop potentials. This layout effectively reduces mutual interference between different potentials, improving the stability and accuracy of power conversion; by layering and dedicatedly carrying different potentials, the power current transmission path can be shortened, stray inductance and power loss in the loop can be reduced, and the system power conversion efficiency can be improved.

[0051] Furthermore, in a specific implementation, in the circuit board provided in the embodiments of the present invention, the first power chip corresponds to the first power device; the second power chip corresponds to the second power device; the first power layer 4 is connected to the drain of the first power device; a portion of the second power layer 5 is connected to the source of the second power device, and another portion is connected to the source of the first power device or the drain of the second power device.

[0052] In implementation, the first power chip and the second power chip are associated with their corresponding power devices. The first power layer 4 is connected to the drain of the first power device, and the second power layer 5 is partitioned to connect the source of the second power device and either the source or drain of the first power device, thus constructing a clear power device potential connection architecture. This connection method achieves precise docking of each electrode of the power device with its corresponding power layer, ensuring orderly transmission of power loop current, reducing circuit faults caused by potential confusion, and shortening the power current transmission path, thereby reducing stray inductance and conduction losses in the loop.

[0053] Furthermore, in specific implementations, in the circuit board provided in the embodiments of the present invention, as follows: Figure 1 As shown, the chip embedding layer 2 can be formed into the smallest power unit 11 containing the power chip through a silver sintering process. The chip embedding layer 2 may also include an insulating resin material; the smallest power unit 11 is embedded in the insulating resin material. The chip embedding layer 2 serves as the interface layer between the drive convergence layer 3, the first power layer 4, and the second power layer 5, realizing the convergence and interface of drive signals and power currents at the power chip end.

[0054] In implementation, the power chip embedded in the chip embedding layer 2 undergoes silver sintering and other processes to form a minimum power unit 11, which has a copper cladding thickness greater than 50μm. Each minimum power unit contains multiple parallel bare chips and a ceramic substrate, and this minimum power unit 11 can be embedded in an insulating resin material. Since power devices typically operate at high junction temperatures, a high TG value resin material can be used to effectively protect the power chip and reduce the impact of the external environment on the chip. In addition, the chip embedding layer 2 serves as the interface layer between the drive convergence layer 3, the first power layer 4, and the second power layer 5, enabling the convergence and interface function of drive signals and power currents at the power chip end, shortening the transmission path, reducing signal attenuation and interference, and optimizing the overall circuit board space layout.

[0055] Furthermore, in a specific implementation, in the circuit board provided in the embodiments of the present invention, the shielding layer 6 can be connected to the source or Kelvin source of the power device corresponding to the power chip in the chip embedding layer 2. The shielding layer 6 can be used to form a spatial separation in the spatially overlapping area of ​​the drive circuit and the power circuit.

[0056] In implementation, shielding layer 6 is used to separate the drive circuit from the power circuit to reduce interference from high-power ripple on the drive circuit. Shielding layer 6 itself requires a reference potential for effective shielding, which can be connected to the source of the power chip or a Kelvin source connection. This synchronizes the reference potential of shielding layer 6 with that of the drive circuit, minimizing the potential difference between them and thus weakening capacitive coupling interference. Furthermore, shielding layer 6 forms a physical separation in the spatial overlap area of ​​the drive circuit and the power circuit, shielding against high-power electromagnetic interference and improving drive signal integrity. Simultaneously, it optimizes the spatial layout compatibility of the drive circuit and the power circuit, enhancing the system's anti-interference capability.

[0057] Furthermore, in a specific implementation, in the circuit board provided in the embodiments of the present invention, the drive aggregation layer 3 can be used to aggregate the gate and Kelvin source drive signals transmitted by the top layer 8 and the drive line layer 7, and transmit the aggregated gate and Kelvin source drive signals to the gate and Kelvin source pins of the power chip connected to the chip embedding layer 2.

[0058] In implementation, the driver aggregation layer 3 can aggregate the gate and Kelvin source drive signals transmitted from the top layer 8 and the drive circuit layer 7, and directly and accurately transmit the aggregated signals to the corresponding pins of the power chip in the chip embedding layer 2 through buried vias. This centralized aggregation of drive signals shortens the path from transmission to application to the power chip, reduces signal delay and attenuation during transmission, improves drive response speed, ensures the accuracy of power chip switching control, avoids interference and confusion caused by multi-path signal transmission, and enhances the integrity and stability of the drive signals.

[0059] Furthermore, in specific implementations, in the circuit board provided in the embodiments of the present invention, both the first power layer 4 and the second power layer 5 can be multi-layer composite conductive layer structures composed of multiple copper layers and insulating resin layers.

[0060] In implementation, both the first power layer 4 and the second power layer 5 can include multiple layers of copper and insulating resin to achieve high current carrying capacity. The copper foil thickness of the first power layer 4 and the second power layer 5 can be flexibly selected according to the actual current size, and multiple power layers can also be used to reduce the impact of proximity effect. Multiple copper layers significantly improve the current carrying capacity of the power layer, can carry larger power currents, and are suitable for high-power scenarios; the alternating combination of copper layers and insulating resin layers enhances the mechanical strength and structural stability of the power layer, extending its service life; the isolation effect of the insulating resin layer avoids the risk of interlayer short circuits and ensures the safe operation of the power circuit.

[0061] It should be noted that this invention can be applied to high-power scenarios, with the power layer employing a thick copper design. Due to limitations in the aspect ratio of via copper plating, microvia copper plating is incomplete. This invention utilizes a staggered microvia design to ensure electrical connection and the current-carrying capacity of the buried vias. When the drive circuit and power circuit overlap spatially, the top layer and drive circuit layer achieve electrical connection and spatial separation through independent copper plating design and staggered vias. The vertical shortest path optimizes the drive circuit and reduces noise.

[0062] Furthermore, in a specific implementation, in the circuit board provided in the embodiments of the present invention, the bottom layer 1 can be a heat dissipation bottom layer, using a microfluidic heat dissipation method to conduct heat generated by the chip embedding layer 2.

[0063] In implementation, the bottom layer 1 serves as the heat dissipation layer and can be a heat dissipation substrate for power semiconductors. Due to the high heat flux density resulting from high power density, a microchannel heat dissipation method is used to dissipate the heat generated by the chip embedding layer 2, constructing a targeted heat dissipation path. Microchannel heat dissipation increases the heat dissipation area through a dense channel structure, improving heat exchange efficiency and quickly dissipating the large amount of heat generated during power chip operation. This effectively controls the chip's operating temperature, avoids performance degradation or failure due to high temperatures, and ensures long-term stable operation of the power chip.

[0064] Figure 2 This is a front view of a circuit board provided in an embodiment of the present invention. In specific implementations, in the circuit board provided in the embodiments of the present invention, as shown... Figure 2 As shown, top layer 8 can be connected to an isolated auxiliary power supply. Specifically, top layer 8 can be used for isolated driving, desaturation protection, Miller clamping, undervoltage protection, and overvoltage protection of the drive circuit. The components of the drive circuit carried on top layer 8 can include driver chips, resistors, capacitors, diodes, and transistors.

[0065] In implementation, the top layer (8) can be used for components in the surface-mount drive circuit, such as driver chips, resistors, capacitors, diodes, and transistors. Powered by an isolated auxiliary power supply, it features isolated drive, desaturation protection, Miller clamping, and undervoltage / overvoltage protection. The isolated auxiliary power supply achieves electrical isolation between the drive circuit and other circuits, preventing common-mode interference from affecting the stability of the drive signal and improving system safety. Desaturation protection prevents overcurrent in power devices, Miller clamping suppresses false conduction, and undervoltage / overvoltage protection ensures circuit safety under abnormal voltage conditions, providing comprehensive protection for the power chip and drive circuit, significantly enhancing system reliability. The top layer, in conjunction with the drive circuit layer, enables drive circuit routing design, allowing for high integration of drive control and protection functions, optimizing PCB space utilization, and contributing to system miniaturization and increased power density.

[0066] It should be noted that the circuit board structure of this invention is suitable for power conversion systems of high-power modules. Through multi-layer layout and embedded design, it achieves good heat dissipation performance, low loop inductance, and integrity of drive signals. In the circuit board of this invention, the top layer 8 can be used to arrange pads for drive components, signal interfaces, and traces. The drive line layer 7 can be used to arrange drive signal lines, ensuring the independence and low noise of the drive circuit; the shielding layer 6 can be placed between the drive line layer and the power layer to isolate the power section from interference to the drive signal. The second power layer 5 and the first power layer 4 respectively arrange positive and negative power buses. The staggered stacking design reduces loop inductance and improves system response speed. It is recommended that the positive power bus be placed on the first power layer and the negative power bus be placed on the second power layer. This design can reduce power loop noise and reduce the number of cross-connects. The positive power bus is connected to the drain of the upper transistor (chip substrate) on the first power layer 4 through cross-connects. The source of the upper transistor and the drain of the lower transistor are connected on the first power layer 4 through cross-connects and copper pour. The source of the lower transistor is connected to the negative power bus on the second power layer 5 through cross-connects, thus forming a loop. The drive aggregation layer 3 can aggregate various drive signals and distribute them to each smallest power unit (i.e., the power chip after silver sintering and other treatments). The chip embedding layer 2 can be used to embed power chips (MOSFETs or IGBTs), shortening the signal path and improving system reliability. The bottom layer 1 can use a high thermal conductivity substrate and contact an external heat sink to achieve efficient thermal management.

[0067] In addition, the structure also features staggered buried vias 9 to connect power and drive copper layers at different levels, avoiding electromagnetic coupling and thermal stress concentration caused by via alignment. Due to the high power output, the power layer uses a thick copper design, while the drive layer can use a standard 1oz or 2oz copper layer thickness.

[0068] The minimum power unit 11 is the basic component module in the structure. Each unit includes a power switching device, a drive circuit, and a local heat dissipation structure. Multiple units can be connected in parallel to expand the structure to meet the needs of high-current applications.

[0069] This embodiment effectively improves power density, suppresses electromagnetic interference, and optimizes thermal management performance through the above-described stacked design and embedded installation, making it suitable for high-frequency, high-current power electronic devices.

[0070] From the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by software plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0071] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a circuit board. Figure 3 This is a flowchart illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. Figure 3 As shown, the method for manufacturing this circuit board includes the following steps:

[0072] S301. Form a chip embedding layer and integrate a power chip within the chip embedding layer.

[0073] S302, respectively forming a bottom layer, a drive convergence layer, a first power layer, a second power layer, a shielding layer, a drive circuit layer, and a top layer.

[0074] S303: Stack the bottom layer, chip embedding layer, driver aggregation layer, first power layer, second power layer, shielding layer, driver circuit layer and top layer in a set order.

[0075] S304. A lamination process is used to laminate the bottom layer, chip embedding layer, driver aggregation layer, first power layer, second power layer, shielding layer, driver circuit layer and top layer to obtain a circuit board.

[0076] In the circuit board manufacturing method provided in the embodiments of the present invention, the power circuit and the driving circuit can be physically separated by a layered three-dimensional collaborative layout and an integrated shielding layer, which effectively shields high-power electromagnetic interference and enhances the system's anti-interference capability. Furthermore, by embedding the power chip inside the circuit board and combining the integrated design of the driving circuit layer and the top driving circuit, the driving circuit area and stray inductance are greatly reduced, while the overall system volume is reduced, the power density and dynamic response performance are improved, and a high degree of compatibility between the driving circuit and the power chip is achieved.

[0077] Since the embodiments of the circuit board manufacturing method correspond to the embodiments of the circuit board, the description of the features in the embodiment corresponding to the circuit board manufacturing method can be found in the relevant description of the embodiment corresponding to the circuit board, and will not be repeated here. Furthermore, it has the same beneficial effects as the circuit board mentioned above.

[0078] Furthermore, in a specific implementation, in the circuit board manufacturing method provided in the embodiments of the present invention, the driving circuit layer can be connected to the driving aggregation layer through a first buried via; the driving aggregation layer can be connected to the corresponding pins of the power chip built into the chip embedding layer through a second buried via. The first buried via of the driving circuit layer, the second buried via of the driving aggregation layer, the third buried via of the first power layer, and the fourth buried via of the second power layer can all be non-overlapping in the vertical direction and staggered from each other in the horizontal position.

[0079] Embodiments of the present invention also provide an electronic device, including any of the circuit board embodiments described above.

[0080] The circuit board, its manufacturing method, and electronic device provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A circuit board, characterized by, The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board.

2. The circuit board of claim 1, wherein The application relates to a power and drive circuit board. The application relates to a power and drive circuit board.

3. The circuit board of claim 1, wherein The application relates to a power and drive circuit board.

4. The circuit board of claim 3, wherein The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board.

5. The circuit board of claim 1, wherein The application relates to a power and drive circuit board. The application relates to a power and drive circuit board.

6. The circuit board of claim 1, wherein The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. The application relates to a power and drive circuit board. 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8. The circuit board of claim 1, wherein, The first power layer and the second power layer are both multi-layer composite conductive layer structures composed of multi-layer copper layers and insulating resin layers.

9. The circuit board of claim 1, wherein, The bottom layer is a heat dissipation bottom layer adopting a micro-channel heat dissipation mode, and is used for leading out heat generated by the chip embedding layer.

10. The circuit board of claim 1, wherein, The top layer is connected with an isolated auxiliary power supply, and is used for isolated driving, desaturation protection, Miller clamping, under-voltage protection and over-voltage protection of the driving circuit.

11. The circuit board of claim 1, wherein, Components of the driving circuit carried on the top layer include driving chips, resistors, capacitors, diodes and triodes.

12. A method of manufacturing a circuit board as claimed in any one of claims 1 to 11, characterized in that The circuit board comprises: forming a chip embedding layer and integrating a power chip in the chip embedding layer; forming a bottom layer, a driving collection layer, a first power layer, a second power layer, a shielding layer, a driving circuit layer and a top layer respectively; stacking the bottom layer, the chip embedding layer, the driving collection layer, the first power layer, the second power layer, the shielding layer, the driving circuit layer and the top layer in a set order; performing lamination processing on the bottom layer, the chip embedding layer, the driving collection layer, the first power layer, the second power layer, the shielding layer, the driving circuit layer and the top layer by using a lamination process to obtain the circuit board.

13. An electronic device, comprising: The circuit board comprises: The circuit board according to any one of claims 1 to 11.

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